JP3560014B2 - Oversampling type A / D converter - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog-to-digital (A / D) converter for converting an analog voltage signal into a corresponding digital signal, and more particularly to an oversampling A / D converter suitable for being realized by a semiconductor integrated circuit. , ΔΣ modulation type A / D converter.
[0002]
[Prior art]
Conventionally, various types of A / D converters, such as a successive approximation type and an oversampling type, have been developed. Generally, when an analog input signal is converted into a digital signal by an A / D converter having no nonlinear distortion, if the input analog input signal is several times the minimum resolution or more, quantization noise is converted from DC to Nyquist frequency (sampling frequency). １ ／) is distributed almost uniformly. For this reason, if the number of quantization bits is equal, the sum of noise power is fixed. Basically, if the sampling frequency is increased, the S / N (Signal to Noise Ratio) characteristics near the signal frequency can be improved. it can. The oversampling A / D converter is a system in which the S / N characteristic is improved by increasing the oversampling ratio (the ratio of the frequency of the sampling clock to the frequency of the signal band).
[0003]
The oversampling type A / D converter includes a modulating means, and the modulating means forms a feedback loop like a successive approximation type A / D converter. That is, it incorporates a quantization means for performing voltage comparison and a D / A converter necessary for feedback. The point that a filter is arranged in a feedback loop is significantly different from other types of A / D converters. However, depending on where the filter is arranged and the positional relationship between signal input points, Δ (delta) modulation is performed. Systems, ΔΣ (delta-sigma) modulation systems, and their mixed systems.
[0004]
Of these, the Δ う ち modulation method integrates the difference between the output signal and the input signal and performs feedback control so that the output of the integration means is minimized. In this ΔΣ modulation method, the order of analog integration, that is, the modulation The S / N characteristics can be further improved by increasing the number of devices. That is, every time the order of the analog integration is increased by one, a noise shaping characteristic (noise reduction) almost inversely proportional to the square of the oversampling ratio can be expected. However, when the order of integration is increased, the ratio of the capacitor is increased, the area of the circuit is increased, the power consumption is increased, and it is difficult to implement a semiconductor integrated circuit. Therefore, a second-order ΔΣ modulation method is generally used. Incidentally, an invention relating to an oversampling type A / D converter of the ΔΣ modulation method is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-294075.
[0005]
[Problems to be solved by the invention]
In a conventional ΔΣ modulation type oversampling A / D converter, for example, as seen in the above-mentioned prior application, a differential type operational amplifier circuit is used, and a voltage comparison means at the last stage uses an analog signal of an analog signal. A 1-bit feedback system in which only the polarity is determined and feedback is provided to the preceding modulation means has been common. The reason is that if the voltage comparison means in the final stage performs voltage comparison with the differential signal as it is and determines not only the polarity but also the level of the amplitude and adopts the multi-bit feedback method, the voltage comparison means becomes very complicated. However, it is not possible to expect a sufficient accuracy. However, the 1-bit feedback method has a problem that the S / N characteristics cannot be sufficiently improved. As a method of improving the S / N characteristics in the oversampling type A / D converter, it is conceivable to increase the sampling frequency. However, such a method causes a problem that the power consumption of the circuit increases. .
[0006]
In recent years, an A / D converter is often mounted on a single chip together with a digital circuit, for example, as in a CODEC (encoder / decoder). There is also a problem that the S / N characteristic of the A / D converter deteriorates due to the substrate noise generated by the operation of the circuit.
[0007]
An object of the present invention is to provide a technique capable of improving the S / N characteristic of an oversampling A / D converter of a ΔΣ modulation system with a relatively simple configuration.
[0008]
Another object of the present invention is to provide a technique capable of improving the S / N characteristics of an oversampling A / D converter of the ΔΣ modulation method without increasing power consumption.
[0009]
Another object of the present invention is to provide an oversampling type A / D converter that can prevent deterioration of S / N characteristics due to substrate noise that occurs when mounted on a single chip together with a digital circuit.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0012]
That is, a ΔΣ modulator comprising an adder for obtaining a difference between an input analog signal and a feedback signal, and a differential integrator for integrating an output signal of the adder, and quantizing the integration result of the integrating means. And a local D / A converter that generates the feedback signal based on the output signal of the quantization means. An analog differential amplifier circuit that amplifies the differential output of the integration unit and outputs the signal as a non-differential signal, and a plurality of output voltages of the analog differential amplifier circuit. And a voltage comparing means for comparing the signal with a reference voltage, and converting a plurality of bits of the signal obtained from the voltage comparing circuit into an analog signal by the local D / A converter. It is intended to be returned.
[0013]
According to the above-mentioned means, the S / N characteristics can be improved by using the differential-type integrating means, and the voltage comparing means can determine a relatively non-differential signal amplitude so that a relatively accurate circuit can be simplified. It can be composed of simple circuits.
[0014]
Preferably, the modulating means includes a first adding means (11a, 11b) for obtaining a difference between the input analog signal and the feedback signal, and a differential first integrating means for integrating an output signal of the first adding means. First modulating means (10) comprising means (13); second adding means (22a, 22b) for obtaining a difference between an output signal of the first integrating means and the feedback signal; and an output signal of the second adding means. And a second-order ΔΣ modulating means including a second modulating means (20) including a differential type second integrating means (24).
[0015]
In the above-described A / D converter, assuming that the sampling frequency is fs, the signal bandwidth is B, the oversampling ratio is K, and the number of bits of the feedback signal is n, the S / A of the first-order ΔΣ modulation A / D converter is used. / N is
S / N = 10Log ｛9 (2 ⁿ -1) ² K ³ / (2π ² )｝
Is represented by Here, K = fs / (2B).
[0016]
The S / N of the A / D converter of the second order ΔΣ modulation method is
S / N = 10Log ｛15 (2 ⁿ -1) ² K ⁵ / (2π ⁴ )｝
It becomes. From the above two equations, if K> 2.43, the S / N of the A / D converter of the second-order ΔΣ modulation method is better than that of the A / D converter of the first-order ΔΣ modulation method. You can see that. Also, from the above equation, it can be seen that the S / N improves as the number of bits of the feedback signal increases. Specifically, for example, in a second-order ΔΣ modulation type A / D converter, the 2-bit feedback improves the S / N by 9.5 dB as compared with the 1-bit feedback (n = 1), and the S / N increases by 3 dB. The bit feedback improves the S / N by 16.9 dB.
[0017]
Further, a first amplifying means (12a, 12b) having a gain Gl set to be smaller than "1" is provided at a stage preceding the first integrating means (13) with the local D / A converter (50). A second amplifying unit (21a, 21b) having a gain Gl substantially equal to that of the first amplifying unit (11a, 11b) is provided between the second adding unit (22a, 22b) and the second integrating unit (24). 3), a third amplifying means (23a, 23b) having a gain G2 set to be smaller than "1" is provided.
[0018]
As described above, by providing the first amplifying means, the second amplifying means, and the third amplifying means having the gains set to be smaller than "1", the outputs are eroded by the respective integrating means and the circuit does not operate. Can be prevented, and the S / N characteristics can be prevented from deteriorating due to variations in the ratio accuracy of the capacitance constituting the integrator, the offset and settling of the operational amplifier, and the like. In the above case, the gain of each of the first amplifying means, the second amplifying means, and the third amplifying means suitable for improving the S / N characteristic is 2/3 or less, more preferably 1/2.
[0019]
Further, the modulation means or the first modulation means and the second modulation means each include a switched capacitor including a sampling capacitor for sampling a corresponding input signal and a plurality of switches for switching terminals of the sampling capacitor. It is preferable to include a capacitor circuit, an operational amplifier, and an integration capacitor for an integration operation. This makes it possible to integrally form the adding means, the integrating means and the amplifying means which constitute the modulator, and the gains of the first amplifying means, the second amplifying means and the third amplifying means correspond respectively. Since the gain can be set by the ratio between the sampling capacity and the integration capacity, the gain can be easily set.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0021]
FIG. 1 shows an embodiment of an oversampling A / D converter of the ΔΣ modulation system according to the present invention.
[0022]
The oversampling type A / D converter shown in FIG. 1 employs a second-order ΔΣ modulation system, and is not particularly limited. However, a single semiconductor substrate such as a single-crystal silicon chip is manufactured by a known semiconductor integrated circuit manufacturing technique. Formed.
[0023]
The oversampling type A / D converter of the embodiment is a differential input / differential output type first ΔΣ modulation circuit that performs integration by taking the difference between the analog input signals X and −X and the feedback signals VR and −VR. 10 and a differential input / differential output type second ΔΣ modulation circuit 20 that performs integration by taking the difference between the differential outputs A1 and -A1 of the first ΔΣ modulation circuit 10 and the feedback signals VR and -VR. A differential input single output analog differential amplifier circuit 30 for amplifying the differential output of the second ΔΣ modulation circuit 20 and outputting the amplified signal as a non-differential signal; and an output voltage of the analog differential amplifier circuit 30 Voltage comparing means 40 for comparing with N (N is an integer of 3 or more) reference voltages, and a local D / A converter 50 for D / A converting an N-bit signal Y obtained from the voltage comparing circuit 40 It is configured.
[0024]
The output signal Y of the voltage comparison means 30 is transmitted to the subsequent circuit as an output signal of the oversampling type A / D converter of this embodiment, and is also transmitted to the local D / A converter 50. The analog signals A / D-converted by the D / A converter 50 are fed back to the ΔΣ modulation circuits 10 and 20 as the feedback signals VR and −VR.
[0025]
The first ΔΣ modulation circuit 10 adds the respective differences between the analog input signals X, −X and the feedback signals VR, −VR, reduces the level of the difference, and transmits the difference to the integration unit 13. It comprises amplification means 12a and 12b having a gain G1 smaller than "1" and a differential type analog integration means 13 for integrating output signals of the amplification means 12a and 12b. The amplification means 12a and 12b having a gain G1 smaller than "1" attenuate the difference and transmit the difference to the integration means 13, thereby preventing the integration means 13 from being saturated. Note that the subtraction means for subtracting b from a can be regarded as an addition means for adding -b to a, and therefore, in this specification, the subtraction means is referred to as an addition means.
[0026]
The second ΔΣ modulation circuit 20 includes amplifiers 21a and 21b having the same gain G1 as the amplifiers 12a and 12b, and a signal G1 in which the levels of the feedback signals VR and −VR are reduced by the amplifiers 21a and 21b. ... VR, G1... -VR and the differential means A1 and -A1 of the first ΔΣ modulation circuit 10 to obtain a difference between the first and second differential outputs A1 and -A1, and the difference is attenuated and transmitted to the integrating means 24. It comprises amplifiers 23a and 23b having a smaller gain G2 and a differential analog integrator 24 for integrating the output signals of the amplifiers 23a and 23b.
[0027]
Amplifying means 21a and 21b having the same gain G1 as the amplifying means 12a and 12b are provided to supply signals G1.VR and G1.-VR with reduced feedback signals VR and -VR to the adding means 22a and 22b. As a result, the level of the feedback signal and the level of the differential outputs A1 and -A1 of the first ΔΣ modulation circuit 10 can be matched, and the difference is amplified by the amplifying means 23a and 23b having a gain G2 smaller than “1”. By transmitting the signal to the integrating means 24 after being attenuated, it is possible to prevent the integrating means 24 from being saturated.
[0028]
Further, in this embodiment, the gain G3 of the analog differential amplifier circuit 30 that converts the differential outputs A2 and -A2 of the second ΔΣ modulation circuit 20 to a non-differential signal is also set to a value smaller than “1”. I have. As a result, the analog differential amplifier circuit 30 is also prevented from being saturated. Desirable values of the gains G1, G2, and G3 are 2/3 or less, and more preferably 1/2. Further, when N = 3, a preferable relation of the reference voltage of the comparison means 40 is Vr / 2, 0, -Vr / 2. The preferred value of the output signal of the local D / A converter 50, that is, the feedback signal VR when N = 3 is VR = Vr when the output A3 of the analog differential amplifier circuit 30 is Vr / 2 ≦ A3. , VR = Vr / 4 when 0 ≦ A3 ≦ Vr / 2, VR = −Vr / 4 when −Vr / 2 ≦ A3 ≦ 0, and VR = −Vr when A3 ≦ −Vr / 2. .
[0029]
FIG. 2 shows a specific circuit configuration example of the first ΔΣ modulation circuit 10 including the adding means 11a and 11b, the amplifying means 12a and 12b, and the integrating means 13 shown in FIG. As shown in FIG. 2, the adding means 11a and 11b, the amplifying means 12a and 12b, and the integrating means 13 include a switched capacitor circuit including sampling capacitors Cs1 to Cs4 and switches SW1 to SW8 for switching terminals thereof. And an operational amplifier (operational amplifier) OP1 and integration capacitors Ci1 and Ci2.
[0030]
One end of the sampling capacitor Cs1 is connected to a terminal 31 to which the input signal X1 is input via a switch SW1 or a constant potential point such as analog ground, and the other end of the sampling capacitor Cs1 is connected to an operational amplifier via a switch SW2. Connected to the inverting input terminal or constant potential point of OP1. One end of the sampling capacitor Cs2 is connected to a terminal 32 to which the feedback signal VR is input via a switch SW3 or a constant potential point such as an analog ground, and the other end of the sampling capacitor Cs2 is connected to a switch SW4. Connected to the inverting input terminal or constant potential point of the operational amplifier OP1.
[0031]
On the other hand, one end of the sampling capacitor Cs3 is connected to a terminal 33 to which the input signal -X1 is input or a constant potential point such as analog ground via the switch SW5, and the other end of the sampling capacitor Cs3 is connected to the switch SW6. It is connected to a non-inverting input terminal of the operational amplifier OP1 or a constant potential point via the operational amplifier OP1. One end of the sampling capacitor Cs4 is connected to a terminal 34 to which a feedback signal -VR is input via a switch SW7 or a constant potential point such as analog ground, and the other end of the sampling capacitor Cs4 is connected to a switch SW8. It is connected to a non-inverting input terminal of the operational amplifier OP1 or a constant potential point via the operational amplifier OP1.
[0032]
The ΔΣ modulation circuit 10 of this embodiment sets the capacitance values of the sampling capacitances Cs1 to Cs4 to a gain multiple (G1 times) of the integral capacitance value C1, that is, G1 ・, where C1 is the capacitance value of the integration capacitances Ci1 and Ci2. The gain G1 can be set by setting C1, that is, by the capacitance ratio between the integration capacitors Ci1 and Ci2 and the sampling capacitors Cs1 to Cs4.
[0033]
In the ΔΣ modulation circuit 10 of this embodiment, a sampling state and an integration state are formed depending on the states of the switches SW1 to SW8. In the sampling state, as shown in FIG. 2, the switches SW1 and SW5 are connected to the input terminals 31 and 33, and the switches SW2, SW3 and SW4; SW6, SW7 and SW8 are connected to the constant potential point. At this time, charges based on the analog signals X1 and -X1 input from the input terminals 31 and 33 are accumulated in the sampling capacitors Cs1 and Cs3.
[0034]
The integration state is a state in which the switches SW1 to SW8 are connected to terminals opposite to those shown in FIG. In this integration state, one terminal of the sampling capacitors Cs2 and Cs4 is connected to the input terminals 32 and 34 of the feedback signals VR and -VR, the other terminals of the sampling capacitors Cs1 and Cs2 are connected to the inverting input terminal of the operational amplifier OP1, and The other terminals of the sampling capacitors Cs3 and Cs4 are connected to the non-inverting input terminal of the operational amplifier OP1. As a result, the charge sampled in the sampling state and the charges of the feedback signals VR and -VR are added, and the integration result at that time appears at the output terminal of the operational amplifier OP1.
[0035]
The switches SW1 to SW8 are switched by clocks φ1 and φ2 that change at the timings shown in FIG. 3, and the sampling state (see FIG. 2) and the integration state are alternately repeated, so that analog signals are obtained. The addition (subtraction) of the input signals X1, -X1 and the feedback signals VR, -VR from the local D / A converter 50 and the integration of the difference are performed simultaneously. When two consecutive sampling timings are represented by n and n + 1, the output A1 (n + 1) at the timing n + 1 of the circuit of FIG.
A1 (n + 1) = G1 (X1 (n) -VR (n)) + A1 (n)
become that way.
[0036]
According to the above equation, the integrated charge amount increases if the levels of the input signals X1 and -X1 are higher than the levels of the feedback signals VR and -VR transmitted from the local D / A converter 50, and decreases if the levels are lower. It is understood that it is done.
[0037]
FIG. 4 shows a specific circuit configuration example of the second ΔΣ modulation circuit 20 shown in FIG. As shown in FIG. 4, the amplifying units 21a and 21b, the adding units 22a and 22b, the amplifying units 23a and 23b, and the integrating unit 24 shown in FIG. , An operational amplifier (operational amplifier) OP2, and integrating capacitors Ci11 and Ci12. That is, the circuit type is the same as that of the first ΔΣ modulation circuit 10 shown in FIG. Clocks for operating the switches SW11 to SW18 are φ1 and φ2 shown in FIG. 3 similarly to the circuit of FIG. 2, and operate in the same manner.
[0038]
The second ΔΣ modulation circuit 20 differs from the first ΔΣ modulation circuit 10 in that the sampling capacitances Cs1 to Cs4 have the same capacitance value and the integration capacitances Ci1 and Ci2 in the first ΔΣ modulation circuit 10 of FIG. While the value C1 is set to G1 times, in the second ΔΣ modulation circuit 20 of FIG. 4, the sampling capacitances Cs11 and Cs13 are set to G2 times the value C2 of the integration capacitances Ci11 and Ci12 with the same capacitance value. The point is that the capacitances Cs12 and Cs14 have the same capacitance value and are G1 · G2 times the integral capacitance value C2.
[0039]
The sampling state in which the switches SW11 to SW18 are switched to the side shown in FIG. 4 and the integration state in which the switches SW11 to SW18 are switched to the side opposite to FIG. Of the feedback signals VR, -VR from the converter 50 (G1 times) and the output signals A1, -A1 of the first ΔΣ modulation circuit 10 and the feedback signals VR, -VR from the local D / A converter 50. Addition (subtraction) and integration of the difference are performed simultaneously. When two consecutive sampling timings are represented by n and n + 1, the output A2 (n + 1) at the timing n + 1 of the circuit in FIG.
A2 (n + 1) = G2 (X1 (n) -G1.VR (n)) + A2 (n)
become that way.
[0040]
FIG. 5 shows a specific circuit configuration example of the analog differential amplifier circuit 30 and the voltage comparison circuit 40 shown in FIG. As shown in FIG. 5, the analog differential amplifier circuit 30 includes a switched capacitor circuit including sampling capacitors Cs21 and Cs22 and switches SW21 to SW24 for switching terminals thereof, an operational amplifier (operational amplifier) OP3, And a feedback capacitor Cf connected between the output terminal and the inverting input terminal of the operational amplifier OP3 and a switch SW25 in parallel with the feedback capacitor Cf. The non-inverting input terminal of the operational amplifier OP3 is connected to a constant potential point such as an analog ground.
[0041]
The voltage comparison circuit 40 includes, for example, three (when N = 3) comparators CMP1 to CMP3, and outputs the output voltage of the analog differential amplifier circuit 30 to the non-inverting input terminals of these comparators CMP1 to CMP3. A3 is commonly input, and Vr / 2, 0, and -Vr / 2 are input to the inverting input terminals as reference voltages, respectively.
[0042]
The analog differential amplifier circuit 30 includes a first state in which the switches SW21 to SW25 are switched to the side as illustrated in FIG. 5 by the clocks φ2 and φ3 with the timing illustrated in FIG. By controlling the SW 25 to alternately repeat the second state in which the SW 25 is switched to the side opposite to FIG. 5, the difference between the differential output signals A2 and -A2 of the second ΔΣ modulation circuit 20 is amplified, and the difference is amplified. It outputs a non-moving signal A3 (= 2G3 · A2). The gain G3 of the analog differential amplifier circuit 30 is determined by the ratio between the sampling capacitors Cs21 and Cs22 and the feedback capacitor Cf. Specifically, assuming that the capacitance value of the feedback capacitance Cf is C3, the capacitance value of the sampling capacitances Cs21 and Cs22 is set to be a gain multiple thereof, that is, G3 · C3.
[0043]
The voltage comparison circuit 40 operates at a timing such as the clock φ4 shown in FIG. Accordingly, each of the comparators CMP1 to CMP3 of the voltage comparison circuit 40 compares the output A3 of the analog differential amplifier circuit 30 with the reference voltages Vr / 2, 0, and -Vr / 2, and according to the magnitude relationship, It outputs 3-bit signals Y (0,1), Y (0,0), Y (0, -1).
[0044]
FIG. 5 shows an embodiment in which the analog differential amplifier circuit 30 is configured using a switched capacitor circuit. However, as shown in FIG. R2, an operational amplifier OP4, a resistor R3 connected between a non-inverting input terminal of the operational amplifier OP4 and a ground point (analog ground), and a feedback resistor connected between an output terminal and an inverting input terminal of the operational amplifier OP3. R4. In this case, the gain of the circuit is set by designing the resistance value of the feedback resistance Rf and the resistance R3 on the non-inverting input terminal side of the operational amplifier to a gain (G3 times) of the resistance value r of the input resistances R1 and R2. be able to.
[0045]
According to the above embodiment, the following effects can be obtained.
[0046]
(1) In an oversampling type A / D converter including a ΔΣ type modulation unit, a quantization unit, and a local D / A converter, the oversampling type A / D converter includes a differential output of the integration unit. And a voltage comparison means for comparing the output voltage of the analog differential amplifier circuit with a plurality of reference voltages, and a plurality of signals obtained from the voltage comparison circuit. Since the bit signal is converted to an analog signal by the local D / A converter and fed back to the modulation means, the voltage comparison circuit needs a relatively high precision circuit to determine the amplitude of the non-differential signal. A simple circuit can be used, and the S / N characteristics can be improved. In addition, the S / N characteristics can be improved without increasing the sampling frequency so much.
[0047]
(2) When the modulation means is a secondary ΔΣ modulation means, the S / N characteristics can be improved as compared with the primary ΔΣ modulation means, and the capacitance ratio can be improved as compared with the case where the modulation means is a third-order or higher. Is not so large, which is suitable for forming a semiconductor integrated circuit.
[0048]
(3) By setting the gain Gl of the first amplifying means, the second amplifying means and the third amplifying means to approximately １ ／, the saturation of the operational amplifying means in the first integrating means and the second integrating means is suppressed, and S / N characteristics can be further improved.
[0049]
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. For example, similarly to the analog differential amplifier circuit 30, the first and second ΔΣ modulation circuits 10 and 20 in the embodiment can be configured using resistors instead of switched capacitor circuits. Further, the present invention can be applied not only to a secondary modulation scheme but also to an oversampling A / D converter of a third or higher modulation scheme.
[0050]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0051]
That is, in an oversampling type A / D converter of a ΔΣ modulation system, an analog differential amplifier circuit that uses a modulating means of differential input and differential output and amplifies a differential output of the modulating means to output as a non-differential signal. And a voltage comparing means for comparing the output voltage of the analog differential amplifier circuit with a plurality of reference voltages. The local D / A converter converts the multi-bit signal obtained from the voltage comparing circuit into an analog signal. As a result, the voltage comparison circuit determines the amplitude of the non-differential signal, so that a relatively accurate circuit can be constituted by a simple circuit and the S / N characteristic is improved. be able to. Further, according to the present invention, it is possible to prevent deterioration of the S / N characteristics due to substrate noise generated when the digital circuit is mounted on one chip together with the digital circuit.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of an embodiment of an oversampling type A / D converter according to the present invention.
FIG. 2 is a circuit diagram showing a specific example of a first ΔΣ modulation circuit in the oversampling A / D converter.
FIG. 3 is a timing chart showing the timing of a clock for operating the oversampling A / D converter.
FIG. 4 is a circuit diagram showing a specific example of a second ΔΣ modulation circuit in the oversampling A / D converter.
FIG. 5 is a circuit diagram showing a specific example of an analog differential amplifier circuit in the oversampling A / D converter.
FIG. 6 is a circuit diagram showing another specific example of the analog differential amplifier circuit in the oversampling A / D converter.
[Explanation of symbols]
10 First ΔΣ modulation circuit
11a, 11b Addition means
12a, 12b Amplifying means
13 Analog integration means
20 Second ΔΣ modulation circuit
21a, 21b adding means
22a, 22b adding means
23a, 23b Amplifying means
24 Analog integration means
30 Analogue differential amplifier circuit with differential input and single output
40 Voltage comparison means
50 Local D / A converter
VR, -VR feedback signal

Claims (1)

ΔΣ modulation means comprising a set of addition means for obtaining a difference between the input differential analog signal and the differential feedback signal, and a differential integration means for integrating the differential output signal of the addition means; An analog differential amplifier circuit for amplifying the differential output of the modulating means and outputting the amplified signal as a non-differential signal; And a local D / A converter for converting a non-differential multi-bit signal obtained from the voltage comparison circuit into an analog signal and generating a differential feedback signal to be fed back to the modulation means. An oversampling A / D converter formed on a semiconductor chip,
The modulating means includes a set of first adding means for obtaining a difference between the input differential analog signal and the differential feedback signal, and a differential type integrating the differential output signal of the first adding means. A first modulating means comprising a first integrating means; a set of second adding means for obtaining a difference between a differential output signal of the first integrating means and the differential feedback signal; A second modulating means comprising a differential type second integrating means for integrating a differential output signal, and a second order ΔΣ modulating means comprising:
The analog differential amplifier circuit includes a switched capacitor circuit including a sampling capacitor and a switch for switching its terminal, an operational amplifier, and a feedback capacitor connected between an output terminal and an inverting input terminal of the operational amplifier. And a switch provided in parallel with this,
A set of first amplifying means having a gain set to be smaller than "1" is provided in a stage preceding the first integrating means, and a gain set to be smaller than "1" is provided in a stage preceding the second integrating means. A set of second amplifying means is provided,
The first modulation means and the second modulation means each include a switched capacitor circuit including a sampling capacitor for sampling a corresponding input signal and a plurality of switches for switching terminals of the sampling capacitor. An amplifier and an integration capacitor for an integration operation, wherein the gains are respectively set by a capacitance ratio between the integration capacitance and the sampling capacitance, and the second modulation is performed when the first modulation means is in a sampling state. The means is in an integration state, the first modulation means is in an integration state when the second modulation means is in a sampling state, and after the integration operation in the second modulation means, the analog differential amplifier circuit is in the state of integration. Amplifying the integral output of the second modulating means, and after the amplifying operation of the analog differential amplifier circuit, the voltage comparing means Oversampling A / D converter and performs.

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