JP3559116B2 - Apparatus for testing sensitivity of input amplifier in semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test apparatus for testing the sensitivity of an input amplifier in a semiconductor device.
[0002]
[Prior art]
Of the input amplifiers provided in the semiconductor device, those output from the semiconductor device in the same form as the output of the amplifier have been tested for the sensitivity of the amplifier by an analog tester.
[0003]
[Problems to be solved by the invention]
However, for example, in semiconductor devices, such as the output of the input amplifier 32 as shown in FIG. 2 are counted by the counter 33, the output terminal O _1, O _2, the voltage occurring · · · O ₈ and the output of the input amplifier 32 Since the form is completely different, it cannot be discriminated by the analog tester.
[0004]
An object of the present invention is to provide an apparatus for testing the sensitivity of an input amplifier in a semiconductor device in which the output of the input amplifier is converted into a different signal form and output.
[0005]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, in a test apparatus for testing the sensitivity of an input amplifier in a semiconductor device having an input amplifier and a digital circuit which operates by an output of the input amplifier and outputs digital data, A logic tester for outputting; a level attenuating circuit for attenuating an output level of the logic tester to be applied to an input terminal of the semiconductor device; and a means for guiding output data of the semiconductor device to the logic tester. The logic tester has a function of determining the sensitivity of the input amplifier based on output data from the semiconductor device. In this case, the attenuation circuit is provided on a test board on which the semiconductor device is mounted, and is connected to a logic tester via the test board.
[0006]
According to such a test apparatus, the output voltage of the logic tester is input to the semiconductor device at a lower level than usual. At this time, if the input amplifier in the semiconductor device has normal sensitivity, the output data of the digital circuit becomes normal data, so that the judgment result becomes good. However, if the sensitivity of the input amplifier is poor or insufficient, the digital circuit does not operate normally, and its output data is different from the expected one, so that the input amplification sensitivity is determined to be poor. You.
[0007]
Further, according to the present invention, in a test apparatus for testing the sensitivity of the input amplifier in a semiconductor device having an input amplifier for amplifying a pulse and a counter for counting the pulse amplified by the input amplifier, the pulse is supplied to the input amplifier. A pulse supply circuit for supplying; a comparison circuit for comparing the output voltage of the counter with a reference voltage; a means for giving an expected pattern expected in advance; a comparison logic circuit for comparing the output of the comparison circuit with the expected pattern; A judgment circuit for judging pass / fail of the input amplifier based on an output of the comparison logic circuit;
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Reference numeral 1 denotes a logic tester, which includes a main unit 1A, a cable 1B, and a test station (test head) 1C.
[0009]
The main unit 1A includes a pattern generator 4 having a pattern memory 5, a timing generator 6, a waveform shaping circuit 7 for shaping output data from the pattern generator 4, and a test board 17 via a test station 1C. An input voltage generating circuit 8 for generating an input voltage applied to the test station 17; a reference voltage generating circuit 9 for generating a reference voltage for comparing whether or not the level of output data applied from the test board 17 to the test station 1C is sufficient; A logical comparison circuit 10 for comparing whether or not the comparison result matches an expected pattern in advance, a file memory 11 for filing the result, a pass / fail judgment circuit 12, a pass / fail display unit 13, a sample (in this case, And a sample power supply 14 for supplying a power supply voltage for the semiconductor device 30).
[0010]
On the other hand, a test circuit 1C is provided with a driver circuit 15 and a comparison circuit 16. The driver circuit 15 includes two analog switches 23 and 24 as shown in FIG. The input terminals 21 and 22 of these analog switches 23 and 24 are connected to the input voltage generating circuit 8, and a high level (for example, 5 V) DC voltage is applied to the input terminal 21 as shown in FIG. The input terminal 22 is supplied with a low-level (for example, 0 V) DC voltage as shown in FIG.
[0011]
The output sides of these analog switches 23 and 24 are commonly connected to an output terminal 25. The control terminal 20 is supplied with a pulse signal as shown in FIG.
[0012]
Assuming that the analog switch 23 is turned on during the high level period of the pulse signal and the analog switch 24 is turned on during the low level period, the output terminal 25 is connected to the output terminal 25 as shown in FIG. A pulse having a peak value of 5 V and a pulse width corresponding to the pulse width of (c) is generated.
[0013]
The analog switch 24 may be turned on when the control pulse (c) is at a high level, and the analog switch 23 may be turned on when the control pulse (c) is at a low level. In such a case, the output pulse (d) becomes the control pulse (c) ) Is 180 ° out of phase. Further, the low level voltage applied to the input terminal 22 may be, for example, 1 V instead of 0 V. In this case, the low level of the output pulse (d) also becomes 1 V.
[0014]
The output pulse of the driver circuit 15 is reduced to about several mV by an attenuation circuit 18 provided on a test board 17 and then applied to an input terminal 31 of a semiconductor device 30 shown in FIG. Attenuating circuit 18 and the input terminal 26 for receiving a pulse from the output terminal 25 of the driver circuit 15 as shown in FIG. 3, an attenuator 27, comprises a resistor R _1, a decoupling capacitor C ₁ and the output terminal 28. ing. Since generally the driver circuit 15 of the logic tester 1 is formed so that the output resistance is 50 [Omega, we used 50 [Omega resistor as a termination resistor R ₁ of the damping circuit 18.
[0015]
As described above, by providing the attenuation circuit 18, a minute pulse having a peak value of about several mV can be supplied to the semiconductor device 30. When the output of the driver circuit 15 of the logic tester 1 is set to directly output several mV, it is not necessary to prepare the attenuation circuit 18. However, when a logic tester having such a small output is formed, the logic tester cannot be used for testing other circuits. At present, the driver output amplitude of a logic tester is generally several hundred mV or more.
[0016]
This is because many CMOS semiconductor devices adopt the form of input of several volts, and testing of a circuit having no amplifier 32 as shown in FIG. Therefore, it is generally advisable to connect the attenuator 18 only when testing the input amplifier 32 in a semiconductor device of the type shown in FIG. It is.
[0017]
Now, the input amplifier 32 of the semiconductor device 30 to which a pulse of several mV is given to the input terminal 31 amplifies the input pulse to about several V and supplies it to the counter 33 in the next stage. Assuming that the output of the counter 33 is 8 bits, each bit is led out to 8 output terminals O ₁ , O ₂ ,..., O ₈ respectively.
[0018]
The comparison circuit 16 of the test station 1C receives the signals of the output terminals O ₁ , O ₂ ,..., O ₈ of the device 30 and determines whether the voltage of each bit has reached the reference value. Compare with value. FIG. 5 shows a comparator for one bit (one PIN) in the comparison circuit 16. When the output data is 8 bits, the comparison circuit 16 uses eight sets of the circuit shown in FIG.
[0019]
In FIG. 5, the comparator 42 has a high-level threshold, and the comparator 43 has a low-level threshold. Here, the high-level threshold is 4 V, and the low-level threshold is 1 V (these voltages are supplied from the reference voltage generation circuit 9).
[0020]
Now, the input terminal 41 is connected to the output terminal O _1, when the signal from the output terminal O ₁ is expected to be a logical "1", only the output of the high-level side comparator 42 Is used for the determination. The signal voltage from the output terminal O ₁ is higher than 4V, the high level side of the comparator 42 "1" is output. If the voltage is lower than 4 V, "0" is output from the comparator 42. When "0" is output, the sensitivity of the amplifier 32 is insufficient, and the main body 1A determines that the amplifier 32 is defective.
[0021]
On the other hand, when the signal from the output terminal O ₁ is expected to be a logic "0", only the output of the low-level side of the comparator 43 is used to determine. At this time, if the signal voltage from the output terminal O ₁ is lower than 1 V, the comparator 43 outputs “0”. If it is higher than 1V, "1" is output. When "1" is output, it is determined that the data is defective.
[0022]
As described above, since one of the comparators 42 and 43 does not need the other output when one of the outputs is used for the pass / fail judgment, only the necessary one may be activated and the unnecessary one may be deactivated. However, in the embodiment of FIG. 5, both are always operated. As described above, when both comparators are operating at the same time, the logical comparison circuit 10 and the pass / fail judgment circuit 12 of the main unit 1A select the necessary one of the outputs of the comparators 42 and 43.
[0023]
The outputs of the comparators 42 and 43 are first compared with the pattern from the pattern generator 4 in the logic comparison circuit 10. Prior to this, for example, 1 bit of the output of the counter 33 (the signal at the output terminal O ₁₎ is either a "1" or "0" is previously expected body 1A side. This is because the number of pulses output from the waveform shaping circuit 7 can be known from the timing signal from the timing generator 6, and the output of the counter 33 that counts input pulses depends on the number of input pulses. It determines the value of the output terminal O ₁ is because seen in the main body 1A side should be a logic "1" level, or should be "0" to send a pulse.
[0024]
Therefore, from the pattern generator 4 wherein in synchronism with the timing signal as an expected value of the signal at the output terminal O ₁ "1" or "0" is sent to the logical comparison circuit 10. The expected value “1” is compared with the actual binary data of the signal at the output terminal O ₁ (output as “1” or “0” by the comparison circuit 16) by the logic comparison circuit 10, and whether the two match each other is determined. It is determined whether or not.
[0025]
As described above, the comparison circuit 16 compares the 8-bit output signals from the counter 33 at the same time, and sends the result to the logical comparison circuit 10. On the other hand, the pattern generator 4 also sends an 8-bit logical pattern to the logical comparison circuit 10 for each pulse output. Then, the logic comparison circuit 10 performs logic comparison on eight bits at the same time.
[0026]
Each time a pulse is transmitted from the main unit 1A, the logical comparison circuit 10 receives a new logical pattern and a new count output and performs comparison. The result is stored in the file memory 11 and determined by a pass / fail determination circuit, and the determination result is displayed on the display unit 13. It should be noted that how many pulses are subjected to the logical comparison to determine whether the sensitivity of the input amplifier 32 is good or not may be determined arbitrarily.
[0027]
In FIG. 1, printed wiring is provided on a test board 17 so that an attenuation circuit 18 can be assembled. In addition, a connection between the attenuation circuit 18 and a semiconductor device 30 (in this case, a test sample) and a main body are provided. The power supply from the 1A sample power supply 14 is also performed via the printed wiring.
[0028]
【The invention's effect】
As described above, according to the present invention, even if the output of the input amplifier is converted into another form and output, the sensitivity of the input amplifier can be reliably tested.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram of an embodiment of a test apparatus of the present invention.
FIG. 2 is a block circuit diagram of a semiconductor device as a sample to be tested by the test apparatus of the present invention.
FIG. 3 is an attenuation circuit for attenuating an output level of a logic tester for a test apparatus and supplying the output to a sample.
FIG. 4 is a configuration diagram of a driver circuit of a logic tester for a test apparatus.
FIG. 5 is a circuit diagram showing a part of a comparison circuit of a logic tester for a test apparatus.
FIG. 6 is a signal waveform diagram for explaining the operation of the driver circuit of the logic tester.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Logic tester 1A Main body 1B Cable 1C Test station 4 Pattern generator 6 Timing circuit 7 Waveform shaping circuit 8 Input voltage generation circuit 10 Logic comparison circuit 12 Pass / fail judgment circuit 13 Display unit 15 Driver circuit 16 Comparison circuit 17 Test board 18 Attenuation circuit 30 Semiconductor device 32 Input amplifier 33 Counter O ₁ , O ₂ ,..., O ₈ Output terminals 42 and 43 of semiconductor device Comparator

Claims (3)

A test apparatus for testing the sensitivity of an input amplifier in a semiconductor device having an input amplifier and a digital circuit operating by an output of the input amplifier and outputting digital data,
A logic tester that outputs pulses,
A level attenuating circuit that attenuates an output level of the logic tester and applies the attenuated output level to an input terminal of the semiconductor device;
Means for guiding output data of the semiconductor device to the logic tester,
And the logic tester has a function of determining the sensitivity of the input amplifier based on output data from the semiconductor device ,
A test apparatus, wherein the attenuation circuit is provided on a test board on which the semiconductor device is mounted, and is connected to a logic tester via the test board . An input amplifier for amplifying a pulse, and a test apparatus for testing the sensitivity of the input amplifier in a semiconductor device having a counter for counting the pulse amplified by the input amplifier,
A pulse supply circuit for supplying a pulse to the input amplifier;
A comparison circuit for comparing the output voltage of the counter with a reference voltage,
Means for giving an expected pattern expected in advance;
A logical comparison circuit that compares the output of the comparison circuit with the expected pattern;
A judgment circuit for judging pass / fail of the input amplifier based on an output of the logical comparison circuit;
A test apparatus comprising: 3. The test apparatus according to claim 2 , wherein the output of the counter includes a plurality of bits, and the comparison circuit compares each bit of the output of the counter with the reference voltage.

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