JP3557359B2 - Image signal playback device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image signal reproducing apparatus for reproducing a still image captured by an electronic still camera or the like.
[0002]
[Prior art]
An electronic still camera in which an image signal is read out by storing it in a magnetic recording medium or memory instead of a silver-lead film and displayed on a television monitor, or output to a printer to be hard-copied for viewing. Has been put to practical use.
[0003]
Such electronic still cameras record image information as analog signals on a floppy disk-shaped video floppy, and also record digital information on a recording medium as a digital signal.On the other hand, image data has a very large amount of information. In general, various types of information compression are applied to a recording medium, encoded, and recorded.
[0004]
Since the signal thus compressed is coded, it cannot be returned to an image signal without decoding. Therefore, conventionally, a processor for image reproduction is prepared for the decoding process, and at the time of reproduction, compression-encoded data of an image to be reproduced is read as shown in FIG. It is necessary to input a compressed image signal to a processor for decoding to perform decoding processing. This was done every frame.
[0005]
[Problems to be solved by the invention]
As described above, in the electronic still camera, in order to compress, encode, and record an image signal, it is necessary to perform a decoding process during reproduction. Further, since the algorithm at the time of encoding is complicated in order to increase the compression ratio of an image, such a conventional decoding process is also complicated, and an enormous amount of arithmetic processing is required.
[0006]
Therefore, if the processing center of the image reproducing processor is constituted by a general-purpose 8-bit to 16-bit microprocessor, it takes a long processing time to decode one image.
[0007]
On the other hand, the number of still images recorded on a recording medium is about 50 frames, and it is necessary to reproduce and display one frame or one frame to find a desired frame.
[0008]
From the viewpoint of usability, it is desirable that the time required for switching images when searching for frames is as short as possible.However, since the decoding process is performed each time the image is switched, even if an attempt is made to search at high speed, at least There is a drawback that the user has to wait for the time required for the decoding process and lacks operability.
[0009]
Therefore, an object of the present invention is to make it possible to continuously reproduce an image on a recording medium at a high speed, and to efficiently retrieve an image even when there are images with a large number of frames, such as an electronic still camera. An object of the present invention is to provide an image signal reproducing device that is optimal for reproduction.
[0010]
[Means for Solving the Problems]
To achieve the above object, the present invention is configured as follows. That is, when a recording medium on which encoded data obtained by compressing and encoding image information is recorded is applied, in response to a control command, the encoded data is read from the recording medium, decoded, and Display image data generating means for sequentially generating display image data of a basic digital mode for each unit image and storing the display image data in a predetermined image display memory having a storage capacity for a plurality of images;
Signal conversion means for sequentially reading and converting the digital display image data stored in the display image memory into an analog form, generating and outputting a video signal for image display,
Operation command means for issuing an operation command signal for displaying an image based on a predetermined operation by the operator,
A first control in which the display image data generating means sequentially generates the display image data and stores the display image data in the image display memory; And then In response to one operation command signal from the operation command means, the signal conversion means generates and outputs a video signal for image display based on the display image data stored in the image display memory. And executing the second control, and responding to the one operation command signal. one time After the second control is performed, do not wait for another operation command signal. First And control means configured to execute the first control immediately after the completion of the second control.
[0011]
Further, the control means is configured to execute the first control without waiting for a separate operation for displaying an image by an operator.
[0012]
That is, the display image data generating means reads out the encoded data from the recording medium on which the encoded data obtained by compressing and encoding the image information is recorded in response to the control command, decodes the encoded data, and decodes the encoded digital data as the basis of the display image. The display image data of the mode is sequentially generated for each unit image, the display image data is stored in a predetermined image display memory having a storage capacity for a plurality of images, and the signal conversion unit is stored in the display image memory. The display image data in the digital form is sequentially read and converted into an analog signal, and a video signal for image display is generated and output.
[0013]
The control means is capable of a first control for causing the display image data generating means to sequentially generate the display image data and store the display image data in the image display memory, Executing the first control, and Upon receiving one operation command signal obtained by operating the operation command means, the signal conversion means generates a video signal for image display based on the display image data stored in the image display memory. Control to output Together with , Then without waiting for another operation command signal right away The first control is executed.
[0014]
In the device of the present invention, when the operator operates the operation command means for displaying an image, the image data stored in the image display memory is stored. Decrypted Since the generation and output of video signals based on display image data is repeatedly performed one after another, images on a recording medium can be continuously reproduced at high speed even when there are a large number of frames. You can search images well.
[0015]
When the control means is provided with a function of performing the first control without waiting for a separate operation for displaying an image by an operator, the control means may include the display image data generating means. Then, the generation of the display image data and the storage of the display image data in the image display memory are sequentially performed, so that the time-consuming decoding of the coded data effectively uses the idle time. From that In addition, images in a recording medium can be continuously reproduced at high speed, and images can be searched efficiently.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention sequentially decodes each image and saves the decoded image data in the frame memory even when a display operation command is not received, and performs time-consuming decoding using an idle time. By performing the processing, the image signal of the frame image can be obtained at any time by reading from the frame memory, so that time-consuming decoding processing can be omitted at the time of reproduction. An embodiment of the present invention will now be described with reference to the drawings, in which images can be continuously reproduced at high speed.
[0017]
FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a memory cartridge, 2 is a connector, 4 is a decoder, 6 is a frame memory, 5 is a write address selection circuit, and 7 is a read address selection circuit. , 8 is a digital-analog converter, 10 is a control circuit, and 13 is an input device such as a keyboard. These are provided in the electronic still camera main body or the reproduction processor main body.
[0018]
The memory cartridge 1 in FIG. 1 is a cartridge mounted with a rewritable digital storage element such as an SRAM (Static Random Access Memory) semiconductor memory or an EEPROM (Electrically Erasable Read Only Memory). Is stored. Since this image data has a huge amount of image data per frame, compression-encoded data is used.
[0019]
Here, the compression-encoded image data refers to orthogonal transform (discrete cosine transform, Hadamard transform, KL transform, discrete Fourier transform, etc.) or entropy encoding (Huffman code, arithmetic code, run code) for predictive coding. (Length code, etc.), adaptive processing on them, or combination of vector quantization.
[0020]
The connector 2 is provided on the main body of the digital electronic still camera or the processor for reproduction. The memory cartridge 1 can be detachably mounted on the main body of the digital electronic still camera or the main body for reproduction by the connector 2.
[0021]
Note that the memory cartridge is a storage medium and a cartridge on which a semiconductor memory is mounted. However, a storage medium in another form capable of digital storage such as a floppy disk may be used.
[0022]
The decoder 4 decodes the signal 3 read from the memory cartridge 1, and the frame memory 6 stores the decoded image data in frame units. In this system, it is assumed that the frame memory 6 has a capacity for storing image data for n sheets.
[0023]
The address selection circuit 5 is a circuit for selecting a write address in the frame memory 6. The frame memory 6 stores the image data decoded by the decoder 4 at the address specified by the write address selection circuit 5. is there.
[0024]
The read address selection circuit 7 is a circuit for selecting a read address in the frame memory 6. One frame is sequentially read from the address specified by the circuit 7, and image data is read from the frame memory 6 for one frame. Read out the appropriate image data.
[0025]
The digital / analog converter 8 (hereinafter abbreviated as DAC) is a signal conversion circuit that converts image data output from the frame memory 6 into an analog signal and outputs the analog signal to an output terminal 9 as a device output.
[0026]
The output terminal 9 is connected to a device that outputs a video signal as a visible image, such as a video monitor or a video printer.
[0027]
The control circuit 10 plays a central role in the overall control of the present system. After transmitting a read request signal from the memory cartridge 1 together with the address of the image data in the memory cartridge 1, the control circuit 10 decodes the read request signal to the decoder 4. , A command is sent to the write address selection circuit 5 to designate the address of the decoded data to be stored in the frame memory 6, or the read address in the frame memory 6 is read. Is given to the read address selection circuit 7 or a control command for the DAC 8 is designated.
[0028]
The write address selection circuit 5 sends the address of the decoded data to be stored in the frame memory 6, and changes the write address after one screen is stored at a predetermined position in the frame memory 6. Thereafter, the image data is read from the memory cartridge 1 again.
[0029]
The read address selection circuit 7 is a circuit for selecting and specifying a read address at the time of image reproduction. When the image at the address specified by the read address selection circuit 7 is read from the frame memory 6 and a reproduction image switching signal is received from the control circuit 10, The read address selection circuit 7 changes the read address to an address of another frame.
[0030]
By doing so, it is possible to switch and display the image once decoded by switching to the image of another frame only by changing the read address of the frame memory 6 at the time of reproduction, so that the displayed image can be switched at high speed. is there.
[0031]
Further, when the control circuit 10 receives the display operation command, the processing for displaying the first image is completed, and if an idle time occurs, the next image is immediately decoded and the decoded image data is decoded. Is sequentially stored in the frame memory 6 so that an image not displayed in the frame memory 6 can be decoded and the decoded image data can be reproduced at any time without any reading operation by the user. It has a function to prepare.
[0032]
Further, the control circuit 10 sequentially decodes each image and saves the decoded image data in the frame memory 6 even when the display operation command is not received, so that the time-consuming decoding is free. Processing is performed using time, and an image signal of a frame image can be obtained by reading from the frame memory 6 at any time.
[0033]
The input device 13 is for performing various operation commands such as reproduction, deletion, and frame designation.
[0034]
Next, the operation of the present device having such a configuration will be described. An image captured by the digital electronic still camera is converted into a video signal, compression-encoded in frame units, and recorded in the memory cartridge 1 mounted on the digital electronic still camera. For playback, the memory cartridge 1 is mounted on the connector 2 of a playback device (if the digital electronic still camera has a playback function, it may be mounted on the camera).
[0035]
Then, on the playback side, or in the case of a camera having a playback system, by giving a playback start command, the control circuit 10 sends a read command (read request signal) to the memory cartridge 1 via the connector 2 and the read frame. Information (address), and the memo corresponding to the address from the memory cartridge 1 is given.
The data of the frame image stored in the rear area is read.
[0036]
The read signal 3 of the image data is input to the decoder 4, which decodes the signal 3 into the original image data and supplies it to the frame memory 6.
[0037]
At this time, the control circuit 10 gives a command to the write address selection circuit 5, whereby the write address selection circuit 5 generates address information to be written (storage area address of the first frame) and gives it to the frame memory 6.
[0038]
Therefore, the decoded image data is stored in the address area specified by the write address selection circuit 5 in the frame memory 6.
[0039]
Until an artificial command to the reproduction system is given, the control circuit 10 sequentially decodes the image of the next frame until the capacity of the n frames of the frame memory 6 is fully satisfied. Is stored in another unrecorded address area designated by the write address selection circuit 5.
[0040]
In this way, the control circuit 10 in the image signal reproducing apparatus of the present invention repeats decoding and recording in the frame memory 6 using the idle time until a reproduction display command is given.
[0041]
The capacity of the frame memory 6 is about ten and several frames, but if there is no cost or dimensional problem, a capacity capable of storing a larger number of images may be secured.
[0042]
If the capacity of the frame memory 6 is large (equivalent to the number of frames stored in the memory cartridge 1), this operation is repeated, so that all the images in the memory cartridge 1 can be decoded and stored in the frame memory 6. The above operation is shown in a flowchart as st1 to st4 in FIG.
[0043]
Next, when a playback frame is commanded from the input device 13 of the playback system, the control circuit 10 sends the command to read out the image data of the commanded frame. reading It is given to the address selection circuit 7.
[0044]
As a result, the read address selection circuit 7 operates to sequentially output the addresses of the area corresponding to the designated frame and supplies the address to the frame memory 6. Therefore, the data is read from the designated address from the frame memory 6 and output to the DAC 8. .
[0045]
The DAC 8 converts digital data into a corresponding analog signal and outputs it to the output terminal 9. Since the read image data is digital data of a decoded video signal, the analog video signal is output from the output terminal 9. A reproduction output is obtained in the form of a signal.
[0046]
If the image signal is a video signal including a television synchronization signal at the time of encoding, the decoded and analogized signal becomes a video signal including the television synchronization signal. For example, if a device such as a video monitor that outputs a video signal as a visible image is connected, the reproduced image can be immediately viewed.
[0047]
If another next frame is designated, the control circuit 10 gives the command to the read address selection circuit 7 so that the control circuit 10 reads the image data of the designated frame.
[0048]
As a result, the read address selection circuit 7 operates to sequentially output the addresses of the area corresponding to the designated frame and supplies the address to the frame memory 6. Therefore, the data is read from the designated address from the frame memory 6 and output to the DAC 8. .
[0049]
Then, the DAC 8 converts the digital data into a corresponding analog signal and outputs it to the output terminal 9, so that the reproduced image is immediately displayed on the video monitor. Is a table Will be shown.
[0050]
The above operation is shown in a flowchart from st5 in FIG. st6 It becomes like.
[0051]
Here, in the apparatus of the present invention, when the capacity of the frame memory 6 is less than the number of images stored in the memory cartridge 1, as shown in FIG. 2, a read request signal output from the control circuit 10, a read address, and an image An empty area detection circuit 11 is provided for monitoring the remaining capacity of the frame memory 6 in response to the information on the amount of reading from the frame memory 6 by the reproduction and outputting information on the empty area. Is provided in the control circuit 10 to determine whether or not the free area has a sufficient area to write the decoded data.
A read control circuit 15 for blocking a read request signal from the control circuit 10 is provided so as to stop reading from the memory cartridge 1 when there is not enough free space for writing decoded data. Is desirable.
[0052]
In this way, when it is determined that there is not enough free space in the frame memory 6 and an area for storing the decoded data cannot be secured, the control circuit 10 requests the control unit 10 to read out the data obtained by compressing and encoding the image from the memory cartridge 1. Can be stopped by the read control circuit 15.
[0053]
Here, the free area refers to an unused portion in the frame memory 6 or a portion in which image data that may be deleted, such as a reproduction end frame or a frame that has received an erasure instruction, is stored. This prevents overflow when the capacity of the frame memory 6 is small.
[0054]
Further, if the present invention is configured as shown in FIG. 3, if the capacity of the frame memory 6 is small and the data of the stored images of all the frames in the memory cartridge 1 cannot be decoded and stored, the reading is performed within a readable range. Has the function of temporarily stopping reading, displaying images, erasing all images in the frame memory 6 when all reproduction is completed, and reading the next unreproduced data from the memory cartridge 1. Can be made.
[0055]
That is, in this case, a reproduced image detecting circuit 12, an erasing circuit 14, and a counter circuit 16 are further provided in the configuration of FIG. The counter circuit 16 receives the storage state information and the like of the stored image in the memory cartridge 1 read from the memory cartridge 1 by the control circuit 10 and refers to the read request signal and the read address given to the memory cartridge 1 from the control circuit 10 to read the memory cartridge. 1 counts the number of remaining stored images in the memory 1. When the judgment result of the control circuit 10 as to whether or not the free area has a sufficient area for writing the decoded data is negative, a read request signal is output. In response to the block signal from the read control circuit 15 that outputs the block signal, the counter circuit 16 determines the read request signal given to the memory cartridge 1 by the control circuit 10 address It has the function of blocking information.
[0056]
The control circuit 10 checks the number of remaining undecoded images of the stored images in the memory cartridge 1 based on the output of the counter circuit 16 and determines whether or not undecoded data still remains in the memory cartridge 1. A determination function is provided so that the control circuit 10 determines that the undecoded data still remains in the memory cartridge 1 and the free area detection circuit 11 writes the decoded data as a free area of the frame memory 6. The control circuit 10 has a function of outputting a reproduced image switching request when it is determined that there is no such area.
[0057]
On the other hand, when the read address is output from the read address selection circuit 7 to the reproduced image detection circuit 12, it is recognized that the image in the address area has been reproduced based on the read address. It has a function of detecting an image, and has a function of outputting information of a reproduced image in the frame memory 6 when the reproduction image switching request is detected. When the erasing circuit 14 receives the information of the reproduced image in the frame memory 6 outputted from the reproduced image detecting circuit 12, based on the information of the reproduced image, at least one of the reproduced images is obtained. It has a function of generating a command to delete image data so that an area to which an image is allocated is set as an unused area, and generating address information of an area to which the reproduced image is allocated.
[0058]
The image data erasure command and the address information are given to the free area detection circuit 11, which recognizes this area as a free area and gives a command to the write address selection circuit 5 to erase the area. Thus, the write address selection circuit 5 generates the address of the area, and the control circuit 10 generates the erasure data in the decoder 4 so that the data of the specified area in the storage area of the reproduced image in the frame memory 6 is stored. There is a configuration that can be erased.
[0059]
In such a configuration, the control circuit 10 reads the storage state information and the like of the image stored in the memory cartridge 1 from the memory cartridge 1 at the initial stage.
[0060]
Then, the control circuit 10 outputs a read request signal and a read address of the first image in order to decode the first image. These signals and address information are supplied to the memory cartridge 1 and the counter circuit 16, and these signals and address information and the read storage state information are also supplied to the counter circuit 16.
[0061]
Thus, the counter circuit 16 counts the number of remaining images stored in the memory cartridge 1 with reference to the read request signal and the read address given from the control circuit 10 to the memory cartridge 1 based on the storage state information. Then, the data of the first image is read from the memory cartridge 1 which has received the read request signal and the read address of the first image, and after being decoded by the decoder 4, it is stored in the frame memory 6. Is stored.
[0062]
When the first image is completed, the second image and the third image are read, decoded, and stored in the frame memory 6.
[0063]
On the other hand, the control circuit 10 checks the remaining number of undecoded images of the stored images in the memory cartridge 1 based on the output of the counter circuit 16 to determine whether or not undecoded data still remains in the memory cartridge 1. I do.
[0064]
Then, the control circuit 10 determines that the undecoded data still remains in the memory cartridge 1, and the free area detection circuit 11 does not have a sufficient area for writing the decoded data as the free area of the frame memory 6. The control circuit 10 outputs the result of the determination and a reproduced image switching request.
[0065]
Then, based on the determination result that there is no sufficient area, the read control circuit 15 outputs a read request signal blocking signal. Then, the counter circuit 16 blocks the read request signal and the address information given to the memory cartridge 1 by the control circuit 10 by the blocking signal.
[0066]
On the other hand, when a frame number is designated or an image playback command is given from the input device 13 without designation, the control circuit 10 causes the designated frame in the former case and the first frame not reproduced in the latter case. Since a command is given to the read address selection circuit 7 to display the frame image, the read address selection circuit 7 generates a storage address of the corresponding image and gives it to the frame memory 6.
[0067]
As a result, the data of the image is read from the frame memory 6, converted into digital data, and provided for display. The output address information of the read address selection circuit 7 is also provided to the reproduced image detection circuit 12, and the reproduced image detection circuit 12 determines the image of the address area based on the read address from the read address selection circuit 7. It recognizes that the image has been reproduced, and thereby detects the reproduced image in the frame memory 6.
[0068]
Then, when the request for switching the reproduced image is detected, the information of the reproduced image in the frame memory 6 is output. When the erasing circuit 14 receives the information of the reproduced image in the frame memory 6 outputted from the reproduced image detecting circuit 12, based on the information of the reproduced image, at least one of the reproduced images is obtained. A command for erasing image data so that an area to which an image is allocated is set as an unused area and address information of an area to which the reproduced image is allocated are generated.
[0069]
The image data erasure command and the address information are given to the free area detection circuit 11, which recognizes this area as a free area and gives a command to the write address selection circuit 5 to erase the area. Thus, the write address selection circuit 5 generates the address of the area, and the control circuit 10 generates the erasure data in the decoder 4 so that the data of the specified area in the storage area of the reproduced image in the frame memory 6 is stored. to erase.
[0070]
When an empty area is created by data erasure, the determination result from the control circuit 10 determines that there is a sufficient write area, and there is no blocking signal. Therefore, the next unreproduced image can be read from the memory cartridge 1, As a result, decoding of a new unreproduced image and update storage in the frame memory 6 are performed.
[0071]
As described above, the configuration of FIG. 3 monitors the remaining capacity of the frame memory 6 in response to the read request signal output from the control circuit 10, the read address, and the information of the read amount from the frame memory 6 by the image reproduction. A free area detection circuit 11 for outputting area information, and reading from the memory cartridge 1 is stopped according to the information from the free area detection circuit 11 when the free area does not have enough area to write the decoded data. A read control circuit 15 for blocking a read request signal from the control circuit 10 is provided, and it is determined that undecoded data still remains, and the free area of the frame memory 6 has a sufficient area for writing decoded data. If it is determined that there is no image, a reproduced image switching request is detected, and the reproduced image detecting circuit 12 When the reproduced image is detected and the information of the area of the reproduced image based on the detected information is given to the image erasing circuit 14, the image erasing circuit 14 determines the area of the reproduced image to which at least one image is assigned. The image is erased so as to be used, and an unreproduced image in the memory cartridge 1 is read out, decoded, stored and waited in this newly secured unused area.
[0072]
Therefore, by adopting such a configuration, even when the capacity of the frame memory 6 is small and it is not possible to decode and store the data of the stored images of all the frames in the memory cartridge 1, it is necessary to read and temporarily read the data within a readable range. When the reproduction is completed, all the images in the frame memory 6 are erased at that point, and the next unreproduced data can be read from the memory cartridge 1. Alternatively, all the images in the frame memory 6 may be erased when the reproduction of all the images in the frame memory 6 is completed, and the next unreproduced data may be read from the memory cartridge 1.
[0073]
The above operation is shown in a flowchart as shown in FIG.
[0074]
In an electronic still camera, when a plurality of images shot in the continuous shooting mode are to be played back continuously at high speed, only a few shots from the continuous shooting need be played back. The configuration 3 is effective for such a use.
[0075]
Of course, after playing back several images, those which are deemed unnecessary are erased by a command from the input device 13, and an unreproduced image or an image with a specified frame number is read from the memory cartridge 1 in an empty area. It is also possible to use it in such a way that it can be played at any time.
[0076]
The image erasing may be performed not at the time of the request for switching the reproduced image but at the time of the direct image erasing request. The request may be automatically generated or may be input from the input device 13. good.
[0077]
The input device is a keyboard in this embodiment, and is connected to the control circuit 10 so that a command can be directly given. The counter circuit 16 is a means for determining the presence or absence of undecoded data, and may be a flip-flop that is turned on / off based on the remaining data.
[0078]
The present invention is not limited to the embodiment described above and shown in the drawings, and it is needless to say that the present invention can be appropriately modified and implemented without departing from the scope of the invention.
[0079]
As described above, the present apparatus reads out the encoded data from the recording medium in response to the control instruction and decodes the encoded data, when the recording medium in which the encoded data obtained by compressing and encoding the image information is recorded is applied. Display image data in which digital display image data serving as a basis of a display image is sequentially generated for each unit image, and the display image data is stored in a predetermined image display memory having a storage capacity for a plurality of images. Data generation means, signal conversion means for sequentially reading and converting analog display image data in digital form stored in the display image memory, and generating and outputting a video signal for image display; An operation command unit for issuing an operation command signal for displaying an image based on a predetermined operation; and generating and displaying the display image data by the display image data generating unit. In response to a first control for sequentially storing data in the image display memory and one operation command signal from the operation command means, the signal conversion means stores the data stored in the image display memory. A second control for generating and outputting a video signal for image display based on the display image data, and the second control is initially performed in response to the one operation command signal. After that, the control means is configured to execute the first control immediately after the completion of the second control without waiting for another operation command signal. Further, the control means is provided with a function of performing the first control without waiting for another operation for displaying an image by the operator.
[0080]
That is, the display image data generating means reads out the encoded data from the recording medium on which the encoded data obtained by compressing and encoding the image information is recorded in response to the control command, decodes the encoded data, and decodes the encoded digital data as the basis of the display image. The display image data of the mode is sequentially generated for each unit image, the display image data is stored in a predetermined image display memory having a storage capacity for a plurality of images, and the signal conversion unit is stored in the display image memory. The display image data in the digital form is sequentially read and converted into an analog signal, and a video signal for image display is generated and output.
[0081]
The control means can perform first control for causing the display image data generation means to sequentially generate the display image data and store the display image data in the image display memory. Receiving the one operation command signal obtained by operating the device, causes the signal conversion means to generate and output a video signal for image display based on the display image data stored in the image display memory. After that, the first control is executed without waiting for another operation command signal.
[0082]
In the device of the present invention, when the operator operates the operation command means for displaying an image, it repeatedly generates and outputs a video signal based on display image data stored in the image display memory. Therefore, even if there are a large number of frames, the images on the recording medium can be continuously reproduced at high speed, and the images can be searched efficiently.
[0083]
When the control means is provided with a function of performing the first control without waiting for a separate operation for displaying an image by an operator, the control means may include the display image data generating means. In addition, since the generation of the display image data and the storage of the display image data in the image display memory are sequentially performed, the decoding of the time-consuming encoded data effectively uses the idle time, so that Images in a recording medium can be continuously reproduced at high speed, and images can be searched efficiently.
[0084]
【The invention's effect】
As described above, according to the present invention, according to the present invention, when an image of an electronic still camera or the like is decoded in advance and stored in the image display memory, and the operator operates the operation instruction unit for displaying the image, Since the video signal is generated and output based on the display image data stored in the image display memory, the image on the recording medium can be continuously reproduced at high speed even if there are a large number of frames, and more efficiently. You can search for images.
[Brief description of the drawings]
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a block diagram showing another embodiment of the present invention.
FIG. 3 is a block diagram showing another embodiment of the present invention.
FIG. 4 is a flowchart for explaining the operation of the device of the present invention.
FIG. 5 is a flowchart for explaining a conventional example.
[Explanation of symbols]
1 ... Memory cartridge,
2. Connector,
4: Decoder,
5 Write address selection circuit
6. Frame memory,
7 read address selection circuit
8 ... Digital-analog converter,
10 ... Control circuit,
11 ... empty area detection circuit
12: Reproduced image detection circuit,
13 input devices,
14 ... Erase circuit,
15 ... Readout control circuit,
16 ... Counter circuit

Claims (1)

When a recording medium on which encoded data obtained by compression-encoding the image information is recorded is applied, in response to the control command, the encoded data is read from the recording medium, decoded, decoded, and used as the basis of the display image. Display image data generating means for sequentially generating display image data in a digital form for each unit image and storing the display image data in a predetermined image display memory having a storage capacity for a plurality of images;
Signal conversion means for sequentially reading and converting the digital display image data stored in the image display memory into an analog form, generating and outputting a video signal for image display,
Operation command means for issuing an operation command signal for displaying an image based on a predetermined operation by the operator,
To the display image data generating unit, sequentially performed occupies the first control storage to the image display memory of the image data for generation and the display of the display image data, otherwise for image display upon mounting said recording medium Is executed without waiting , and further in response to one operation command signal from the operation command means, the signal conversion means causes the signal conversion means to display an image based on the display image data stored in the image display memory. And a second control for generating and outputting a video signal for the second operation command signal. After the second control is performed once in response to the one operation command signal, another operation command signal is output. Control means configured to execute the first control immediately after completion of the second control without waiting;
An image reproducing apparatus comprising:

Images