JP3555265B2 - Frequency division multiplex signal transmitter - Google Patents

Description

選択回路４５より取り出されたこれらの出力４ビットが順番に図１及び図４に示した伝送情報入力バッファ回路４に格納されるが、これらの値の並びは、出力時間軸データ整列型（入力周波数軸データビットリバース型）で、２倍オーバーサンプリングのＩＤＦＴ演算において、第一ステージの結果と一致する。
【００６１】
選択回路４５の出力は１６ビットデータバスとして、また、２の補数表記で演算されることを前提にして、伝送情報入力バッファ回路４に格納される。すなわち、選択回路４５の出力４ビットデータは図７に示すように、１６ビットデータバスＤＡＴＡ０〜１５のうちのＤＡＴＡ１４〜１１に割り当てられ、ＤＡＴＡ１４がＤＡＴＡ１５に拡張され、さらに、ＤＡＴＡ１０は”Ｈ”に固定され、ＤＡＴＡ９〜０は”Ｌ”に固定される。
【００６２】
次に、これらの操作について説明する。ＩＤＦＴの演算をする際に、ステージごとにその結果を１／２にする操作は、時間はかからず簡単である。また、そのようにする方がソフト上利便である。そのため、４ビットデータは上位に配置すべきである。第一ステージでの１／２と、オーバーフロー、アンダーフローを避けることも考慮し、ＤＡＴＡ１４〜１１に配置する。ＤＡＴＡ１５の処理は、符号拡張のためである。
【００６３】
ＤＡＴＡ１０に”Ｈ”を指定することは、一般的にＱＡＭ変調等で行われる様に、信号点配置を”０．５”ずらし、受信機での復調を簡単にするためである。ここで、符号反転するために、すべて信号反転する回路を用いたが、前記”０．５”を加算する処理がなされるため、結果は、符号反転されていることになる。４ビットＤＡＴＡに”０．５”を加算して符号反転した結果と、４ビットデータを反転して”０．５”を加算した結果とが一致することを次表に示す。
【００６４】
【表２】

すなわち、Ｗ、Ｘ、Ｙ及びＺをそれぞれ”０”又は”１”の値のビットとし、Ａ、Ｂ、Ｃ及びＤをそれぞれＷ、Ｘ、Ｙ及びＺの反転した値とすると、Ｗ、Ｘ、Ｙ及びＺの４ビットに対し”０．５”を加算すると、”ＷＸＹＺ１”の５ビットとなるから、この値を符号反転して最下位に１ビットを加えると”ＡＢＣＤ１”となる。一方、上記のＷ、Ｘ、Ｙ及びＺの４ビットを反転すると、”ＡＢＣＤ”となるから、この値の最下位に１ビットの値”１”を加算すると、”ＡＢＣＤ１”となる。そこで、本実施の形態では後者の方法で４ビットデータに”０．５”を加算して符号反転した、第一ステージの演算結果を得ている。
【００６５】
上記のようにしてステージ演算回路３により第一ステージの演算が実行されて得られた１６ビットデータは、図４に示した伝送情報入力バッファ回路４に格納される。ＩＤＦＴ演算部５は、入力完了信号（ＷＥＮＡ１）ｂが伝送情報入力制御回路２から入力された時点で、高速に伝送情報入力バッファ回路４から上記の１６ビットデータを読み取り、第二ステージ以降のＩＤＦＴ演算を実施する。
【００６６】
図８はＩＤＦＴ演算部５と、演算結果出力バッファ回路６と、演算結果出力制御回路７の詳細ブロック図を示す。初期状態において、演算結果出力バッファ回路６内のデータ量はゼロである。
【００６７】
ＩＤＦＴ演算部５は一回のＩＤＦＴ演算では、Ｉ信号、Ｑ信号それぞれに約５１２個のデータを生成する（１シンボル分）。実際には、５１２個のデータに、１２個のガードインターバル用のデータを加え、５２４個のデータをそれぞれ生成する。演算結果出力バッファ回路６は８ｋ×１６ビットのＦＩＦＯ−ＲＡＭ６ａ及び６ｂからそれぞれ構成されている。従って、約１６個弱のシンボルが蓄えられる。
【００６８】
演算結果出力制御回路７は、演算結果出力バッファ回路６内のデータ量が半分に達するまで、出力要求信号ｃを発し続ける。従って、前記伝送情報の入力とＩＤＦＴ演算と演算結果書き込みが、出力要求信号ｃがノンアクティブになるまで約８回以上繰り返される。
【００６９】
演算結果出力バッファ回路６の記憶データは所定の連続クロックで読み出され、図示しない次段の直交変調器に転送されるが、ＩＤＦＴ演算結果の書き込みの方が多少速く動作する（データ生成スピードが速い）ため、演算結果出力バッファ回路６内のデータは漸次増加してゆく。データ量が増加し、演算結果出力バッファ回路６の記憶容量の半分に達すると、演算結果出力制御回路７がこれを検出してその出力要求信号ｃをノンアクティブとする。
【００７０】
ＩＤＦＴ演算部５は、この出力要求信号ｃがノンアクティブとなるとＩＤＦＴ演算結果の演算結果出力バッファ回路６への書き込みをせず、出力要求信号ｃがアクティブ状態になるまで待つ。 しかし、その間にも、演算結果出力バッファ回路６内のデータは連続的に読み出されるため、データ量は漸次減少してゆく。更にデータ量が減少して、演算結果出力バッファ回路６の記憶容量の半分以下になったときに、演算結果出力制御回路７がこれを検出してその出力要求信号ｃをアクティブ状態とし、ＩＤＦＴ演算部５の出力演算結果の演算結果出力バッファ回路６への書き込みを許可する。
【００７１】
このようにして、ＩＤＦＴ演算部５は、出力要求信号ｃの制御下で、ＤＳＰの速度限界で高速にＩＤＦＴ演算結果を演算結果出力バッファ回路６に出力して書き込むことができる。よって、データ出力に関しては、ＤＳＰからなるＩＤＦＴ演算部５にとって極力無駄な時間を省くことが可能となる。
【００７２】
なお、上記の出力要求信号ｃは、ハーフ（ＨＡＬＦ）フラグ（データ量が半分以上か、以下かを示す信号ピン）付きのＦＩＦＯ−ＲＡＭの機能で代用してもよく、また、カウンタを用意し、バッファ書き込みクロックでカウントアップ、バッフア読み出しクロックでカウントダウンして実現してもよい。
【００７３】
上記のＩＤＦＴ演算部５、すなわちＤＳＰの動作は図２のフローチャートと共に説明したように、電源投入初期の段階で一回、入力完了信号待ちの状態が発生するが、その後、装置の安定状態では、毎回、ほぼ一定時間、出力要求信号待ちの状態が繰り返されることになる。
【００７４】
このように、本実施の形態では２倍オーバーサンプリング時のＩＤＦＴ演算の第一ステージの演算を図７に示したハードウェア回路構成のステージ演算回路３により実現しているため、ＩＤＦＴ演算部５に対して伝送情報の入力時間及び演算結果の出力時間を極力少なくすることができる。また、ＩＤＦＴ演算部５が入力要求信号ａを発するのみで、伝送情報は入力され、必要な時に入力完了信号ｂを検査し、ＩＤＦＴ演算部５の速度限界で入力バッファ回路４からデータを読み取ることができる。
【００７５】
以上より、この実施の形態のデータ入力に関しては、ＩＤＦＴ演算部５にとって極力無駄な時間を省くことができ、結果として演算時間の短縮が図れる。従って、安価なＤＳＰをＩＤＦＴ演算部５に用いてＩＤＦＴ演算を実行でき、装置全体での低コスト化を実現することができる。また、演算時間の短縮化により、余った時間を他の機能を実現するために使用することもできる。
【００７６】
次に、本発明の要部のステージ演算回路３の他の実施の形態について説明する。上記の説明ではステージ演算回路３は２倍オーバーサンプリングの第一ステージの演算をするように説明したが、４倍オーバーサンプリングの一部のＩＤＦＴ演算をすることもできる。この場合、ステージ演算回路３はＩＤＦＴ演算の第一及び第二ステージの演算を実行する。
【００７７】
この４倍オーバーサンプリング時のＩＤＦＴ演算の第一及び第二ステージの演算について説明するに、入力の実数部データと虚数部データ（入力）と、第一ステージ結果と第二ステージ結果とは以下に示すようになる。
【００７８】

の繰り返しにおいて（数字は１６進）、

にデータが割り当てられ、

にはゼロが設定される。
【００７９】
従って、４倍オーバーサンプリングでは、以下のようになる。
【００８０】

これを、前記したパルスＣＬＫ２４８と入力８ビットとアドレス信号と最終４ビットとの関係で表すと、表３のようになる。
【００８１】
【表３】

このようにして、ステージ演算結果が前記伝送情報入力バッファ回路４に格納される。このステージ演算回路は既述の応用で簡単に実現できる。この４倍オーバーサンプリング時にも２倍オーバーサンプリング時と同様の効果を奏する。
【００８２】
次に、本発明の要部のステージ演算回路３の第２の実施の形態について説明する。図９は本発明の要部のステージ演算回路３の第２の実施の形態のブロック図を示す。この実施の形態では、後段のアナログ系の設計を容易にするため、２倍のオーバーサンプリングを使用し、基数２で２５６ポイントのＩＤＦＴ演算を行い、ＯＦＤＭ信号を発生させるものとする。また、２５６ＱＡＭにより１本の搬送波に８ビットの情報を印加し、ＩＤＦＴ演算部への入力割り当ては、入力周波数整列型で順番に番号をふると次のようになる。
【００８３】
番号 ０〜 ６４ 搬送波を変調する情報信号が与えられる。
【００８４】
番号６７〜１９１ 搬送波レベルを０とし、信号を発生させない。
【００８５】
番号１９２〜２５５ 搬送波を変調する情報信号が与えられる。
【００８６】
出力時間軸データ整列型のＩＤＦＴ演算の第一ステージ、第二ステージについて説明する。 ビットリバース型周波数入力に対して、それぞれの演算は以下の通りとなる。
【００８７】

この繰り返しにおいて、２倍オーバーサンプリングのため（数字は１６進）、

にデータが割り当てられ、

にはゼロが設定される。
従って、入力割り当てと上記の第一、第二ステージの結果は、

の繰り返しとなる。
【００８８】
図９は前述したように、２倍のオーバーサンプリングを使用し、基数２で２５６ポイントのＩＤＦＴ演算を行うに当たり、ＩＤＦＴ演算部の入力側に設けられた第一ステージと第二ステージを実施しながら伝送情報を出力するステージ演算回路のブロック図で、この実施の形態のステージ演算回路は、入力データ分割回路５１、反転回路５２及び５３、加算回路５４〜６１からなるハードウェア回路である。
【００８９】
同図において、入力データ分割回路５１は図示しない外部システムからの８ビットデータを入力として受け、入力データをを４ビット毎に分割し、分割された４ビットデータを順次４個ずつまとめ、それらを出力端子Ａ、Ｂ、Ｃ、Ｄより出力する。出力端子Ａからの４ビットデータＡ_ｎ等は１番目、３番目、５番目及び７番目の２入力加算回路５４、５６、５８及び６０の各一方の入力端子に入力され、出力端子Ｂからの４ビットデータＢ_ｎ等は２番目、４番目、６番目及び８番目の２入力加算回路５５、５７、５９及び６１の各一方の入力端子に入力される。
【００９０】
また、入力データ分割回路５１の出力端子Ｃからの４ビットデータＣ_ｎ等は１番目と８番目の２入力加算回路５４、６１の各他方の入力端子に入力され、出力端子Ｄからの４ビットデータＤ_ｎ等は２番目と３番目の２入力加算回路５５、５６の各他方の入力端子に入力される。更に、入力データ分割回路５１の出力端子Ｃ、Ｄからの各４ビットデータは、それぞれ反転回路５２、５３に入力されてすべてのビットが論理反転された後、反転回路５２の出力データ（−Ｃ_ｎ等）は４番目と５番目の２入力加算回路５７、５８の各他方の入力端子に入力され、反転回路５３の出力データ（−Ｄ_ｎ等）は６番目と７番目の２入力加算回路５９、６０の各他方の入力端子に入力される。
【００９１】
上記の８個の加算回路５４〜６１は、いわゆる全加算器で、一方の入力端子（第１入力）と、他方の入力端子（第２入力）に入力された４ビットデータに対し加算演算すると共に符号拡張する。その際に、更に＋１の加算も行われる。実際には、上記の符号拡張は最上位ビットのデータがさらにその上位２ビットとしてコピーされ、全体として６ビットとするものである。符号拡張された後のデータをＡｍ、Ｂｍ、Ｃｍ、Ｄｍ、−Ｃｍ、−Ｄｍとする。以後これらのデータは２の補数表現で演算される。これにより、加算回路５４〜６１の入力と出力の関係はまとめると、表４に示すようになる。
【００９２】
【表４】

上記の表４の加算結果は、前記した第二ステージ演算結果と同等の結果である。例えば、Ｒ０、Ｉ０、Ｒ３、Ｉ３に入力に対して、前記したように第二ステージ演算結果は、Ｒ０＋ｊＩ０と更に続くＲ３＋ｊＩ３の入力に対しては、（Ｒ０＋Ｒ３）／４と（Ｉ０＋Ｉ３）／４、（Ｒ０＋Ｉ３）／４と（Ｉ０−Ｒ３）／４、（Ｒ０−Ｒ３）／４と（Ｉ０−Ｉ３）／４及び（Ｒ０−Ｉ３）／４と（Ｉ０＋Ｒ３）／４である。
【００９３】
ここで、上記のＲ０、Ｉ０、Ｒ３及びＩ３をそれぞれＡ、Ｂ、Ｃ及びＤで表すものとし、また１／４はビットシフトにより得られるので無視すると、第二ステージ演算結果は上記の入力の場合には、｛（Ａ＋Ｃ）、（Ｂ＋Ｄ）｝、｛（Ａ＋Ｄ）、（Ｂ−Ｃ）｝、｛（Ａ−Ｃ）、（Ｂ−Ｄ）｝及び｛（Ａ−Ｄ）、（Ｂ＋Ｃ）｝と書き改めることができる。これは表４から分かるように、加算回路５４〜６１の出力加算結果Ｈｍ０〜Ｈｍ７にほかならない。ただし、表４の加算結果Ｈｍ０〜Ｈｍ７では符号拡張と＋１の加算結果が得られているが、この意味は第二ステージ演算結果に関係ないので、加算結果Ｈｍ０〜Ｈｍ７が実質上、第二ステージ演算結果であることが分かる。他の入力の場合も上記と同様である。
【００９４】
なお、図９において、説明を簡略化するため、Ｈｍ０〜Ｈｍ７が伝送情報バッファ回路に伝達される部分は記述してないが、実際には図７の選択回路４５と同等な機能を有する８入力１出力型の選択回路で実現できる。選択信号も容易に作成できる。
【００９５】
ここで、２ビット符号拡張する意味は、加算時のオーバーフロー、アンダーフローを避けるためであり、記述の第二ステージ演算結果の１／４スケーリングに対応している。また、＋１を加算するのは第１の実施の形態で図７のＤＡＴＡ１０に”Ｈ”を与えた理由と同じである。
【００９６】
すなわち、一般的にＱＡＭ変調等では、信号点配置を＋０．５ずらし、受信機での復調を簡単にする。そこで、通常の方法としては、既述の入力ｎビットに対し、最下位ビットのさらに下位に１ビットを論理”１”で加える。補数を求めるには、すべてのビットを反転しＬＳＢに”１”を加えてつくる。そして加算する。この動作の簡便な方法として、補数に関してはビット反転することと、加算後には＋１することで、同等となる。
【００９７】
そのままの加算については、０．５に対応するビットは常に論理”１”であり、加算により０．５＋０．５＝１になるからであり、補数の場合も、反転するだけで、０．５に対応するビットは常に論理”１”であり、加算で１になるからである。２つの例についてこの様子を図１０及び図１１に示す。なお、両図中、＋０．５した値を”’”で表す。
【００９８】
このような方法により、ＩＤＦＴ演算の第一、第二ステージを実施することができる。なお、上記は一例であり、所望の結果を得ることが要点である。加算回路５４〜６１より得られた８個のデータは、前記ＩＤＦＴ演算部５に渡され、第三ステージ以降の演算を実施する。演算の最終結果は、図示しない直交変調器に入力され、Ｄ／Ａ、周波数変換部等を通ってＯＦＤＭ信号となり、増幅器を介して送信アンテナに給電され、電波発射される。
【００９９】
次に、本発明の第３の実施の形態ついて説明する。この場合、２倍オーバーサンプリングを使用し、基数４で２５６ポイントのＩＤＦＴ演算を行い、ＯＦＤＭ信号を発生させる。基数４のＩＤＦＴ演算の詳細は、他に専門書が多数あるので省略する。基数４の基本演算は、図１２に示すように行われる。なお、入力データをｘ（０）、ｘ（１）、ｘ（２）、ｘ（３）とし、求まる変換値をＸ（０）、Ｘ（１）、Ｘ（２）、Ｘ（３）とし、回転因子Ｗ^ｎをｅｘｐ（−２πｊｎ／４）とする。
【０１００】
図１２から次式が成立する。
【０１０１】
Ｘ（０）＝ｘ（０）＋ｘ（１）＋ｘ（２）＋ｘ（３）
Ｘ（１）＝ｘ（０）＋ｊｘ（１）−ｘ（２）−ｊｘ（３）
Ｘ（２）＝ｘ（０）−ｘ（１）＋ｘ（２）−ｘ（３）
Ｘ（３）＝ｘ（０）−ｊｘ（１）−ｘ（２）＋ｊｘ（３）
入力整列型のＩＤＦＴ演算において、第一ステージを実施する際、２倍オーバーサンプリングを考慮すると、上記のｘ（１）とｘ（２）は常にゼロであるから上式は次のように書き表せる。
【０１０２】
Ｘ（０）＝ｘ（０）＋ｘ（３）＝（Ｒ０＋Ｒ３）＋ｊ（Ｉ０＋Ｉ３）
Ｘ（１）＝ｘ（０）−ｊｘ（３）＝（Ｒ０＋Ｉ３）＋ｊ（Ｉ０−Ｒ３）
Ｘ（２）＝ｘ（０）−ｘ（３）＝（Ｒ０−Ｒ３）＋ｊ（Ｉ０−Ｉ３）
Ｘ（３）＝ｘ（０）＋ｊｘ（３）＝（Ｒ０−Ｉ３）＋ｊ（Ｉ０＋Ｒ３）
ここで、記述内容に合わせて、ｘ（０）＝Ｒ（０）＋ｊＩ０、ｘ（３）＝Ｒ３＋ｊＩ３とおいている。
【０１０３】
上記の説明から分かるように、基数４のＩＤＦＴ演算の第一ステージは、前記の基数２のＩＤＦＴ演算の第一及び第二ステージと同じ演算であり、同じハードウェア回路により演算できる。
【０１０４】
次に、本発明の要部のステージ演算回路３の第４の実施の形態について説明する。図１３は本発明の要部のステージ演算回路３の第４の実施の形態のブロック図を示す。この実施の形態では、後段のアナログ系の設計を容易にするため、４倍のオーバーサンプリングを使用し、５１２ポイントのＩＤＦＴ演算を行い、ＯＦＤＭ信号を発生させる。また、２５６ＱＡＭにより１本の搬送波に８ビットの情報を印加し、ＩＤＦＴ演算部への入力割り当ては、入力周波数整列型で順番に番号をふると、次のようになる。
【０１０５】
番号 ０〜 ６４ 搬送波を変調する情報信号が与えられる。
【０１０６】
番号 ６５〜４４７ 搬送波レベルを０とし、信号を発生させない。
【０１０７】
番号４４８〜５１１ 搬送波を変調する情報信号が与えられる。
【０１０８】
この場合の出力時間軸データ整列型のＩＤＦＴ演算の第一、第二、第三ステージの演算は図１４に示すようになる。また、このＩＤＦＴ演算による第三ステージの演算結果は次式のＨ０〜Ｈ７の繰り返しとなる。
【０１０９】
【数１】

（１）式を更に整理すると次式が得られる。
【０１１０】
【数２】

次に、上記の第三ステージの演算結果を得る図１３のステージ演算回路３の構成及び動作について説明する。図１３中、図１と同一構成部分には同一符号を付してある。この実施の形態のステージ演算回路３は、図１３に示すように、入力データ分割回路７１、反転回路７２及び７３、２入力加算回路７４及び７５、６個の拡張回路７６〜８１からなるハードウェア回路である。
【０１１１】
図１３において、入力データ分割回路７１は図示しない外部システムからの８ビットデータを入力として受け、入力データを４ビット毎に分割し、分割された４ビットデータを順次４個ずつまとめ、それらを出力端子Ａ、Ｂ、Ｃ、Ｄより出力する。出力端子Ａ、Ｂ、Ｃ及びＤからの各４ビットデータＡ_ｎ、Ｂ_ｎ、Ｃ_ｎ及びＤ_ｎ等は１番目、２番目、３番目及び４番目の拡張回路７６、７７、７８及び７９に入力され、更に出力端子Ｃからの４ビットデータＣ_ｎ等は反転回路７２と加算回路７４に入力され、出力端子Ｄからの４ビットデータＤ_ｎ等は反転回路７３と加算回路７４及び７５にそれぞれ入力される。反転回路７２の出力反転データ（−Ｃ_ｎ等）は、拡張回路８０と加算回路７５にそれぞれ入力される。また、反転回路７３の出力反転データ（−Ｄ_ｎ等）は、拡張回路８１に入力される。
【０１１２】
加算回路７４及び７５は、いわゆる全加算器で、一方の入力端子（第１入力）と、他方の入力端子（第２入力）に入力された４ビットデータに対し加算演算すると共に符号拡張する。実際には、図９の加算回路５４〜６１と同様に、符号拡張は最上位ビットのデータをさらにその上位２ビットとしてコピーし、全体として６ビットとするものである。また、このとき＋１の加算を行い、ＬＳＢの下位に論理”０”で１ビット付加して７ビットとする。すなわち、加算回路７４、７５では、６ビットに０．５＋０．５を加算するので、００００１．０（７ビット）を加算することになる。よって、＋１をして最下位（ＬＳＢ）の下に”０”を付加するのと同等である。
【０１１３】
以下、時刻ｎにおける動作につき説明するに、加算回路７４は第１入力Ｄｎと第２入力 Ｃｎの４ビットデータに対し符号拡張して６ビットとし、かつ、加算演算結果（Ｄｍ＋Ｃｍ）を生成し、さらに＋１を加算し、ＬＳＢの下位に論理”０”で１ビット付加して７ビットのデータＥｍを生成出力する。また、もう一つの加算回路７５は、第１入力Ｄｎと第２入力−Ｃｎの４ビットデータに対し符号拡張して６ビットとし、かつ、加算演算結果により（Ｄｍ−Ｃｍ）を生成し、さらに＋１を加算し、ＬＳＢの下位に論理”０”で１ビット付加して７ビットのデータＦｍを生成する。
【０１１４】
拡張回路７６は、入力４ビットデータＡｎを２ビット符号拡張し、ＬＳＢの下位に論理”１”で１ビット付加して７ビットとした拡張データＡｍを出力する。他の拡張回路７７、７８及び７９も上記と同様に、入力４ビットデータＢｎ、Ｃｎ及びＤｎの最上位ビットが更にその上位２ビットとしてコピーされ、全体として６ビットとされた後、そのＬＳＢの下位に論理”１”で１ビット付加して７ビットとされた、拡張データＢｍ、Ｃｍ及びＤｍをそれぞれ出力する。
【０１１５】
また、拡張回路８０は、反転回路７２より入力された４ビットデータ−Ｃｎを２ビット符号拡張し、かつ、ＬＳＢの下位に論理”１”で１ビット付加して７ビットとした拡張データ−Ｃｍを生成する。更に、拡張回路８１は、反転回路７２より入力された４ビットデータ−Ｄｎを２ビット符号拡張し、かつ、ＬＳＢの下位に論理”１”で１ビット付加して７ビットとした拡張データ−Ｄｍを生成する。
【０１１６】
ここで、上記の演算をより具体的に、例えばＡｎを「１００１（−７）」、Ｂｎを「００１１（３）」、Ｃｎを「０００１（１）」、Ｄｎを「１０１１（−５）」であるものとして説明するに、このときは反転回路７２、７３の出力は−Ｃｎ＝１１１０、−Ｄｎ＝０１００となる。また、加算回路７４は上記のＤｎを上位２ビット符号拡張してＤｍ＝１１１０１１を生成し、Ｃｎを上位２ビット符号拡張してＣｍ＝０００００１を生成し、それらを加算してＤｍ＋Ｃｍ＝１１１１００を生成した後、＋１を加算した値（Ｄｍ＋Ｃｍ＋１）として「１１１１０１」を生成し、この６ビットのＬＳＢの下に１ビット”０”を付加して７ビットデータＥｍとして「１１１１０１０」を生成する。同様にして、加算回路７５は７ビットデータＦｍとして「１１１０１００」を生成する。
【０１１７】
また、拡張回路７６〜８１は、上位２ビットを符号拡張して更にＬＳＢに下に１ビット付加するので、「１１１００１１」の値の７ビットデータＡｍ、「００００１１１」の値の７ビットデータＢｍ、「０００００１１」の値の７ビットデータＣｍ、「１１１０１１１」の値の７ビットデータＤｍ、「１１１１１０１」の値の７ビットデータ−Ｃｍ、「０００１００１」の値の７ビットデータ−Ｄｍをそれぞれ出力する。
【０１１８】
ここで、上記７ビットの上位４ビット目と５ビット目の間に小数点があると仮定すると、Ａｍは「１１１０．０１１」で、これは−１．６２５であるから（−７＋．５）／４と同等である。同様に、Ｂｍは（３＋．５）／４と、Ｃｍは（１＋．５）／４と、Ｄｍは（−５＋．５）／４とそれぞれ同等である。更に、−Ｃｍ、−ＤｍはＣｍ、Ｄｍの符号反転と同等である。また、Ｅｍの「１１１１．０１０」は「−０．７５」で、これはＤｍ＋Ｃｍと同等であり、Ｆｍの「１１１０．１００」は「−１．５」で、これはＤｍ−Ｃｍと同等である。
【０１１９】
以上のようにして得られた拡張データＡｍ、Ｂｍ、Ｃｍ、Ｄｍ、−Ｃｍ、−Ｄｍ、Ｅｍ及びＦｍの８個のデータは、それぞれ伝送情報入力バッファ回路４に入力される。ＩＤＦＴ演算部５は、伝送情報入力バッファ回路４内の８個のデータから、ＩＤＦＴ演算部５の有するメモリの、所望の１６個の番地（０番地〜Ｆ番地）に対し、次式が得られるように演算して格納する。
【０１２０】
【数３】

上記の（３）式は、（２）式と同一である。すなわち、（２）式において、Ｒ０＝Ａｍ、Ｉ０＝Ｂｍ、Ｒ７＝Ｃｍ、Ｉ７＝Ｄｍであり、Ｓ＝√２であり、更にＤｍ＋Ｃｍ＝Ｅｍ、Ｄｍ−Ｃｍ＝Ｆｍを用いて（２）式を書き直すと（４）式が得られる。
【０１２１】
【数４】

（４）式のＨ０〜Ｈ７を実数部と虚数部に分けて各番地に格納すると（３）式と同等となる。従って、図１３に示したハードウェア回路のステージ演算回路３によりＩＤＦＴ演算の第一、第二ステージと第三ステージの一部の演算を実施できる。なお、上記は一例であり、所望の結果を得ることが要点である。更に、もっと第三ステージの部分をハードウェアで実施したい場合は、加算器を備え、Ａｍ＋Ｃｍ等をハードウェアで実施してもよい。
【０１２２】
ＩＤＦＴ演算部５は、１６個のデータを得る上記の動作を６４回繰り返した後、さらに第四ステージ以降の演算を実施する。演算の最終結果は、図示しない直交変調器に入力され、Ｄ／Ａ、周波数変換部等を通ってＯＦＤＭ信号となり、増幅器を介して送信アンテナに給電され、電波発射される。
【０１２３】
次に、上記の実施例の形態で８倍オーバーサンプリングを使用した場合について説明する。この場合ＩＤＦＴ演算は前記のＲ７＋ｊＩ７、Ｒ８＋ｊＩ８ はゼロとなるため、さらに簡単になる。すなわち、（２）式に対応する式は以下のようになる。
【０１２４】
【数５】

（５）式から解かるように、バッファ回路４内に８個のデータが入るまでは、第４の実施の形態と同様であり、ＩＤＦＴ演算部５で、ＩＤＦＴ演算部５の有するメモリの、所望の３２個の番地に対し、（５）式の演算を施せばよい。すなわち、ＩＤＦＴ演算部５内のメモリの所望の０番地から１Ｆ（１６進数）番地までの計３２個の番地に対し、０、２、４、６、８、Ａ、Ｃ及びＥの各番地がＡｍ、１、３、５、７、９、Ｂ、Ｄ及びＦの各番地がＢｍ、１０番地が＋Ｃｍ、１１番地が＋Ｄｍ、１２番地が＋ＳＥｍ、１３番地がＳＦｍ、１４番地が＋Ｄｍ、１５番地が−Ｃｍ、１６番地が＋ＳＦｍ、１７番地が−ＳＥｍ、１８番地が−Ｃｍ、１９番地が−Ｄｍ、１Ａ番地が−ＳＥｍ、１Ｂ番地が−ＳＦｍ、１Ｃ番地が−Ｄｍ、１Ｄ番地が＋Ｃｍ、１Ｅ番地が−ＳＦｍ、１Ｆ番地が＋ＳＥｍ（ただし、Ｓ＝√２）となるように演算して格納する。
【０１２５】
このようにして、ステージ演算回路３で第三ステージの一部までの演算が終了するので、ＩＤＦＴ演算部５は、３２個のデータを得る上記の動作を３２回繰り返した後、さらに第四ステージ以降の演算を実施する。
【０１２６】
なお、以上では８倍オーバーサンプルまで説明したが、本発明はこれに限定されるものではなく、それ以上のものでも適用可能である。それらのステージ演算回路については、以上の実施の形態の説明より容易に類推できる。
【０１２７】
【発明の効果】
以上説明したように、本発明によれば、ＩＤＦＴ演算の第ｋステージの演算を簡単な構成のハードウェア回路であるステージ演算回路により実施しながら出力して、演算部はそれ以降のステージの演算を行うようにしたため、演算部に対して入力時間は同じで、全体として演算時間の短縮に役立ち、伝送情報の入力時間及び演算結果の出力時間を極力少なくすることができ、よって、安価なＤＳＰを用いてＩＤＦＴ演算をソフトウェアにより実行する演算部を実現することができる。
【０１２８】
また、本発明によれば、演算部の速度限界で入力バッファ回路からデータを読み取ることができ、データ入力に関しては、演算部にとって極力無駄な時間を省くことができ、演算部は、最小の時間でＩＤＦＴ演算結果を出力バッファ回路に出力できる。以上より、本発明によれば、装置全体での低コスト化を実現できると共に、余った時間を利用して、他の機能を実施することもできる。
【図面の簡単な説明】
【図１】本発明の要部の一実施の形態を示すブロック図である。
【図２】図１の動作説明用フローチャートである。
【図３】本発明装置で送信するＯＦＤＭ信号の一例の周波数スペクトラムを示す図である。
【図４】図１の要部の詳細ブロック図である。
【図５】図１の要部の伝送情報入力制御回路の一実施の形態を示す回路図である。
【図６】図５の動作説明用タイミングチャートである。
【図７】本発明の要部のステージ演算回路の第１の実施の形態を示す回路系統図である。
【図８】図１の他の要部の詳細ブロック図である。
【図９】本発明の要部のステージ演算回路の第２の実施の形態を示すブロック図である。
【図１０】図９の動作を説明する図である。
【図１１】図９の動作を説明する図である。
【図１２】ステージ演算の動作を説明する図である。
【図１３】本発明の要部のステージ演算回路の第４の実施の形態を示すブロック図である。
【図１４】図１３のステージ演算回路の第４の実施の形態のステージ演算を説明する図である。
【符号の説明】
１ 外部システム
２ 伝送情報入力制御回路
３ ステージ演算回路
４ 伝送情報入力バッファ回路
５ 逆離散的フーリエ変換（ＩＤＦＴ）回路
６ 演算結果出力バッファ回路
７ 演算結果出力制御回路
２１ 第１のカウンタ
２２〜２５、２８、３３ Ｄ型フリップフロップ
３１ 第２のカウンタ
３２ ３ＤＣ検出回路
４１ ラッチ回路
４２、４５ 選択回路
４３、５２、５３、７２、７３ 反転回路
５１、７１ 入力データ分割回路
５４〜６１、７４、７５ 加算回路
７６〜８１ 拡張回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frequency division multiplexing signal transmission apparatus, and in particular, converts an encoded digital video signal or the like into an orthogonal frequency division multiplexing (OFDM) signal of a limited frequency band and transmits the signal. The present invention relates to a signal transmission device.
[0002]
[Prior art]
As one of methods for transmitting an encoded digital video signal or the like in a limited frequency band, multi-level modulated digital information such as 256 quadrature amplitude modulation (QAM) is transmitted using a large number of carriers. An OFDM system for transmitting an OFDM signal is conventionally known. The OFDM system is a system in which a large number of carriers are arranged orthogonally and independent digital information is transmitted on each carrier. Note that “carriers are orthogonal” means that the spectrum of an adjacent carrier becomes zero at the frequency position of the carrier.
[0003]
According to the OFDM method, a guard band period (guard interval) is set, and information of the period is transmitted in an overlapping manner, so that transmission distortion caused by multipath of radio waves can be reduced. That is, the reception of the OFDM signal detects the amplitude and phase modulation components of the signal transmitted within the symbol period, and decodes the value of the information based on these levels. By removing and decoding, the multipath signal of the same symbol section and the signal to be received have the same frequency component, so that decoded digital data with little transmission distortion can be transmitted in a relatively narrow frequency band.
[0004]
Conventionally, the above-mentioned OFDM signal is generated using a single inverse fast Fourier transform circuit (IFFT circuit). This IFFT circuit has a data sequence length N of 2 raised to a power of 2^L  Is a circuit for decomposing a discrete Fourier transform (DFT) of size N into a DFT of size N / 2 and multiplexing butterfly operations, and when the order is k, the real and imaginary parts of k A signal having a value (level) corresponding to the digital value to be transmitted is supplied to the terminal of (1) to obtain a signal for transmitting the digital value. When an inverse DFT (IDFT) operation using N complex numbers is performed during a time interval T, an OFDM signal can be generated, and it is known that each point of the inverse DFT corresponds to a carrier (“data compression and digital modulation”). Nikkei Electronics Book, p. 233).
[0005]
Since a large number of information carriers generated by using this IFFT circuit are modulated and transmitted according to information to be transmitted, an OFDM signal which is a frequency division multiplexed signal of these information carriers takes a form of a random signal. .
[0006]
Here, the IFFT circuit operates at a sample clock frequency higher than a predetermined frequency bandwidth. For example, when an N-point IDFT is calculated by double oversampling, when an input frequency aligned IDFT circuit is used as an IFFT circuit, the 0th to [N / 4] th input terminals and the [3N / Digital information is input to the 4th to [N-1] th input terminals to perform an arithmetic operation to generate an OFDM signal within a modulation band.
[0007]
[Problems to be solved by the invention]
For example, when calculating an N-point IDFT by double oversampling, the 0th to [N / 4] th input terminals of the input frequency aligned IDFT circuit and the [3N / 4] to [N-1] Conventionally, when digital information is input to the first input terminal to generate an OFDM signal within a modulation band, a signal is conventionally input to the [(N / 4) +1] to [(3N / 4) -1] th input terminals. The level is set to zero so that out-of-band signals are not generated.
[0008]
Since the IDFT operation involves a multi-stage butterfly operation and generates an output signal as a result, the IDFT operation is generally performed by a digital signal processor (hereinafter referred to as DSP) in consideration of the flexibility of the apparatus. Can be considered. In this case, if an inexpensive DSP is used, the operation time becomes longer due to the low speed of the DSP. On the other hand, if a high-speed DSP is used to reduce the operation time, such a DSP is considerably expensive, so that the entire device is required. Make it expensive.
[0009]
The present invention has been made in view of the above points, and an object of the present invention is to provide an orthogonal frequency division multiplexed signal transmission device capable of performing a high-speed IDFT operation using an inexpensive DSP.
[0012]
[Means for Solving the Problems]
The present inventionIn order to achieve the above object, digital data as transmission information is input to a plurality of^MAn arithmetic unit for performing an inverse discrete Fourier transform operation by double sampling (where M is any natural number from 1 to 3), and a k-th stage of the inverse discrete Fourier transform of the arithmetic unit (where k is 1 ( (When M = 1), or 1 and 2 (M = 2) Or part of 1 and 2 and 3 (M = 3)), A stage operation circuit composed of a hardware circuit for outputting the operation result as digital data to the operation unit while executing the operation of the stage operation circuit), and the remaining stages after the stage operated by the stage operation circuit. An output buffer circuit that temporarily holds the operation result of the operation unit obtained by performing the operation, and a quadrature modulation after the operation result continuously read from the output buffer circuit is converted into a digital signal or converted to an analog signal. And a transmitting means for transmitting an orthogonal frequency division multiplexed signal output from the orthogonal modulating means.
[0013]
In general, when inputting transmission information from an external system, it is desirable that the read clock be several MHz or less in view of the reliability of the entire apparatus. However, waiting for the transfer time as it is results in a large time loss for the arithmetic unit. However, in the present invention, in the IDFT operation using oversampling by the operation unit, there is a frequency at which the input is set to zero, and the operation of that part can be realized by a small-scale circuit, and the k-th stage of the IDFT operation is used. The operation is performed by the stage operation circuit, which is a hardware circuit, and is output. Therefore, the operation unit only needs to perform the operation of the subsequent stages, so that the input time to the operation unit is the same. As a result, the operation time can be reduced, and the input time of the transmission information and the output time of the operation result can be reduced as much as possible.
[0014]
The present invention also provides a transmission information input control circuit for supplying digital data from an external system to a stage operation circuit in accordance with an input request from an operation unit, and an output operation result of the stage operation circuit under the control of the transmission information input control circuit. After temporarily storing the data, the transmission information input buffer circuit which outputs the digital data to the arithmetic unit and the data amount in the output buffer circuit are monitored. And an operation result output control circuit for outputting the operation result to the output buffer circuit.The operation unit continuously reads the operation result stored in the output buffer circuit at a speed lower than the speed at which the operation result is written to the output buffer circuit. The operation result output control circuit monitors the amount of data stored in the output buffer circuit and, when the amount of data exceeds a predetermined amount, outputs an output signal to be supplied to the operation unit. And a signal non-active, in which a structure for writing to the output buffer circuit an operation result of the arithmetic unit to activate the output request signal becomes less than a predetermined amount of data.
[0015]
Thus, in the present invention, the transmission information is input only by the operation unit issuing the input request signal, the input completion signal is checked when necessary, and the data can be read from the input buffer circuit at the speed limit of the operation unit. . Therefore, in the present invention, as for the data input, the useless time for the operation unit can be reduced as much as possible, and the operation unit can output the IDFT operation result to the output buffer circuit in the minimum time.
[0016]
Further, the present invention provides a stage arithmetic circuit, a holding circuit for sequentially holding digital data to be transmitted by a predetermined bit, and a digital data held by the holding circuit, the upper bit data and the lower bit of a predetermined number of bits. A first selection circuit that selects one of the upper bit data and the lower bit data when the data is divided into two, an inversion circuit that logically inverts all output bit data of the first selection circuit, and a selection circuit And a second selection circuit for selecting one of the output bit data of the inversion circuit and the output bit data of the inversion circuit, and a first and second selection circuit of the first and second selection circuits so that the operation result of the k-th stage is obtained from the second selection circuit. And a control circuit for controlling the selection operation.
[0017]
According to this configuration, the transmission information is performed while performing the first stage when performing the IDFT calculation of double oversampling, and while performing the first stage and the second stage when performing the IDFT calculation of quadruple oversampling. Can be constituted by a hardware circuit.
[0018]
Further, according to the present invention, the first to fourth divisional circuits in which digital data to be transmitted is input to the stage operation circuit and divided by a predetermined number of bits, and the divided data are sequentially collected in groups of four. An input data dividing circuit that outputs data in parallel, a first inverting circuit that inverts the logical values of all bits of the third divided data, and a second inverting circuit that inverts the logical values of all bits of the fourth divided data A first dividing circuit comprising: an inverting circuit; and a total of eight first to eighth adding circuits each of which adds the data input to the first and second input terminals and outputs a stage operation result. The data is input to the first input terminals of the first, third, fifth and seventh adders, and the second divided data is input to the first input terminals of the second, fourth, sixth and eighth adders. The third divided data is input to the input terminal, Input to the input terminal, input the fourth divided data to the second input terminal of the second and third addition circuits, and output the inverted data of the first inversion circuit to the fourth and fifth addition circuits. The configuration is such that the data is input to a second input terminal, and the inverted output data of the second inverting circuit is input to the second input terminals of the sixth and seventh adding circuits.
[0019]
Thus, when performing IDFT calculation in radix 2 using double oversampling, a stage calculation circuit that outputs transmission information while performing the first stage and the second stage can be configured by a hardware circuit. Alternatively, when performing the IDFT operation by double oversampling, a stage operation circuit that executes the first stage of the radix-4 IDFT operation can be configured by a hardware circuit.
[0020]
Further, according to the present invention, the first to fourth divisional circuits in which digital data to be transmitted is input to the stage operation circuit and divided by a predetermined number of bits, and the divided data are sequentially collected in groups of four. An input data dividing circuit for outputting data in parallel, first and second inverting circuits for inverting logical values of all bits of the third and fourth divided data, and adding the third and fourth divided data, respectively. A first adding circuit, a second adding circuit for adding the fourth divided data and the output data of the first inverting circuit, respectively, and a first, a second, a third and a fourth divided data, respectively. First, second, third, and fourth extension circuits that are input and sign-extend at least one bit or more, and a fifth that input output data of the first and second inversion circuits and sign-extend at least one bit or more. And a sixth extension circuit. It is obtained by the.
[0021]
According to the present invention, the output data of the first to sixth extension circuits and the output data of the first and second addition circuits are respectively converted to the first and second IDFT operations in the IDFT operation at the time of 4 × or 8 × oversampling. It can be output as a partial calculation result of the stage calculation and the third stage calculation.
[0023]
Further, according to the present invention, the arithmetic unit sets the output data of the first to sixth extension circuits input via the input buffer circuit to Am, Bm, Cm, Dm, -Cm and -Dm, and the first and the second Assuming that the output data of the adder 2 is Em and Fm, 0, 2, 4, 6, 8, and 8 for a total of 32 addresses from the desired address 0 to the address 1F (hexadecimal) in the internal memory. Addresses A, C and E are Am, 1, 3, 5, 7, 9, B, D and F are Bm, address 10 is + Cm, address 11 is + Dm, address 12 is + SEm and address 13 is + SFm, address 14 is + Dm, address 15 is -Cm, address 16 is + SFm, address 17 is -SEm, address 18 is -Cm, address 19 is -Dm, address 1A is -SEm, address 1B is -SFm, address 1C Is -Dm, 1D is + Cm, 1E is -SFm, 1F Is + SEm (where S = √2), the IDFT operation of the third stage of 8 times oversampling can be executed, and the arithmetic unit can be implemented by a simple hardware configuration. The input time of the transmission information and the output time of the calculation result can be reduced as much as possible.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described. FIG. 1 is a block diagram of a main part of a first embodiment of a frequency division multiplex signal transmitting apparatus according to the present invention. Referring to FIG. 1, an external system 1 is a system for generating digital data to be transmitted. The digital data includes digital video signals and audio signals compressed by an encoding method such as an MPEG method which is a color moving image encoding and displaying method. There are signals.
[0025]
The present embodiment is a device for transmitting digital data from the external system 1, and includes a transmission information input control circuit 2, a stage operation circuit 3, a transmission information input buffer circuit 4, an IDFT operation unit 5, an operation result output buffer circuit 6 And an operation result output control circuit 7, which is not shown in the figure. On the output side of the operation result output buffer circuit 6, a quadrature modulator performs frequency conversion to a transmission frequency band and further performs predetermined transmission processing. A transmission circuit section is provided.
[0026]
The IDFT operation unit 5 is an operation circuit configured by a DSP and performing an inverse discrete Fourier transform (IDFT) by software operation, and performs an operation of all the remaining stages by the stage operation circuit 3. In the present embodiment, when the data sequence N is transmitted on 256 carriers, in the double oversampling, a signal is generated by performing an IDFT operation of M = 2N = 512. At this time, the input assignment to the IDFT operation unit 5 is as follows when the numbers are sequentially assigned in the input frequency alignment type.
[0027]
n = 0 to 128 An information signal for modulating the carrier is provided.
[0028]
n = one hundred twenty-nine to three hundred eighty-three the carrier level to 0 does not generate a signal.
[0029]
n = 384-511 An information signal for modulating the carrier is provided.
[0030]
That is, the number of input terminals of the IDFT operation unit 5 is 512 for the real part (R) signal and 512 for the imaginary part (I) signal, and the first (n = 1) to the 127th (n = 127) of them. And information signals are input to the 385th (n = 385) to 511th (n = 511) total 127 input terminals, and to the 0th (n = 0) input terminal. Is transmitted at the center frequency of a carrier wave to which a DC voltage (constant) is input and transmitted. The 128th (n = M / 4) and 384th (n = 3M / 4) input terminals are for pilot signals, for example. , And is transmitted on a carrier having a frequency at both ends which is a half of the Nyquist frequency.
[0031]
Here, the input information of a total of 128 input terminals from the 1st to the 128th is transmitted by a carrier for information transmission on the upper side (higher frequency side) of the center carrier frequency F0, and a total of 128 input information from the 384th to the 511th is provided. The input information of the input terminal is transmitted by an information transmission carrier below (lower side of) the center carrier frequency. Also, it is assumed that 0 is input to the remaining 129th to 383th input terminals (the ground potential), so that a carrier wave of that portion is not generated (not used for data transmission).
[0032]
Next, an outline of the operation of the embodiment of FIG. 1 will be described with reference to the flowchart of FIG. First, after the power is turned on, when an input request signal a is generated from the IDFT operation unit 5 (step 11), the transmission information input control circuit 2 receives the input request signal a and sends the external system 1 an interval of about 1.6 μs. 248 pulses (RCLK 248 described later) are output at (612.5 kHz), and in synchronization with this, the external system 1 inputs 248 bytes of digital data to the stage operation circuit 3 in parallel for each byte. To generate the input request signal a, one bit of the I / O port is allocated because the IDFT operation unit 5 is embodied by a DSP.
[0033]
An error correction code is added to this digital data, and the stage operation circuit 3 performs the first stage operation of the IDFT operation on the input digital data. Here, the first stage of the output time axis data alignment type IDFT operation of the present embodiment will be described.
[0034]
Generally, {(R1 + R2) / 2} + j (I1 + I2) / 2 for real part data R1 and imaginary part data I1 represented by R1 + jI1 and next real part data R2 and imaginary part data I2 represented by R2 + jI2. , {(R1−R2) / 2} + j (I1−I2) / 2.
[0035]
When calculating data AB, CD, EF,... (Each character indicates a lump every 4 bits), the input frequency assignment and the first stage calculation result are based on the consideration of double oversampling. In the case of complex number and bit reverse,
Frequency input assignment First stage calculation result
0th carrier A + Bj A / 2 + jB / 2
256th carrier 0 + 0j A / 2 + jB / 2
128th carrier 0 + 0j C / 2 + jD / 2
384th carrier C + Dj-C / 2-jD / 2
64th carrier E + Fj E / 2 + jF / 2
320th carrier 0 + 0j E / 2 + jF / 2
192nd carrier 0 + 0j G / 2 + jH / 2
448th carrier G + Hj-G / 2-jH / 2
32nd carrier I + Jj I / 2 + jJ / 2
288th carrier 0 + 0j I / 2 + jJ / 2
160th carrier 0 + 0j K / 2 + jL / 2
416th carrier K + Lj-K / 2-jL / 2
96th carrier M + Nj M / 2 + jN / 2
352nd carrier 0 + 0j M / 2 + jN / 2
224th carrier 0 + 0j O / 2 + jP / 2
480th carrier O + Pj-O / 2-jP / 2
16th carrier Q + Rj Q / 2 + jR / 2
. . . . . . . . . . . . . . . . . . . . . . . .
It becomes. Since "1/2" of the above operation result can be easily operated by bit shift, A, B, A, B, C, D, -C, -D, E, F, E, F , G, H, -G,..., The first stage has been executed.
[0036]
Although not described in this specification, the 0th carrier, the 128th carrier, the 384th carrier, and the like are used as carriers for reference data and synchronization data, and therefore, data at addresses corresponding to these are used before the second stage. Transferred to another address. The data generation speed is set slightly lower than the transmission capacity of the OFDM wave to be transmitted. In order to absorb the difference, the external system 1 is configured to appropriately generate null data.
[0037]
In this way, while the operation of the first stage is being executed by the stage operation circuit 3, the operation result is taken out, supplied to the transmission information input buffer circuit 4, and stored. The transmission information input control circuit 2 outputs an input completion signal b to the IDFT operation unit 5 when the input of the 248-byte transmission information is completed. Thereby, as shown in the flowchart of FIG. 2, the IDFT operation unit 5 checks whether or not the input completion signal b has been input (step 12). When the input completion signal b has been input, it is stored in the transmission information input control circuit 2. The transmission information (digital data) of 248 bytes is read (step 13).
[0038]
Subsequently, the IDFT operation unit 5 outputs the input request signal a to the transmission information input control circuit 2 (Step 14). In response to the input request signal a, the transmission information input control circuit 2 causes the external system 1 to again input 248 bytes of digital data of the next symbol to the stage operation circuit 3, where the first stage operation is executed. After that, it is stored in the transmission information input buffer circuit 4. At this time, the IDFT operation unit 5 executes the IDFT operation of the second stage and subsequent stages on the digital data input in step 13 with double oversampling, and executes the in-phase signal (I signal) and the quadrature signal (Q signal). ) Is obtained (step 15).
[0039]
Subsequently, the IDFT operation unit 5 checks whether or not the output request signal c has been input from the operation result output control circuit 7 (step 16). If the output request signal c has been input, the operation result obtained by the IDFT operation is output as the operation result output. The data is supplied to and stored in the buffer circuit 6 (step 17). After outputting the data, the IDFT operation unit 5 monitors whether the input completion signal a has been input again, and executes the processing of steps 13 to 17 when the input completion signal a has been input.
[0040]
In this way, the output operation result of the IDFT operation unit 5 is such that in one IDFT operation, 248 pieces of input information (248 pieces of data + 9 pieces of reference data and the like) have 512 time-axis signals (I signal and Q signal). Signal) is generated in a burst. The operation result output buffer circuit 6 reads the stored contents continuously at a constant reading speed. That is, the IDFT calculation result is generated in a predetermined amount at regular time intervals. On the other hand, they are transferred to the next-stage quadrature modulator at a predetermined continuous clock. Therefore, the operation result output buffer circuit 6 is provided to adjust the time difference between the output operation result of the IDFT operation unit 5 and the circuits subsequent to the operation result output buffer circuit 6.
[0041]
The IDFT operation results (I signal and Q signal) continuously read from the operation result output buffer circuit 6 are converted into analog signals by a D / A converter and then supplied to an analog quadrature modulator. The signal is supplied to the digital quadrature modulator as it is. Quadrature amplitude modulation (QAM) is performed on the input digital data I and Q signals to generate an OFDM signal composed of 257 information carriers. That is, in the present embodiment, 16 levels (4 bits) of each of the real part and the imaginary part are converted into an amplitude component and a phase component, an I signal and a Q signal are generated, and a total of 257 sets of the I signal and the Q signal are generated. By supplying the signal to the quadrature modulator, an OFDM signal having a center frequency F0 and a frequency spectrum as shown in FIG. 3 is extracted from the quadrature modulator.
[0042]
The OFDM signal in the case where the data series of the IDFT operation unit 5 is 512 has a total of 257 carriers in a frequency band of 99 kHz, and 248 carriers are 256QAM-modulated, each having 1-byte information data. The remaining nine carriers including the center frequency F0 are used for transmitting the auxiliary signal.
[0043]
However, in this case, the frequency spectrum of the OFDM signal is such that the carrier wave higher than the center frequency F0 is the first to 128th real part input terminal and the imaginary part input terminal of the IDFT operation unit 5, as shown in FIG. The carrier wave lower than the center frequency F0 is modulated by the data and the like input to the 384th to 511th real part input terminals and the imaginary part input terminals of the IDFT arithmetic unit 5. Is modulated.
[0044]
As described above, "128" shown in FIG. 3 is a carrier for transmitting a pilot signal generated by the fixed voltage input to the 128th real part input terminal and the imaginary part input terminal of the IDFT operation unit 5, and "-". 128 "is a carrier for transmitting a pilot signal generated by a fixed voltage input to the 384th real part input terminal and the imaginary part input terminal of the IDFT operation unit 5, and these are equivalent to a frequency half the Nyquist frequency. Is a carrier having a frequency of
[0045]
Also, since the first stage is implemented by the stage operation circuit 3 assuming that 0 is inputted to the 129th to 383rd input terminals of the IDFT operation unit 5, as shown in FIG. The carrier waves of "129" to "256" and "-256" to "-129" transmitting the data of the input terminal of "0" are zero.
[0046]
The above-mentioned OFDM signal composed of a plurality of carriers arranged adjacent to each other for each symbol frequency and extracted from the quadrature modulator is transmitted by a transmission circuit unit (not shown), for example, with the center carrier frequency F0 being 100 MHz. The setting of the guard interval will not be described.
[0047]
Next, each component of the embodiment shown in FIG. 1 will be described in more detail. FIG. 4 is a detailed block diagram of a portion including the transmission information input control circuit 2, the stage operation circuit 3, the transmission information input buffer circuit 4, and the IDFT operation section 5 of FIG. 1, and FIG. 5 is the transmission information input control of FIGS. FIG. 6 is a circuit diagram of an embodiment of the circuit 2, and FIG. 6 is a timing chart for explaining the operation of FIGS. (Note that signal 1 and the like described later are described as S1 and the like.)
In FIG. 5, a 2.5 MHz signal (hereinafter, CLKA) obtained by dividing the frequency of 40 MHz (not shown) is input to the transmission information input control circuit 2 and is obtained by dividing the frequency by 情報 by the internal first counter 21. A first frequency-divided clock CLKB and a second frequency-divided clock CLKC obtained by dividing by 1/4 are generated. These clocks are shown in FIG. Here, as shown in FIG. 5, the transmission information input control circuit 2 is connected to the data input terminal of the first stage D-type flip-flop 22 of the four-stage cascade-connected D-type flip-flops 22, 23, 24 and 25. 6, when the input request signal a having the fourth waveform from the top arrives, it is latched as shown in FIG. 6 by the rise of CLKA input to the clock terminal of the D-type flip-flop 22, and the signal S1 is output from the Q output terminal. Is output.
[0048]
The signal S1 is applied to the clock terminal of the D-type flip-flop 23. At the rising edge of the signal S1, the high level fixedly applied to the data input terminal is latched to output the signal S2 as shown in FIG. Further, the signal S3 is generated by the D-type flip-flop 24 to which the signals S2 and CLKC are applied, and the phase of the signal generated by the D-type flip-flop 25 to which the signals S3 and CLKB are applied is inverted by the inverter 26. A signal S4 as shown in FIG. The signal S4 and the output clock CLKC of the counter 21 are respectively supplied to the OR gate 27 shown in FIG. 5 and are subjected to a logical sum operation, thereby generating a pulse RCLK248 as shown in FIG.
[0049]
This pulse RCLK 248 is transferred to the external system 1 shown in FIG. 1 and used as a read clock for transmission information in the external system 1. The inverted signal of the signal S4 (Q output signal of the D-type flip-flop 25) is applied to the data input terminal of the D-type flip-flop 28 shown in FIG. 5, and the rising edge of the third clock CLKC input to the clock terminal. , A WENA1 signal (write enable 1) as shown in FIG. 6 is output from the Q output terminal. The WENA1 signal is used as a write enable signal to the transmission information input buffer circuit 4, and is also supplied to an AND gate 29 to gate the first clock CLKA to generate a WCLK1 (write clock) signal as shown in FIG. Also used to generate.
[0050]
Here, as can be seen from the timing chart of FIG. 6, four write clocks are generated corresponding to one read pulse. This indicates that data is stored in four addresses for one-byte input as described later.
[0051]
The write clock WCLK1 is input to the transmission information input buffer circuit 4 shown in FIGS. 1 and 4 at the rising edge to repeat the writing, and is input to the second counter 31 in FIG. It is used to generate address signals 0 to 9 as shown in FIG. The second counter 31 is cleared by a signal obtained by inverting the phase of the write enable signal WENA1 by the inverter 30.
[0052]
The address signals 0 to 9 are input to the data input terminal of the D-type flip-flop 33 after the address 988 (3DCh) is decoded by the detection circuit 32, and the first clock CLKA is input to the clock terminal of the D-type flip-flop 33. Is input, an RST2 signal (reset) as shown in FIG. 6 is generated from the Q output terminal. The RST2 signal is applied to the reset terminals of the D-type flip-flops 23 and 24 via the inverter 35, and makes the signals S2 and S3 non-active at the rise. Thereafter, the signal S4 changes to the high level, and the generation of the pulse RCLK248 is inhibited (that is, fixed to the high level as shown in FIG. 6). At this point, 248 pulses RCLK 248 are generated.
[0053]
The write enable signal WENA1 subsequently changes to a low level at the rising edge of the third clock CLKC, so that the writing is further continued and finally the addresses 0 to 991 are performed. The write enable signal WENA1 also functions as an input completion signal b by connecting to a predetermined one bit of the I / O port of the IDFT operation unit 5 composed of a DSP.
[0054]
The external system 1 outputs 8-bit data in synchronization with the falling edge of the pulse RCLK248 as shown in FIG. 4 uses the rising edge of pulse RCLK 248 to hold 8-bit data from external system 1 as shown in FIG.
[0055]
Next, the configuration and operation of the stage operation circuit 3 in which the operation of the first stage is performed by a hardware circuit at the time of double oversampling will be described with reference to FIG. As shown in FIG. 7, the stage operation circuit 3 includes a latch circuit 41 for latching input 8-bit data, a selection circuit 42 for selecting output data of the latch circuit 41, an inversion circuit 43 for inverting output data of the selection circuit 42, It comprises an AND gate 44 and a selection circuit 45 for selecting one of the output data of both the selection circuit 42 and the inversion circuit 43.
[0056]
The operation of the stage operation circuit 3 will be described. The 8-bit data AB, CD, EF,... (Each character indicates a lump every 4 bits) arriving from the external system 1 is the rising edge of the pulse RCLK248. It is held by the latch circuit 41 of FIG. 7 using the edge. The selection circuit 42 selects the upper 4 bits or the lower 4 bits of the held 8-bit data by the address signal 0 among the address signals 0 to 9 described above. When the address signal 0 = "L", that is, the upper 4 bits are selected for the even address, and when the address signal 0 = "H", that is, the lower 4 bits are selected for the odd address.
[0057]
Thereafter, the four bits selected by the selection circuit 42 are supplied to the selection circuit 45 as they are, and are also supplied to the inversion circuit 43 and all signals are inverted before being supplied to the selection circuit 45. The selection circuit 45 receives, as a select signal, a signal obtained by performing an AND operation on the address signal 1 and the address signal 2 by the AND gate 44, and when the select signal is "H", that is, when both the address signal 1 and the address signal 2 are used. Only when the signal is "H", the inverted 4 bits are selected, and when the select signal is "L", the output 4 bits of the selection circuit 42 are selected.
[0058]
Therefore, the selection circuit 45 selects the state as it is when the address signal is 0h-5h, 8h-Dh, 10h-15h, 18h-1Dh,..., And 6h-7h, Eh-Fh, 16h-17h, 1Eh ... 1Fh,...
[0059]
The following table summarizes the relationship between these operations and the last four bits.
[0060]
[Table 1]

These four bits output from the selection circuit 45 are sequentially stored in the transmission information input buffer circuit 4 shown in FIGS. 1 and 4, and the arrangement of these values is based on the output time axis data alignment type (input Frequency axis data bit reverse type), which coincides with the result of the first stage in the IDFT operation of twice oversampling.
[0061]
The output of the selection circuit 45 is stored in the transmission information input buffer circuit 4 as a 16-bit data bus, on the assumption that it is operated in two's complement notation. That is, as shown in FIG. 7, the output 4-bit data of the selection circuit 45 is allocated to DATA14 to 11 of the 16-bit data bus DATA0 to DATA15, DATA14 is expanded to DATA15, and DATA10 is set to "H". It is fixed, and DATA9-0 are fixed at "L".
[0062]
Next, these operations will be described. When performing the IDFT operation, the operation of halving the result for each stage does not take much time and is easy. In addition, it is more convenient for software to do so. Therefore, 4-bit data should be placed at the upper position. In consideration of avoiding an overflow and an underflow in half in the first stage, the data is arranged in DATA14 to DATA11. The processing of DATA15 is for sign extension.
[0063]
The designation of "H" for DATA10 is for shifting the signal point arrangement by "0.5" and simplifying the demodulation at the receiver, as generally performed by QAM modulation or the like. Here, in order to invert the sign, all the circuits for inverting the signal are used. However, since the process of adding "0.5" is performed, the result is that the sign is inverted. The following table shows that the result obtained by adding "0.5" to 4-bit DATA and inverting the sign and the result obtained by inverting 4-bit data and adding "0.5" match.
[0064]
[Table 2]

That is, if W, X, Y, and Z are bits of “0” or “1”, respectively, and A, B, C, and D are the inverted values of W, X, Y, and Z, respectively, W, X , Y and Z are added to "0.5" for the 5 bits of "WXYZ1". If this value is inverted and one bit is added to the least significant bit, it becomes "ABCD1". On the other hand, if the above four bits of W, X, Y and Z are inverted, the result is "ABCD". If the value of one bit "1" is added to the least significant part of this value, the result is "ABCD1". Therefore, in the present embodiment, the calculation result of the first stage is obtained by adding "0.5" to the 4-bit data and inverting the sign by the latter method.
[0065]
The 16-bit data obtained by performing the first stage operation by the stage operation circuit 3 as described above is stored in the transmission information input buffer circuit 4 shown in FIG. When the input completion signal (WENA1) b is input from the transmission information input control circuit 2, the IDFT operation unit 5 reads the 16-bit data from the transmission information input buffer circuit 4 at high speed, and executes the IDFT operation for the second and subsequent stages. Perform the operation.
[0066]
FIG. 8 is a detailed block diagram of the IDFT operation unit 5, the operation result output buffer circuit 6, and the operation result output control circuit 7. In the initial state, the data amount in the operation result output buffer circuit 6 is zero.
[0067]
The IDFT operation unit 5 generates about 512 data for each of the I signal and the Q signal in one IDFT operation (for one symbol). Actually, 524 data are generated by adding 12 guard interval data to the 512 data. The operation result output buffer circuit 6 is composed of FIFO-RAMs 6a and 6b of 8k × 16 bits. Therefore, less than about 16 symbols are stored.
[0068]
The operation result output control circuit 7 continues to output the output request signal c until the data amount in the operation result output buffer circuit 6 reaches half. Therefore, the input of the transmission information, the IDFT operation, and the operation result writing are repeated about eight times or more until the output request signal c becomes inactive.
[0069]
The data stored in the operation result output buffer circuit 6 is read out at a predetermined continuous clock and transferred to the next-stage quadrature modulator (not shown). However, the operation of writing the IDFT operation result is slightly faster (the data generation speed is lower). Therefore, the data in the operation result output buffer circuit 6 gradually increases. When the data amount increases and reaches half of the storage capacity of the operation result output buffer circuit 6, the operation result output control circuit 7 detects this and makes the output request signal c non-active.
[0070]
When the output request signal c becomes non-active, the IDFT operation unit 5 does not write the IDFT operation result to the operation result output buffer circuit 6 and waits until the output request signal c becomes active. However, during that time, the data in the operation result output buffer circuit 6 is continuously read out, so that the data amount gradually decreases. When the data amount further decreases and becomes less than half of the storage capacity of the operation result output buffer circuit 6, the operation result output control circuit 7 detects this and sets the output request signal c to an active state, and the IDFT operation is performed. Writing of the output operation result of the section 5 to the operation result output buffer circuit 6 is permitted.
[0071]
In this way, the IDFT operation unit 5 can output and write the IDFT operation result to the operation result output buffer circuit 6 at high speed at the DSP speed limit under the control of the output request signal c. Therefore, with regard to data output, it is possible to save as much useless time as possible for the IDFT operation unit 5 including the DSP.
[0072]
The output request signal c may be replaced by a function of a FIFO-RAM having a half (HALF) flag (a signal pin indicating whether the data amount is half or more or less), or a counter is prepared. Alternatively, it may be realized by counting up with a buffer write clock and counting down with a buffer read clock.
[0073]
As described with reference to the flowchart of FIG. 2, the operation of the IDFT operation unit 5, that is, the DSP, once waits for an input completion signal at the initial stage of turning on the power supply. Each time, the state of waiting for the output request signal is repeated for a substantially constant time.
[0074]
As described above, in the present embodiment, the operation of the first stage of the IDFT operation at the time of double oversampling is realized by the stage operation circuit 3 having the hardware circuit configuration shown in FIG. On the other hand, the input time of the transmission information and the output time of the calculation result can be minimized. Also, the transmission information is input only when the IDFT operation unit 5 issues the input request signal a, the input completion signal b is checked when necessary, and the data is read from the input buffer circuit 4 at the speed limit of the IDFT operation unit 5. Can be.
[0075]
As described above, with regard to the data input of this embodiment, the useless time for the IDFT calculation unit 5 can be reduced as much as possible, and as a result, the calculation time can be reduced. Therefore, the IDFT operation can be executed by using an inexpensive DSP for the IDFT operation unit 5, and the cost of the entire apparatus can be reduced. Further, by shortening the calculation time, the remaining time can be used for realizing other functions.
[0076]
Next, another embodiment of the stage operation circuit 3 according to the present invention will be described. In the above description, the stage operation circuit 3 has been described to perform the operation of the first stage of double oversampling, but it is also possible to perform a part of the IDFT operation of quadruple oversampling. In this case, the stage operation circuit 3 executes the operations of the first and second stages of the IDFT operation.
[0077]
The first and second stages of the IDFT operation at the time of 4 × oversampling will be described. The real part data and imaginary part data (input) of the input, the first stage result and the second stage result are as follows. As shown.
[0078]

(Number is hexadecimal),

Is assigned data,

Is set to zero.
[0079]
Therefore, in the case of 4 times oversampling, the following is obtained.
[0080]

Table 3 shows the relationship between the pulse CLK248, the input 8 bits, the address signal, and the last 4 bits.
[0081]
[Table 3]

Thus, the result of the stage operation is stored in the transmission information input buffer circuit 4. This stage operation circuit can be easily realized by the application described above. This quadruple oversampling has the same effect as the double oversampling.
[0082]
Next, a second embodiment of the stage operation circuit 3 as a main part of the present invention will be described. FIG. 9 is a block diagram of a second embodiment of the stage operation circuit 3 as a main part of the present invention. In this embodiment, in order to facilitate the design of the analog system at the subsequent stage, it is assumed that double oversampling is used, a 256-point IDFT operation is performed in radix-2, and an OFDM signal is generated. Also, 8-bit information is applied to one carrier wave by 256QAM, and the input allocation to the IDFT operation unit is as follows when the numbers are sequentially assigned in the input frequency alignment type.
[0083]
An information signal that modulates a number 0-64 carrier is provided.
[0084]
Numbers 67 to 191 The carrier level is set to 0, and no signal is generated.
[0085]
Nos. 192 to 255 are provided with information signals modulating the carrier.
[0086]
The first and second stages of the output time axis data alignment type IDFT operation will be described. For a bit reverse type frequency input, each operation is as follows.
[0087]

In this repetition, due to double oversampling (number is hexadecimal),

Is assigned data,

Is set to zero.
Therefore, the input assignment and the results of the first and second stages are

Is repeated.
[0088]
FIG. 9 shows that, as described above, when performing an IDFT operation of 256 points in radix 2 using double oversampling, the first stage and the second stage provided on the input side of the IDFT operation unit are performed. FIG. 3 is a block diagram of a stage operation circuit that outputs transmission information. The stage operation circuit of this embodiment is a hardware circuit including an input data division circuit 51, inversion circuits 52 and 53, and addition circuits 54 to 61.
[0089]
In the figure, an input data dividing circuit 51 receives 8-bit data from an external system (not shown) as an input, divides the input data into 4-bit units, and groups the divided 4-bit data into four units sequentially. Output from output terminals A, B, C, D. 4-bit data A from output terminal A_nAre input to one input terminal of each of the first, third, fifth, and seventh two-input adders 54, 56, 58, and 60, and the 4-bit data B from the output terminal B_nAre input to one input terminal of each of the second, fourth, sixth and eighth two-input addition circuits 55, 57, 59 and 61.
[0090]
The 4-bit data C from the output terminal C of the input data dividing circuit 51_nAre input to the other input terminals of the first and eighth 2-input adders 54 and 61, respectively, and the 4-bit data D from the output terminal D_nAre input to the other input terminals of the second and third two-input addition circuits 55 and 56, respectively. Further, the 4-bit data from the output terminals C and D of the input data dividing circuit 51 are input to the inverting circuits 52 and 53, respectively, and after all the bits are logically inverted, the output data (−C_n) Are input to the other input terminals of the fourth and fifth two-input addition circuits 57 and 58, respectively, and output data (−D_n) Are input to the other input terminals of the sixth and seventh two-input addition circuits 59 and 60, respectively.
[0091]
The eight adders 54 to 61 are so-called full adders, and perform an addition operation on 4-bit data input to one input terminal (first input) and the other input terminal (second input). Sign extension with. At this time, +1 is further added. Actually, the above-mentioned sign extension is performed by copying the data of the most significant bit further as the upper two bits so that the data becomes 6 bits as a whole. The data after sign extension is defined as Am, Bm, Cm, Dm, -Cm, and -Dm. Thereafter, these data are calculated in two's complement representation. Thus, the relationship between the inputs and outputs of the adders 54 to 61 is summarized in Table 4 below.
[0092]
[Table 4]

The result of the addition in Table 4 is a result equivalent to the result of the second stage operation described above. For example, as described above, for the inputs to R0, I0, R3, and I3, the result of the second stage operation is (R0 + R3) / 4 and (I0 + I3) / 4 for the inputs of R0 + jI0 and further subsequent R3 + jI3. (R0 + I3) / 4 and (I0-R3) / 4, (R0-R3) / 4 and (I0-I3) / 4 and (R0-I3) / 4 and (I0 + R3) / 4.
[0093]
Here, the above R0, I0, R3, and I3 are represented by A, B, C, and D, respectively. Since 1/4 is obtained by bit shift and ignored, the result of the second stage operation is the same as that of the above input. In this case, {(A + C), (B + D)}, {(A + D), (BC)}, {(AC), (BD)} and {(AD), (B + C) Can be rewritten as｝. As can be seen from Table 4, this is nothing but the output addition results Hm0 to Hm7 of the addition circuits 54 to 61. However, although the sign extension and the addition result of +1 are obtained in the addition results Hm0 to Hm7 of Table 4, since the meaning is not related to the second stage operation result, the addition results Hm0 to Hm7 are substantially the second stage calculation results. It can be seen that this is a calculation result. The same applies to other inputs.
[0094]
In FIG. 9, for simplification of the description, a portion where Hm0 to Hm7 are transmitted to the transmission information buffer circuit is not described, but actually, an eight-input having the same function as the selection circuit 45 in FIG. It can be realized by a one-output type selection circuit. Selection signals can also be easily created.
[0095]
Here, the meaning of the 2-bit sign extension is to avoid overflow and underflow at the time of addition, and corresponds to 1/4 scaling of the second stage operation result described. Further, the addition of +1 is the same as the reason why “H” is given to DATA10 in FIG. 7 in the first embodiment.
[0096]
That is, generally, in QAM modulation and the like, the signal point arrangement is shifted by +0.5 to simplify demodulation at the receiver. Therefore, as a usual method, one bit is added to the above-mentioned input n bits by a logic “1” further lower than the least significant bit. To find the complement, all bits are inverted and LSB is added with "1". Then add. As a simple method of this operation, the complement is equivalent by performing bit inversion and adding +1 after addition.
[0097]
This is because the bit corresponding to 0.5 is always logic "1" and 0.5 + 0.5 = 1 is obtained by the addition. Is always logic "1" and becomes 1 by addition. This situation is shown in FIGS. 10 and 11 for two examples. In both figures, the value obtained by adding +0.5 is represented by "".
[0098]
By such a method, the first and second stages of the IDFT operation can be performed. The above is only an example, and it is essential to obtain a desired result. The eight data obtained from the adders 54 to 61 are passed to the IDFT operation unit 5, and execute the operations of the third and subsequent stages. The final result of the operation is input to a quadrature modulator (not shown), passes through a D / A, a frequency converter, and the like, becomes an OFDM signal, is fed to a transmission antenna via an amplifier, and is emitted.
[0099]
Next, a third embodiment of the present invention will be described. In this case, a 2-point oversampling is performed, an IDFT operation of 256 points in radix 4 is performed, and an OFDM signal is generated. Details of the radix-4 IDFT operation are omitted because there are many other specialized books. The radix-4 basic operation is performed as shown in FIG. The input data is x (0), x (1), x (2), x (3), and the obtained conversion values are X (0), X (1), X (2), X (3). , Twiddle factor WⁿIs exp (-2πjn / 4).
[0100]
The following equation is established from FIG.
[0101]
X (0) = x (0) + x (1) + x (2) + x (3)
X (1) = x (0) + xx (1) -x (2) -xx (3)
X (2) = x (0) -x (1) + x (2) -x (3)
X (3) = x (0) -jx (1) -x (2) + xx (3)
In the input-aligned IDFT operation, when the first stage is performed and the double oversampling is taken into account, the above equation can be expressed as follows because x (1) and x (2) are always zero. .
[0102]
X (0) = x (0) + x (3) = (R0 + R3) + j (I0 + I3)
X (1) = x (0) -jx (3) = (R0 + I3) + j (I0-R3)
X (2) = x (0) -x (3) = (R0-R3) + j (I0-I3)
X (3) = x (0) + jx (3) = (R0−I3) + j (I0 + R3)
Here, x (0) = R (0) + jI0 and x (3) = R3 + jI3 according to the description.
[0103]
As can be seen from the above description, the first stage of the radix-4 IDFT operation is the same operation as the first and second stages of the radix-2 IDFT operation, and can be performed by the same hardware circuit.
[0104]
Next, a fourth embodiment of the stage operation circuit 3 as a main part of the present invention will be described. FIG. 13 is a block diagram of a fourth embodiment of the stage operation circuit 3 as a main part of the present invention. In this embodiment, in order to facilitate the design of the analog system at the subsequent stage, a quadruple oversampling is used, a 512-point IDFT operation is performed, and an OFDM signal is generated. Also, when 8-bit information is applied to one carrier wave by 256QAM and the input allocation to the IDFT operation unit is input frequency-aligned type and the numbers are sequentially assigned, the following is obtained.
[0105]
An information signal that modulates a number 0-64 carrier is provided.
[0106]
Numbers 65 to 447 The carrier level is set to 0, and no signal is generated.
[0107]
Numbers 448-511 are provided with information signals modulating the carrier.
[0108]
The first, second, and third stages of the output time axis data alignment type IDFT operation in this case are as shown in FIG. In addition, the result of the operation of the third stage by the IDFT operation is a repetition of H0 to H7 in the following expression.
[0109]
(Equation 1)

When the equation (1) is further arranged, the following equation is obtained.
[0110]
(Equation 2)

Next, the configuration and operation of the stage operation circuit 3 of FIG. 13 for obtaining the operation result of the third stage will be described. 13, the same components as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 13, the stage operation circuit 3 of this embodiment includes a hardware including an input data division circuit 71, inversion circuits 72 and 73, two-input addition circuits 74 and 75, and six extension circuits 76 to 81. Circuit.
[0111]
In FIG. 13, an input data dividing circuit 71 receives 8-bit data from an external system (not shown) as an input, divides the input data into 4-bit data, collects the divided 4-bit data sequentially into four pieces, and outputs them. Output from terminals A, B, C and D. 4-bit data A from output terminals A, B, C and D_n, B_n, C_nAnd D_nAre input to the first, second, third and fourth extension circuits 76, 77, 78 and 79, and the 4-bit data C from the output terminal C_nAre input to an inverting circuit 72 and an adding circuit 74, and the 4-bit data D_nAre input to the inverting circuit 73 and the adding circuits 74 and 75, respectively. Inverted output data of the inverting circuit 72 (−C_n) Are input to the extension circuit 80 and the addition circuit 75, respectively. Further, the output inverted data (−D_n) Are input to the extension circuit 81.
[0112]
The adders 74 and 75 are so-called full adders, and perform addition and sign extension on 4-bit data input to one input terminal (first input) and the other input terminal (second input). Actually, as in the case of the adders 54 to 61 in FIG. 9, the sign extension is to copy the data of the most significant bit further as the upper two bits, thereby making the data 6 bits as a whole. At this time, +1 is added, and one bit is added to the lower part of the LSB with logic "0" to make 7 bits. That is, since the addition circuits 74 and 75 add 0.5 + 0.5 to 6 bits, 00001.0 (7 bits) is added. Therefore, it is equivalent to adding +1 and adding “0” below the least significant (LSB).
[0113]
Hereinafter, the operation at the time n will be described. The adder circuit 74 sign-extends the 4-bit data of the first input Dn and the second input Cn to 6 bits, and generates an addition operation result (Dm + Cm). Further, +1 is added, and one bit is added to the lower part of the LSB with logic "0" to generate and output 7-bit data Em. Another adder circuit 75 sign-extends the 4-bit data of the first input Dn and the second input -Cn to 6 bits, and generates (Dm-Cm) according to the addition operation result. +1 is added, and one bit is added to the lower part of the LSB with logic “0” to generate 7-bit data Fm.
[0114]
The extension circuit 76 subjects the input 4-bit data An to 2-bit sign extension, adds 1 bit to the lower part of the LSB with logic "1", and outputs extension data Am of 7 bits. Similarly to the above, the other extension circuits 77, 78, and 79 also copy the most significant bits of the input 4-bit data Bn, Cn, and Dn as the upper two bits, and make 6 bits as a whole. The extended data Bm, Cm, and Dm, each of which is made 7 bits by adding 1 bit to the lower logic “1”, are output.
[0115]
The extension circuit 80 extends the 4-bit data -Cn input from the inversion circuit 72 by 2-bit sign extension, and adds 1 bit to the lower part of the LSB with a logic "1" to make the extension data -Cm 7 bits. Generate Further, the extension circuit 81 performs 2-bit sign extension on the 4-bit data -Dn input from the inversion circuit 72, and adds 1 bit with a logic "1" to the lower part of the LSB to make the extension data -Dm 7 bits. Generate
[0116]
Here, the above operation is performed more specifically, for example, “1001 (−7)” for An, “0011 (3)” for Bn, “0001 (1)” for Cn, and “1011 (−5)” for Dn. In this case, the outputs of the inverting circuits 72 and 73 are -Cn = 1110 and -Dn = 0100. The addition circuit 74 sign-extends the above-mentioned Dn to the upper 2 bits to generate Dm = 111011, sign-extends the Cn to the upper 2 bits to generate Cm = 000001, and adds them to generate Dm + Cm = 111100. After that, “111101” is generated as a value (Dm + Cm + 1) obtained by adding +1. One bit “0” is added below the 6-bit LSB to generate “1111010” as 7-bit data Em. Similarly, the adding circuit 75 generates “1110100” as the 7-bit data Fm.
[0117]
Further, since the extension circuits 76 to 81 sign-extend the upper two bits and further add one bit lower to the LSB, the 7-bit data Am of the value of “1110011”, the 7-bit data Bm of the value of “0000111”, 7-bit data Cm having a value of "0000011", 7-bit data Dm having a value of "1110111", 7-bit data -Cm having a value of "1111101", and 7-bit data -Dm having a value of "0001001" are output.
[0118]
Here, assuming that there is a decimal point between the upper 4th bit and the 5th bit of the above 7 bits, Am is "1110.011", which is -1.625, so that (-7 + 0.5) / Equivalent to 4. Similarly, Bm is equivalent to (3 + .5) / 4, Cm is equivalent to (1 + .5) / 4, and Dm is equivalent to (-5 + .5) / 4. Further, -Cm and -Dm are equivalent to sign inversion of Cm and Dm. Further, “1111.010” of Em is “−0.75”, which is equivalent to Dm + Cm, and “1110.100” of Fm is “−1.5”, which is equivalent to Dm−Cm. is there.
[0119]
The eight data of the extended data Am, Bm, Cm, Dm, -Cm, -Dm, Em and Fm obtained as described above are input to the transmission information input buffer circuit 4, respectively. The IDFT operation unit 5 obtains the following expression from the eight data in the transmission information input buffer circuit 4 for the desired 16 addresses (addresses 0 to F) of the memory of the IDFT operation unit 5. And store it.
[0120]
(Equation 3)

The above equation (3) is the same as equation (2). That is, in the equation (2), R0 = Am, I0 = Bm, R7 = Cm, I7 = Dm, S = √2, and further, Dm + Cm = Em, Dm−Cm = Fm, and the equation (2) is used. Is rewritten to obtain equation (4).
[0121]
(Equation 4)

When H0 to H7 in the expression (4) are divided into real and imaginary parts and stored at respective addresses, the result is equivalent to the expression (3). Therefore, a part of the first, second, and third stages of the IDFT operation can be executed by the stage operation circuit 3 of the hardware circuit shown in FIG. The above is only an example, and it is essential to obtain a desired result. Further, when it is desired to implement the third stage part by hardware, an adder may be provided, and Am + Cm or the like may be implemented by hardware.
[0122]
After repeating the above operation of obtaining 16 data 64 times, the IDFT operation unit 5 further executes the operation of the fourth stage and thereafter. The final result of the operation is input to a quadrature modulator (not shown), passes through a D / A, a frequency converter, and the like, becomes an OFDM signal, is fed to a transmission antenna via an amplifier, and is emitted.
[0123]
Next, a case in which 8-times oversampling is used in the above embodiment will be described. In this case, the IDFT operation is further simplified because R7 + jI7 and R8 + jI8 become zero. That is, the equation corresponding to equation (2) is as follows.
[0124]
(Equation 5)

As can be understood from the equation (5), the operation until the eight data are stored in the buffer circuit 4 is the same as that in the fourth embodiment. The operation of the expression (5) may be performed on the desired 32 addresses. That is, for a total of 32 addresses from the desired address 0 to the address 1F (hexadecimal) in the memory in the IDFT operation unit 5, the addresses 0, 2, 4, 6, 8, A, C, and E are Am, 1, 3, 5, 7, 9, B, D and F each address is Bm, 10 address is + Cm, 11 address is + Dm, 12 address is + SEm, 13 address is SFm, 14 address is + Dm, 15 address Is -Cm, address 16 is + SFm, address 17 is -SEm, address 18 is -Cm, address 19 is -Dm, address 1A is -SEm, address 1B is -SFm, address 1C is -Dm, address 1D is + Cm, The address is calculated and stored so that address 1E is -SFm and address 1F is + SEm (where S = $ 2).
[0125]
In this manner, the operation up to a part of the third stage is completed by the stage operation circuit 3, and the IDFT operation unit 5 repeats the above operation of obtaining 32 data 32 times, and then further executes the fourth stage The following calculation is performed.
[0126]
Although the above description has been made up to an eight-fold oversampling, the present invention is not limited to this, and even more samples can be applied. These stage arithmetic circuits can be easily inferred from the description of the above embodiment.
[0127]
【The invention's effect】
As described above, according to the present invention, the operation of the k-th stage of the IDFT operation is output while being executed by the stage operation circuit which is a hardware circuit having a simple configuration, and the operation unit performs the operation of the subsequent stages. Is performed, the input time to the arithmetic unit is the same, which contributes to shortening the arithmetic time as a whole, and the input time of the transmission information and the output time of the arithmetic result can be reduced as much as possible. , An operation unit that executes the IDFT operation by software can be realized.
[0128]
Further, according to the present invention, data can be read from the input buffer circuit at the speed limit of the arithmetic unit, and for data input, useless time for the arithmetic unit can be reduced as much as possible. Can output the IDFT operation result to the output buffer circuit. As described above, according to the present invention, it is possible to reduce the cost of the entire apparatus and to perform other functions by using the extra time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a main part of the present invention.
FIG. 2 is a flowchart for explaining the operation of FIG. 1;
FIG. 3 is a diagram showing a frequency spectrum of an example of an OFDM signal transmitted by the apparatus of the present invention.
FIG. 4 is a detailed block diagram of a main part of FIG. 1;
FIG. 5 is a circuit diagram showing an embodiment of a transmission information input control circuit of a main part of FIG. 1;
FIG. 6 is a timing chart for explaining the operation of FIG. 5;
FIG. 7 is a circuit diagram showing a first embodiment of a stage operation circuit as a main part of the present invention.
FIG. 8 is a detailed block diagram of another main part of FIG. 1;
FIG. 9 is a block diagram showing a second embodiment of the stage operation circuit according to the present invention;
FIG. 10 is a diagram illustrating the operation of FIG. 9;
FIG. 11 is a diagram illustrating the operation of FIG. 9;
FIG. 12 is a diagram illustrating an operation of a stage operation.
FIG. 13 is a block diagram illustrating a fourth embodiment of a stage operation circuit according to the present invention;
FIG. 14 is a diagram illustrating the stage operation of the fourth embodiment of the stage operation circuit of FIG. 13;
[Explanation of symbols]
1 external system
2 Transmission information input control circuit
3 stage arithmetic circuit
4 Transmission information input buffer circuit
5. Inverse discrete Fourier transform (IDFT) circuit
6 Operation result output buffer circuit
7 Operation result output control circuit
21 First counter
22-25, 28, 33 D-type flip-flops
31 Second counter
32 3DC detection circuit
41 Latch circuit
42, 45 selection circuit
43, 52, 53, 72, 73 inverting circuit
51, 71 input data division circuit
54-61, 74, 75 Adder circuit
76-81 Extension circuit

Claims (9)

An arithmetic unit for inputting digital data as transmission information to a plurality of input terminals and performing an inverse discrete Fourier transform operation by oversampling 2 ^M times (where M is any natural number from 1 to 3);
The k-th stage of the inverse discrete Fourier transform of the arithmetic unit (where k is 1 (when M = 1), or 1 and 2 (when M = 2 ), or a part of 1 and 2 and 3 ( M = 3 ) a stage operation circuit composed of a hardware circuit that outputs the operation result as the digital data to the operation unit while executing the operation of
An output buffer circuit that temporarily holds the operation result of the operation unit obtained by performing the operation of all remaining stages after the stage operated by the stage operation circuit;
Quadrature modulation means for performing quadrature modulation after converting the operation result read continuously from the output buffer circuit as a digital signal or as an analog signal,
Transmitting means for transmitting an output orthogonal frequency division multiplexed signal of the orthogonal modulation means ,
A frequency division multiplexing signal transmission device comprising: A transmission information input control circuit for supplying digital data from an external system to the stage operation circuit in accordance with an input request from the operation unit, and temporarily storing an output operation result of the stage operation circuit under the control of the transmission information input control circuit After that, the transmission information input buffer circuit for outputting the digital data to the arithmetic unit and the amount of data in the output buffer circuit are monitored, and when the amount becomes smaller than a predetermined amount, an output request signal is generated and the arithmetic unit 2. A frequency division multiplexed signal transmitting apparatus according to claim 1, further comprising: an operation result output control circuit for supplying the operation result to the apparatus and outputting the operation result. 2. The frequency division multiplexed signal transmitting apparatus according to claim 1, wherein k = 1 and M = 1.
The stage operation circuit includes:
A holding circuit for sequentially holding digital data to be transmitted by predetermined bits,
When the digital data held by the holding circuit is divided into upper bit data and lower bit data of a predetermined number of bits, respectively, a first selection for selecting one of the upper bit data and the lower bit data Circuit and
An inverting circuit that logically inverts all output bit data of the first selecting circuit;
A second selection circuit that selects one of output bit data of the selection circuit and output bit data of the inversion circuit;
A control circuit for controlling a selection operation of the first and second selection circuits so that an operation result of the k- th stage (k = 1) is obtained from the second selection circuit ;
A frequency division multiplexing signal transmission device comprising: 2. The frequency division multiplexing signal transmitting apparatus according to claim 1, wherein k = 1 and 2, M = 2,
The stage operation circuit includes:
An input data dividing circuit for receiving digital data to be transmitted, dividing the data into a predetermined number of bits, and outputting in parallel first to fourth divided data obtained by sequentially grouping the divided data into four pieces; ,
A first inverting circuit for inverting logical values of all bits of the third divided data;
A second inverting circuit for inverting logical values of all bits of the fourth divided data;
A total of eight first to eighth adders for adding the data input to the first and second input terminals and outputting a stage operation result, respectively;
The first divided data is input to first input terminals of odd-numbered first, third, fifth, and seventh adders, and the second divided data is converted to even-numbered second, 4, input to a first input terminal of a sixth and eighth adder circuit, input the third divided data to a second input terminal of the first and eighth adder circuit, The divided data is input to second input terminals of the second and third adders, and inverted output data of the first inverter is input to second input terminals of the fourth and fifth adders. A frequency division multiplexed signal transmitting apparatus characterized in that inverted output data of the second inverting circuit is inputted to second input terminals of the sixth and seventh adding circuits. The first to eighth adders arithmetically add the n-bit data input to the first and second input terminals thereof to m bits by sign-extending at least one bit or more to m bits, 5. The frequency division multiplexed signal transmission device according to claim 4, further comprising adding +1. The frequency division according to claim 5 , wherein the stage operation circuit executes a first stage and a second stage of a radix-2 IDFT operation when the operation unit performs the IDFT operation with double oversampling. Multiplex signal transmitter. 6. The frequency division multiplexed signal transmitting apparatus according to claim 5 , wherein the stage operation circuit executes a first stage of a radix-4 IDFT operation when the operation unit performs the IDFT operation with double oversampling. . 2. The frequency division multiplexed signal transmitting apparatus according to claim 1, wherein k = 1, a part of 2 and 3, M = 3,
The stage operation circuit includes:
An input data dividing circuit for receiving digital data to be transmitted, dividing the data into a predetermined number of bits, and outputting in parallel first to fourth divided data obtained by sequentially grouping the divided data into four pieces; ,
A first inverting circuit for inverting logical values of all bits of the third divided data;
A second inverting circuit for inverting logical values of all bits of the fourth divided data;
A first adding circuit for adding the third divided data and the fourth divided data, respectively;
A second adding circuit for adding the fourth divided data and the output data of the first inverting circuit, respectively;
First, second, third and fourth extension circuits to which the first, second, third and fourth divided data are respectively input and sign-extended by at least one bit;
Fifth and sixth extension circuits to which output data of the first and second inversion circuits are input and sign-extends at least one bit or more;
And the output data of the first to sixth extension circuits and the output data of the first and second adder circuits are first and second of the IDFT operation at the time of 4 times or 8 times oversampling, respectively. A frequency division multiplexed signal transmission device characterized in that it is configured to output a result of a part of a stage operation and a third stage operation. The first and second addition circuits sign-extend at least one bit of the n-bit data input to the first and second input terminals, arithmetically add the data, and further lower-order the LSB. The first to sixth extension circuits add one bit with logic "0" to m bits, and the first to sixth extension circuits perform logic "1" at the lower level of the LSB of data obtained by sign-extending the input data by at least one bit. The arithmetic unit converts the output data of the first to sixth extension circuits input via the input buffer circuit into Am, Bm, Cm, Dm, -Cm and -Dm by adding 1 bit to m bits. Assuming that the output data of the first and second adder circuits are Em and Fm, 0, 2 and 3 are assigned to a total of 32 addresses from the desired address 0 to 1F (hexadecimal) in the internal memory. , 4, 6, 8, A, C and Are Am, 1, 3, 5, 7, 9, B, D, and F are Bm, 10 is + Cm, 11 is + Dm, 12 is + SEm, 13 is + SFm, and 14 is + Dm, address 15 is -Cm, address 16 is + SFm, address 17 is -SEm, address 18 is -Cm, address 19 is -Dm, address 1A is -SEm, address 1B is -SFm, address 1C is -Dm, 1D 9. The frequency division multiplexed signal transmission according to claim 8 , wherein an IDFT operation of eight times oversampling is performed so that the address is + Cm, the address 1E is -SFm, and the address 1F is + SEm (where S = Ｓ2). apparatus.

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