JP3554651B2 - High-speed sequence control method and apparatus, program creation method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-speed sequence control method, a high-speed sequence control method, a program, and a program creation method. The present invention relates to a high-speed sequence control method and apparatus for performing high-speed sequence control using this control table, and a program creation method therefor.
[0002]
[Prior art]
In the conventional sequence control method, in many cases, a dedicated computer for device control called a programmable controller is used, and a dedicated control program corresponding to an operation specification of a control target is input to the computer, and the sequence of the device is controlled. Control. The control program is described by a ladder diagram, an SFC (Sequential Function Chart), or the like. In particular, a process requiring a high-speed response needs to be described as an interrupt program different from a normal program. A well-known example of a sequence control method using this interrupt program is described in “Hitachi Programmable Controller HIDIC H Series CPU Module Operation Manual (Software) NB323C” (Hitachi, 1995). 15-30. Hereinafter, an operation example when this interrupt program is used will be described.
[0003]
FIG. 2 is a timing chart showing the relationship between the cycle of the scan processing and the cycle of the state change of the input signal in the programmable controller. The cycle of the state change of the input signal is longer than one cycle of the scan processing, that is, the scan time. Show the case. Here, in the program processed in the scan process 202, a process of detecting an event that the input signal 201 changes from OFF to ON, that is, a process of detecting a rising edge, is described. This process is executed during one cycle of the scan process. The timing 203 is indicated by an upward arrow. FIG. 2 shows that the rising edge of the input signal 201 is completely captured.
[0004]
On the other hand, FIG. 3 shows a case where the cycle of the state change of the input signal is shorter than the scan time. The program to be scanned is the same as in FIG. In FIG. 3, since the change of the input signal 301 is fast, the scan processing 302 cannot follow the change, and a missing detection 304 of the rising edge of the input signal 301 occurs.
[0005]
FIG. 4 shows a case in which an interrupt process is used together to cope with such a high-speed state change that makes it difficult to follow the scan process. The interrupt process 402 is a process that is started by a timer or the like that interrupts at a fixed cycle, and the interrupt cycle can follow a change in the input signal 401. In the program processed in the interrupt processing 402, processing for detecting the rise of the input signal 401 is described, and the timing 403 of this processing is indicated by an upward arrow. In FIG. 4, the rising of the input signal 401 is completely captured. It is assumed that one cycle of the interrupt processing 402 is shorter than the interrupt cycle itself. Further, in the program processed in the normal scan process 404, other processes except for the process described in the program processed in the interrupt process 402 are described. Here, the scan process 404 itself is intermittent because it is interrupted by the interrupt process 402, and the scan time is longer than in FIGS. 2 and 3, but in consideration of the total performance of the system, the input signal 401 Responsiveness to is improved.
[0006]
[Problems to be solved by the invention]
In the above-described conventional technology, a process requiring a high-speed response is described as an interrupt program separate from the normal sequence. However, even in a process requiring such a high-speed response, the process frequently synchronizes with other normal sequence processes. When viewed as a series of sequences that need to be performed, a process that requires a high-speed response is often substantially mixed in a normal sequence. For this reason, in the conventional method in which the normal sequence and the processing requiring a high-speed response are described separately from the beginning, the description of the program itself becomes complicated, and as a result, the visibility of a series of sequences is impaired. This makes it difficult to change the sequence.
[0007]
Therefore, in the present invention, when describing a series of sequences, particularly steps that require a high-speed response are designated by marks indicating high-speed processing, and a high-speed sequence control program in which a normal sequence and a high-speed sequence are mixed at the step level is used. It is an object of the present invention to provide a high-speed sequence control method and apparatus for automatically generating a sequence control table and controlling a high-speed sequence using the high-speed sequence control table, and a program creation method therefor.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, among the steps of the sequence control program, a mark is added to a step requiring high-speed processing, and the high-speed step to which the mark is added and the mark are added. Generating a high-speed and normal intermediate code by separating no normal steps, further generating a high-speed execution program and a normal execution program from each of the intermediate codes, and synchronizing the steps being executed between the high-speed execution program and the normal execution program A high-speed sequence control method characterized in that the high-speed execution program is executed while taking into account.
[0009]
Also, the present invention provides the high-speed execution program, wherein a command list for storing a command sequence of the high-speed step, an end condition of a current step, a step number to be executed next, and A high-speed sequence control table comprising a control table for storing an entry address of a command sequence to be executed and an entry table for storing an entry address of the control table in each step. A control method is disclosed.
[0011]
Further, the present invention is a high-speed sequence control device for performing high-speed sequence control using the sequence control program created by the method for creating a sequence control program described above,
Intermediate code generating means for generating a high-speed and normal intermediate code by separating the high-speed step to which the mark is added and the normal step to which the mark is not added,
Execution program generation means for generating a high-speed execution program and a normal execution program from each of the intermediate codes;
A processor for executing the high-speed execution program while synchronizing steps during execution between the high-speed execution program and the normal execution program,
A high-speed sequence control device characterized by comprising:
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is a block diagram schematically showing a processing flow in the high-speed sequence control method according to the present invention. First, a series of sequence control programs 102 are created by the sequence control program editing means 101, and steps requiring high-speed response are marked with high-speed processing. The sequence control program 102 created in this way is separated and converted into a normal sequence control internal code 104 and a high-speed sequence control table 105 by the sequence control program conversion means 103. In the high-speed sequence control table 105, processing that requires a high-speed response specified by a mark, that is, data for controlling a high-speed sequence is stored in a table format suitable for high-speed processing. On the other hand, in the normal sequence control internal code 104, processing other than the high-speed sequence allocated to the high-speed sequence control table 105, that is, an internal code sequence (executable program) of the normal sequence is stored. Here, the normal sequence control internal code 104 is interpreted and executed by the normal sequence control internal code execution means 106. Further, in parallel with this, the high-speed sequence control table 105 is processed by the high-speed sequence control table processing means 107. As described above, when the sequence control program 102 is created, the high-speed sequence control table 105 can be automatically generated only by designating the steps that require the high-speed response by the mark. Can be easily described in a natural form without impairing the visibility as a series of sequences. That is, since the sequence can be created and changed more easily than before, the program development efficiency and maintainability are improved.
[0013]
FIG. 5 shows an example of the sequence control program 102 described by the sequence control program editing means 101 in FIG. In FIG. 5, a graphic programming language that expresses a series of sequences in a Petri net format is used. A known example of such a language is disclosed in Japanese Patent Application Laid-Open No. 7-72920. Language. In this cell control language, a place of a Petri net (denoted by a circle in the figure) is defined as an operation per step of a device (hereinafter, referred to as a unit) constituting a cell of a factory automation (FA) system. Then, each place is assigned a step number, which is the reference number of the step. (For example, S100). A transition (denoted by in the figure) is defined as a transition condition to the next step. Further, a so-called safe Petri net in which a place having a token (not shown in the figure) is set as a step being executed and each place includes at most one token at a time is considered.
[0014]
Step No. of place 501 in FIG. Is S102, and the operation of the unit in that step is described as a command sequence using the sequence control program editing means 101 in FIG. The transitions 502, 503, and 504 on the output side of the place 501 use the end conditions OK1, OK2, and OK3 of step S102 as transition conditions, respectively, and use the sequence control program editing means 101 for each of the end conditions OK1, OK2, and OK3. Are described as conditional expressions relating to input / output signals. FIG. 5 shows only the sequence notation, and does not show these command strings and conditional expressions (examples of command strings and conditional expressions will be described later).
[0015]
In the present invention, the use of the cell control language as described above is slightly extended to mark places requiring high-speed processing. For example, the place 505 has a square mark at the upper right of a normal place symbol (denoted by a circle in the figure) such as the place 501, and a transition on the input side of the place (in the case of the place 505, This means that it is necessary to respond at high speed to the state transition of transition 503). Let's call this mark the fast option for the place. As described above, when a part of the sequence requires a high-speed response, simply adding the high-speed option to the place will cause the step to be processed as a high-speed sequence. For example, in the place 505, whether or not the transition condition of the input transition 503, that is, the end condition OK2 in step S102 is satisfied is performed in the interrupt processing 402 of FIG. 4, and if the end condition OK2 is satisfied. Then, a command sequence that defines the operation of step S105 is executed, and a high-speed response to a state change is possible. Further, a normal place step without the high-speed option is executed in a normal scan process.
[0016]
Such a notation method in which a mark is added to a step requiring a high-speed response in a series of sequences to distinguish the steps from each other is not prepared even in the related art such as the SFC. Thus, FIG. 6 shows an example in which a similar extension is made to the SFC notation. In FIG. 6, the upper right corner of the step element of the SFC (denoted by □ in the figure) is painted in a triangular shape to give the same meaning as the high-speed option in FIG. For example, step 601 (S105) has the high-speed option, and the monitoring of the condition described in the transition (t1022) on the input side is performed in the interrupt processing. It should be noted that SFC is a notation that originates from Petri nets, and the following description using Petri nets as an example is also valid when SFC is used.
[0017]
Also, when describing a Petri net as shown in FIG. 5, the sequence control program editing means 101 presupposes that the operation in each step is described by a command sequence and the transition condition of each transition is described by a conditional expression. Even when these are described in a conventional ladder diagram, function block diagram, or the like, the high-speed sequence control method described below can be similarly realized.
[0018]
FIG. 7 shows a coded version of the sequence control program 102 of FIG. 5 and has a structure corresponding to the Petri net notation of FIG. The sequence control program editing means 101 shown in FIG. 1 edits the sequence control program 102 in the Petri net format shown in FIG. 5 and finally saves it in a code format as shown in FIG. Here, the conversion from the Petri net format to the code format is automatically performed by the processing of the sequence control program editing means 101. Further, it is assumed that the sequence control program conversion means 103 processes the sequence control program 102 in a code format as shown in FIG. 7 as an input.
[0019]
The sequence control program in FIG. 7 is roughly composed of two blocks. One is a normal sequence block 701, and the other is a high-speed sequence block 702 that starts with a #INTERRUPT statement 703. The high-speed sequence block 702 is a collection of descriptions of places with the high-speed option among the places of the Petri net in FIG. 5, and the normal sequence block 701 is a collection of descriptions of other places. . Further, the normal sequence block 701 and the high-speed sequence block 702 are respectively composed of a cell block 704 starting with a “cell” statement 706 and a def block 705 starting with a “def” statement 707. The cell block 704 includes the connection relationship between places and transitions, that is, the structure of the Petri net, and the processing in each place. The cell label 708 includes the step number of each place. (S101) and the unit NO. (UNIT1) is described. The transition condition expression 709 includes the step number of the place connected as an input to the transition on the input side of the place. (S100) and an end condition name (OK1) are described. When there are a plurality of transitions on the input side as in S108 of FIG. 5, step NO. Of the place connected as an input to the transition is performed. And the end condition name are described after the symbol "|" meaning OR. In the command column 710, a command that defines processing per step is described. The def block 705 includes a conditional expression that defines the end condition of the step of each place. The def label 711 includes the step number of each place. (S101) is described. The end condition expression 712 describes an end condition name (OK1) of each step and a conditional expression that defines it. In the case of a step having several termination conditions as in S102 in FIG. 5, a plurality of termination condition names and conditional expressions are described. The description of the high-speed sequence block 702 is the same as that of the normal sequence block 701 described above.
[0020]
Further, the sequence control program of FIG. 7 (that is, FIG. 5) is modularized for each unit that is an operation main body of the sequence. For example, FIG. 7 shows a module of UNIT1. As described above, each module of the sequence control program 102 has the unit No. Are distinguished by
[0021]
FIG. 8 is a flowchart showing the processing of the sequence control program conversion means 103 of FIG. The sequence control program conversion means 103 first analyzes the input sequence control program 102 (process 801), and generates a sequence control intermediate code based on the information obtained by this analysis (process 802). Next, the normal sequence control internal code 104 and the high-speed sequence control table 105 are generated from the sequence control intermediate code (steps 803 and 804).
[0022]
FIG. 9 is a detailed flowchart of the sequence control program analysis processing 801. Assuming that the sequence control program of FIG. 7 has been input, first, a data area for storing the Petri net structure, the command string, and the end condition of the normal sequence block 701 is secured (process 901). Next, the cell block 704 and the def block 705 of the normal sequence block 701 are sequentially analyzed. In the analysis of the cell block 704, one unprocessed place is extracted (process 909), the Petri net structure of the place is analyzed (process 902), and the command string 710 and the like are further analyzed (process 903). Such an analysis is repeated until there is no description of the next place (process 904). In the analysis of the next def block 705, one unprocessed place is taken out (process 910), the end condition expression 712 of the place is analyzed (process 905), and this is repeated until there is no description of the next place (process 905). Process 906). With the above processing, the analysis of the normal sequence block 701 is completed. However, if the #INTERRUPT statement 703 is described subsequently (processing 907), it is known that the high-speed sequence block 702 exists, and the data for the analysis is obtained. An area is secured (process 908), and thereafter, the same process as in the normal sequence block 701 is performed.
[0023]
FIG. 10 is a detailed flowchart of the net structure analysis process 902 for each place in FIG. In this net structure analysis, the cell label 708 and the like and the transition condition expression 709 and the like are analyzed. In the analysis of the cell label 708 and the like, the step NO. Is extracted (process 1001), and the unit No. of the current place is further extracted. Is extracted (process 1002). In the analysis of the transition condition expression 709, one unprocessed transition condition expression is extracted (process 1006), and the transition connected as an input to the transition on the input side of the current place, that is, the immediately preceding place (hereinafter, the previous place) Step NO.) Is extracted (step 1003), and the end condition name of the previous place is extracted (step 1004). If there is another transition condition expression 709 in the current place, the processes 1003 and 1004 are repeated (process 1005). Note that the presence of a plurality of transition condition expressions 709 in the current place corresponds to the presence of a plurality of transitions on the input side of the current place.
[0024]
FIG. 11 is a detailed flowchart of the command line analysis process 903 for each place in FIG. In this command string analysis, commands are extracted one by one from the command string 710 or the like of the current place (step 1101), and this is repeated until there is no next command (step 1102).
[0025]
FIG. 12 is a detailed flowchart of the processing 905 of the end condition analysis for each place in FIG. In this end condition analysis, the step NO. Is extracted (process 1201), one unprocessed OK condition is extracted (process 1206), and the end condition expression 712 and the like are extracted (process 1202). This process is repeated until the OK condition for the place is removed (process 1203). Note that the end condition expression 712 and the like include not only a conditional expression (hereinafter, an OK conditional expression) defining an OKn end condition indicating a normal end, but also a conditional expression (hereinafter, NG) defining an NGn end condition indicating an abnormal end. Conditional expression), and this case is similarly analyzed in processing 1207, 1204, and 1205.
Each data extracted in the sequence control program analysis processing 801 described above is stored in step NO. And stored as structured data that can be searched by the end condition name.
[0026]
FIG. 13 is a flowchart showing details of the sequence control intermediate code generation processing 802 in FIG. In the sequence control intermediate code generation, one unprocessed unit is first extracted (process 1311), and the data of the net structure, command sequence, and end condition of the normal sequence and the high-speed sequence are loaded (processes 1301, 1302). Next, step NO. One of the data of the place having the smaller size is fetched (processing 1312). If this is the place with the high-speed option (processing 1303), the high-speed sequence intermediate code buffer is selected (processing 1305). ), A normal sequence intermediate code buffer is selected (process 1304). Here, it is assumed that two intermediate code buffers are prepared for each unit: a normal sequence and a high-speed sequence. Next, an intermediate code for each place is generated and output to a buffer (process 1306). Further, step NO. If there is a place with a larger value, the process returns to the process 1312 and the same process is repeated (process 1307). When there is no next place, the unit number is higher than the current unit. If there is a module of a larger unit, the process returns to the process 1311 to repeat the same process (process 1308). As described above, after generating the intermediate codes for the modules of all the units, first, the intermediate code buffers of the normal sequence are combined and stored (processing 1309). Further, the intermediate code buffers of the high-speed sequence are combined and stored (process 1310).
[0027]
FIG. 14 is a flowchart showing details of the intermediate code generation processing 1306 for each place in FIG. In this process, first, one previous place is taken out (process 1406), and the step NO. (= I) is obtained (process 1401). Next, the step NO. And an end condition, and a conditional expression of the end condition of the previous place is obtained from the end condition data (process 1402). Next, the first half of the IF statement, which is the basic form of the intermediate code, is generated from these data and output to the buffer (process 1403). Here, "IF Sj == Executing & conditional expression->" means "if the conditional expression of the end condition is satisfied after execution of step j". The command “TERM Sj” means “end step Sj”, and “EXEC Si” means “execute step Si”. Next, the command string of the current place Si is output to the buffer continuously (process 1404). This completes the processing for one previous place. If there is another previous place, that is, if there is another transition on the input side of step Si, the process returns to step 1406 and the same processing is repeated (step 1405). ).
[0028]
FIG. 15 shows the sequence control program 102 of FIG. 7 converted into an intermediate code. Similarly to FIG. 7, the intermediate code is also composed of two blocks, a normal sequence block 1501 and a high-speed sequence block 1502. Here, the intermediate code has an IF sentence as shown in the IF sentence 1503 as a basic form, and a collection of these becomes a block.
[0029]
FIG. 16 shows an example in which the normal sequence control internal code 104 is generated from the IF sentence of the normal sequence intermediate code. The internal code is actually in a binary format, but is shown in a mnemonic format in FIG. An internal code 1606 is generated from the condition part 1602 of the IF statement 1601, and an internal code 1607 is generated from the command sequence 1603. Thus, the internal code of the IF statement 1601 is a block 1604 starting from the “STTi” internal code 1605. The "STTi" internal code 1605 is used when executing the internal code.
[0030]
FIG. 17 is a flowchart showing details of the process 803 in FIG. 8 for generating the normal sequence control internal code 104 as shown in FIG. First, the intermediate code of the normal sequence is loaded (processing 1701). Next, the unprocessed IF statements of the intermediate code are fetched one by one (processing 1709), and the steps from the conditional part “IF Si ==. NO. (= I) is extracted (processing 1702). In this step NO. If i is not the same as the condition part of the previous IF statement (step 1703), the internal code “STTi” is generated (step 1704). Next, an internal code is generated from the conditional expression (processing 1705), and an internal code is generated from the command sequence (processing 1706). Thereafter, if there is a next IF statement, the process returns to step 1709, and the same processing is repeated (step 1707). After processing all IF statements, an address table indicating where each "STT" internal code is located in the normal sequence control internal code 104 is generated (process 1708).
FIG. 18 shows the internal sequence block of the normal sequence block 1501 of FIG. A block 1801 is obtained by internally coding the IF statement 1503.
[0031]
FIG. 19 shows an example in which the high-speed sequence control table 105 is generated from the IF statement of the high-speed sequence intermediate code. As shown in FIG. 19, the high-speed sequence control table 105 includes three pieces of data: an entry table 1906, a control table 1907, and a command list 1908. The entry table 1906 is a table for storing an entry address in the control table 1907 when registering the content of the IF statement in the control table 1907. The entry table 1906 contains the step NO. Is a one-dimensional array subscripted with the current step NO. , The entry address of the control table 1907 can be uniquely specified. Step No. irrelevant to the high-speed sequence intermediate code In the case of, the entry table 1906 stores a value (FFFF in hexadecimal notation) which means that it is not registered. In the control table 1907, the condition part of the IF statement and the step NO. A field for updating is stored, a field for storing the number of transitions on the output side (hereinafter, the number of branches), a field for storing a conditional expression, and a next step NO. And a field for storing an entry address to the command list 1908. The command list 1908 is an area in which a command string of an IF statement is internally coded and stored. An end code (CmdListEndCode) is added so that the end of each command sequence can be recognized. By using the high-speed sequence control table 105 having the above configuration, the current step NO. Can be called efficiently, and the processing time can be shortened. As described above, the high-speed sequence control table 105 is executed by interrupt processing. The time required for the interrupt processing, that is, the interrupt processing time, is determined by the time for processing the high-speed sequence control table 105. In order to improve the responsiveness of the system, it is necessary to shorten the interrupt processing time and further shorten the interrupt cycle. Therefore, in the present embodiment, the high-speed sequence control table 105 as described above is used.
[0032]
FIG. 20 is a flowchart showing details of the processing 804 in FIG. 8 for generating the high-speed sequence control table 105 as shown in FIG. Hereinafter, the flowchart will be described with reference to FIG. First, the high-speed sequence intermediate code is loaded (process 2001), and one unprocessed IF statement is extracted (process 2011). Next, from the condition part of the IF statement, such as “IF Sj ==...” 1902 (FIG. 19), the step NO. (= J) is extracted (process 2002), and step NO. If j is not the same value as the previously processed IF statement (Process 2003), the entry address of the control table 1907 for registering new data is stored in the j-th entry table 1906 (Process 2004). Here, it is assumed that the size of the field of the control table 1907 assigned per place is fixed, and the entry address can be uniquely calculated from the number of places already registered. Next, the number of branches in the control table 1907 is counted up (process 2005). The number of branches is 0 at the time of new registration, and it is assumed that a certain finite number can be registered. As described above, the number of branches is the number of transitions on the output side of the previous place that are connected as inputs to the place with the high-speed option. Next, a condition part of the control table 1907 is generated from other conditional expressions 1903 of the IF statement (processing 2006). The condition part of the control table 1907 is in a simplified data format (hereinafter, abbreviated code) so that high-speed processing can be performed using a simple matching process. In order to enable such a simplified coding, a conditional description of the IF statement may be restricted to some extent. For example, there may be restrictions such as limiting each side of the conditional expression to a monomial expression. Next, the step number of the IF statement command “EXEC Si” 1904 or the like is used. i, and the next step NO. (Process 2007). Further, the entry address of the command list 1908 for storing the remaining command sequence 1905 is calculated, and this is stored in the command entry field of the control table 1907 (process 2008). Next, the command sequence is internally coded and stored in the command list 1908 (process 2009). Since the internal code of each command sequence is not of a fixed length, CmdListEndCode is added so that the end of the command sequence can be recognized. Further, if there is the next IF statement, the process returns to the process 2011, and the same process is repeated (process 2010).
[0033]
FIG. 21 shows a table generated from the high-speed sequence block 1502 in FIG. Here, as shown in the entry table 2101, the number of places registered in the control table 2102 is three, and the number of branches of the place S102 in the places is two. This corresponds to two of the three output transitions of S102 in FIG. 5 being connected as inputs to the place with the high-speed option.
[0034]
FIG. 22 is a flowchart showing the processing of the normal sequence control internal code execution means 106 of FIG. The normal sequence control internal code execution means 106 is one of the tasks provided as firmware of the controller, and interprets and executes the normal sequence internal code 104 downloaded into the controller to execute a device connected to the controller. Control.
[0035]
In FIG. 22, first, the normal sequence control internal code executing means 106 scans the internal code for each unit. (= N) is initialized (n = 0) (processing 2201). Next, the value of n is increased by 1, and the next unit NO. (Process 2202). Note that the current step No. indicating the place being executed for each unit. This information can be referred to from the normal sequence control internal code executing means 106. Therefore, the current step NO. (= I) is acquired (process 2203), and the process jumps to the “STTi” internal code (process 2204). At this time, the jump destination address is obtained from the address table of the "STTi" internal code accompanying the normal sequence control internal code 104. After the jump, the internal codes are sequentially fetched and executed until the next "STT" internal code appears (process 2205). Further, if n is not the predetermined maximum value and there is a next unit, the process returns to the process 2202, and the same process is repeated (process 2206). If n reaches the maximum value, that is, the number of registered units, and there is no next unit, the process returns to step 2201 (step 2206). As described above, the scan time can be reduced by selectively scanning only the block of the currently executing step of each unit of the normal sequence control internal code 104.
[0036]
FIGS. 23 and 24 are flowcharts showing the processing of the high-speed sequence control table processing means 107 of FIG. These two figures constitute one flowchart, and in the figures, (1), (2), and (3) show the connection relationship between the two figures. The high-speed sequence control table processing unit 107 is an interrupt task provided as firmware of the controller, and controls devices connected to the controller by processing the high-speed sequence control table 105 downloaded in the controller. Note that the interrupt task is a task that is started by a timer for inputting an interrupt at a fixed cycle or an external input signal, and is normally executed by the task of the sequence control internal code execution unit 106 with priority interrupted during execution. You. In FIGS. 23 and 24, the high-speed sequence control table processing means 107 also performs table processing for each unit. (= N) is initialized (step 2301). Next, the value of n is increased by 1 (process 2302), and the current step NO. (= I) is acquired (process 2303). Further, the entry address of the control table 2102 is obtained from the i-th data of the entry table 2101 (process 2304). Next, the number of branches is obtained from the field of the corresponding address of the control table 2102 (step 2305). To process the table for each branch, the current branch NO. (= M) is initialized (m = 0) (processing 2306). m is incremented by 1 and the next branch NO. (Step 2307). The simplified expression code of the condition part of the m-th branch in the corresponding field of the control table 2102 is evaluated (processing 2308). If the condition is satisfied (processing 2309), the entry address of the command list 2103 is obtained from the control table 2102 (processing 2401). Further, the internal code of the corresponding address in the command list 2103 is sequentially fetched and executed until CmdListEndCode appears (processing 2402). Next, the next step NO. Is acquired (processing 2403), and step NO. In the next step NO. (Step 2404). In addition, the current step No. of each unit is used. Is shared data that can be referred to and rewritten by both the normal sequence control internal code execution means 106 and the high-speed sequence control table processing means 107. As described above, the normal sequence control internal code execution means 106 and the high-speed sequence control table processing means 107 execute step NO. , It is possible to synchronize with each other at the step level. If the condition is not satisfied (step 2309), the branch NO. Is checked to see if it has reached the number of branches, that is, whether there is a next branch. If there is a next branch, the process returns to step 2307 to repeat the same processing. If there is no next branch, the next unit Processing shifts to processing (processing 2310). Finally, if n is not the maximum value and there is a next unit, the flow returns to step 2302 to repeat the same processing. If there is no next unit, one cycle of interrupt processing is completed here (step 2405).
[0037]
In the above embodiment, in the present embodiment, the high-speed sequence control table processing unit 107 has been described as a process executed by an interrupt. It is clear that the sequence control method of the present invention has the same effect in the case of processing. Also, in place of the high-speed sequence control table, a method of generating a high-speed sequence control internal code having the same format as that of the normal sequence control internal code 104 and processing this with a controller having a sufficient processing speed may be used. Can be realized.
[0038]
【The invention's effect】
According to the present invention, when describing a series of sequences, a high-speed sequence control table can be automatically generated simply by designating a step requiring a high-speed response with a mark. The description can be easily made without impairing the visibility as a series of sequences, and as a result, there is an effect that the program development efficiency and the maintainability can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a processing flow of a high-speed sequence control method according to the present invention.
FIG. 2 is a timing chart showing a relationship between a scan processing cycle and a cycle of a state change of an input signal in the programmable controller.
FIG. 3 is a timing chart showing a case where a cycle of a state change of an input signal in FIG. 2 is shorter than a scan time.
FIG. 4 is a timing chart showing a case where interrupt processing is used in combination to capture a change in the state of the input signal of FIG. 3;
FIG. 5 is a diagram showing an example of a sequence control program in Petri net notation.
FIG. 6 is a diagram showing an example of a sequence control program in SFC notation.
FIG. 7 is a diagram showing a code obtained by coding the sequence control program of FIG. 5;
FIG. 8 is a flowchart showing processing of a sequence control program conversion means.
FIG. 9 is a flowchart showing a process of analyzing a sequence control program of FIG. 8;
FIG. 10 is a flowchart showing a net structure analysis process for each place in FIG. 9;
FIG. 11 is a flowchart showing a command sequence analysis process for each place in FIG. 9;
FIG. 12 is a flowchart showing a process of end condition analysis for each place in FIG. 9;
FIG. 13 is a flowchart showing a sequence control intermediate code generation process of FIG. 8;
14 is a flowchart showing a process of generating an intermediate code for each place in FIG.
FIG. 15 is a diagram showing an intermediate code generated from the sequence control program of FIG. 7;
FIG. 16 is a diagram illustrating an example in which a normal sequence control internal code is generated from a normal sequence intermediate code.
FIG. 17 is a flowchart showing a process of generating a normal sequence control internal code in FIG. 8;
FIG. 18 is a diagram showing an internal code generated from the normal sequence block of FIG.
FIG. 19 is a diagram illustrating an example in which a high-speed sequence control table is generated from high-speed sequence intermediate codes.
FIG. 20 is a flowchart showing processing for generating a high-speed sequence control table in FIG. 8;
FIG. 21 is a diagram showing a table generated from the high-speed sequence block in FIG.
FIG. 22 is a flowchart showing processing of a normal sequence control internal code execution means.
FIG. 23 is a flowchart showing processing of a high-speed sequence control table processing means.
FIG. 24 is a continuation of the flowchart in FIG. 23;
[Explanation of symbols]
101 Sequence control program editing means
102 Sequence control program
103 Sequence control program conversion means
104 Normal sequence control internal code
105 High-speed sequence control table
106 Normal sequence control internal code execution means
107 High-speed sequence control table processing means
501 place
502, 503, 504 transition
505 Place with fast option
Step element with high-speed option in 601 SFC
701 Normal sequence block
702 High-speed sequence block
703 #INTERRUPT statement
704 cell block
705 def block
706 "cell" statement
707 "def" statement
708 cell label
709 Transition conditional expression
710 Command string
711 def label
712 End condition expression
1501 Normal sequence block
1502 High-speed sequence block
1503 IF statement of intermediate code
1601 IF statement of intermediate code
1602 Condition part
1603 Command string
1604 Block of internal code
1605, 1606, 1607 Internal code
1801 Internal code block
1901 IF statement of intermediate code
1902, 1903 Condition part
1904, 1905 Command string
1906 Entry table
1907 control table
1908 Command list
2101 Entry table
2102 control table
2103 Command list

Claims (6)

Among the steps of the sequence control program, a mark is added to a step that requires high-speed processing, and the high-speed step with the mark and the normal step without the mark are separated to form a high-speed and normal intermediate code. Generating a high-speed execution program and a normal execution program from each of the intermediate codes, and executing the high-speed execution program while synchronizing the steps being executed between the high-speed execution program and the normal execution program. A high-speed sequence control method characterized by the above-mentioned. The high-speed execution program includes a command list for storing a command sequence of the high-speed step, an end condition of a current step, a number of a next step to be executed, and an entry of a command sequence to be executed next to the command list. 2. The high-speed sequence control table according to claim 1, wherein the high-speed sequence control table includes a control table for storing an address and an entry table for storing an entry address of the control table in each step. Control method. 2. The high-speed sequence control method according to claim 1, wherein the high-speed execution program and the normal execution program are processed by the same processor, and the high-speed execution program is executed by interruption to the processor. A high-speed sequence control device for performing high-speed sequence control using a sequence control program in which a step requiring high-speed processing is marked among steps ,
Intermediate code generating means for generating a high-speed and normal intermediate code by separating the high-speed step to which the mark is added and the normal step to which the mark is not added,
Execution program generation means for generating a high-speed execution program and a normal execution program from each of the intermediate codes;
A processor for executing the high-speed execution program while synchronizing steps during execution between the high-speed execution program and the normal execution program,
A high-speed sequence control device comprising: 5. The processor according to claim 4, wherein the processor executes the normal execution unit together with the high-speed execution program, and further includes an interrupt unit for activating the high-speed execution program by interrupting the processor. High-speed sequence controller. 6. The high-speed sequence control device according to claim 5, further comprising storage means for sharing the number of the step being executed by the high-speed execution program and the normal execution program.

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