JPH10293604A - Fast sequence control method, device therefor, and program production method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily describe a sequence including a process that requires a fast response without deteriorating the viewing easiness of the sequence as a series of sequences and also to attain the fast response. SOLUTION: This method consists of a sequence control program editing means 101 which produces a sequence control program 102 that designates a step requiring a fast response with a mark, a sequence control program conversion means 103 which separates and converts the program 102 into a normal sequence control internal code 104 and a fast sequence control table 105, a normal sequence control internal code execution means 106 which executes the code 104, and a fast sequence control table processing means 107 which processes the table 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed sequence control method and apparatus, and a program creation method.
In particular, a high-speed sequence control method in which a high-speed sequence control table is automatically generated simply by designating a step requiring a high-speed response in a series of sequences with a mark, and high-speed sequence control is performed using the control table. And a device for the same, and a program creating method therefor.

[0002]

2. Description of the Related Art In a conventional sequence control method, a computer dedicated to device control called a programmable controller is used in many cases, and a dedicated control program corresponding to an operation specification of a control target is input to the computer. Thus, the sequence control of the device was performed. The above control program is described by a ladder diagram, an SFC (Seqential Function Chart), or the like. In particular, processing requiring a high-speed response needs to be described as an interrupt program different from a normal program. A well-known example of a sequence control method using this interrupt program is described in PP.15-30 of "Hitachi Programmable Controller HIDIC H Series CPU Module Instruction Manual (Software) NB323C" (Hitachi, 1995). Sequence control method. Hereinafter, an operation example when this interrupt program is used will be described.

FIG. 2 is a timing chart showing a relationship between a cycle of a scan process and a cycle of a state change of an input signal in a programmable controller. A cycle of a state change of an input signal corresponds to one cycle of the scan process, that is, a scan time. This shows a case where the length is longer.
Here, in the program processed in the scan process 202, a process of detecting an event that the input signal 201 changes from OFF to ON, that is, a process of detecting a rising edge, is described.
During the scan process of the cycle, the timing 203 at which this process is executed is indicated by an upward arrow. FIG. 2 shows that the rising edge of the input signal 201 is completely captured.

On the other hand, FIG. 3 shows a case where the cycle of the state change of the input signal is shorter than the scan time.
The program to be scanned is the same as in FIG.
In FIG. 3, since the change of the input signal 301 is fast, the scan process 302 cannot follow the change, and a missing detection 304 of the rising edge of the input signal 301 occurs.

FIG. 4 shows a case in which an interrupt process is used together in order to cope with a high-speed state change in which it is difficult to follow the scan process. The interrupt process 402 is a process that is started by a timer or the like that interrupts at a constant cycle. The interrupt cycle can follow a change in the input signal 401. In the program processed in the interrupt processing 402, processing for detecting the rising of the input signal 401 is described.
3 is indicated by an upward arrow. In FIG. 4, the rising of the input signal 401 is completely captured. Note that one cycle of the interrupt processing 402 is shorter than the interrupt cycle itself. In the program processed in the normal scan process 404, other processes are described, excluding the processes described in the program processed in the interrupt process 402. Here, the scan process 404 itself is intermittent because it is interrupted by the interrupt process 402, and the scan time is longer than in FIGS. 2 and 3. However, considering the total performance of the system, the input signal 401 Responsiveness to is improved.

[0006]

In the above-described prior art, the processing requiring a high-speed response is described as an interrupt program different from the normal sequence. It is necessary to frequently synchronize with the processing of the sequence, and when viewed as a series of sequences, the processing requiring a high-speed response is often substantially mixed in the normal sequence. For this reason, in the conventional method in which the normal sequence and the processing requiring high-speed response are described separately from the beginning, the description of the program itself becomes complicated, and as a result, the visibility as a series of sequences is impaired. This makes it difficult to change the sequence.

Therefore, according to the present invention, when describing a series of sequences, a step requiring a high-speed response is designated by a mark indicating high-speed processing, and a sequence control program in which a normal sequence and a high-speed sequence are mixed at the step level is specified. , A high-speed sequence control table is automatically generated, and using this high-speed sequence control table,
It is an object of the present invention to provide a high-speed sequence control method and device for controlling a high-speed sequence, and a program creation method therefor.

[0008]

In order to achieve the above object, according to the present invention, a mark is added to a step requiring high-speed processing among the steps of a sequence control program, and the mark is added. Generating high-speed and normal intermediate codes by separating high-speed steps and normal steps to which the mark is not added, further generating a high-speed execution program and a normal execution program from each of the intermediate codes,
A high-speed sequence control method characterized in that the high-speed execution program is executed while synchronizing the steps being executed between the high-speed execution program and the normal execution program.

Further, the present invention provides the high-speed execution program, wherein a command list for storing the command sequence of the high-speed step, an end condition of a current step, a number of a next step to be executed, and A high-speed sequence control table comprising a control table for storing an entry address of a command string to be executed next, and an entry table for storing an entry address of the control table in each step. A high-speed sequence control method is disclosed.

The present invention also relates to a method for creating a sequence control program, wherein a step mark requiring high-speed processing is added to each step of the sequence control program. Is disclosed.

Further, the present invention provides a high-speed sequence control device for performing high-speed sequence control using a sequence control program created by the above-described method for creating a sequence control program, wherein the high-speed step Intermediate code generating means for generating a high-speed and normal intermediate code by separating normal steps to which the mark is not added, and generating an execution program for generating a high-speed execution program and a normal execution program from each intermediate code And a processor for executing the high-speed execution program while synchronizing the steps being executed between the high-speed execution program and the normal execution program. .

[0012]

Embodiments of the present invention will be described below in detail. FIG. 1 is a block diagram schematically showing a processing flow in a high-speed sequence control method according to the present invention. First, sequence control program editing means 101
In this way, a series of sequence control programs 102 are created, and the steps requiring high-speed response include:
Add a mark for high-speed processing. The sequence control program 102 thus created is separated and converted into a normal sequence control internal code 104 and a high-speed sequence control table 105 by the sequence control program conversion means 103. In the high-speed sequence control table 105, processing that requires high-speed response specified by a mark, that is, data for controlling a high-speed sequence is stored in a table format suitable for high-speed processing. On the other hand, the normal sequence control internal code 104 stores processing other than the high-speed sequence allocated to the high-speed sequence control table 105, that is, the internal code sequence (executable program) of the normal sequence. Here, the normal sequence control internal code 104 is interpreted and executed by the normal sequence control internal code execution means 106. In parallel with this, the high-speed sequence control table processing means 107
05 is processed. As described above, when the sequence control program 102 is created, the high-speed sequence control table 105 can be automatically generated only by designating the steps that require the high-speed response by the mark. Can be easily described in a natural form without impairing the visibility as a series of sequences. That is, since the sequence can be created and changed more easily than in the past, program development efficiency and maintainability are improved.

FIG. 5 shows an example of the sequence control program 102 described by the sequence control program editing means 101 of FIG. In FIG. 5, a graphic type programming language for expressing a series of sequences in the form of a Petri net is used. A known example of such a language is a cell control described in Japanese Patent Application Laid-Open No. 7-72920. Language. In this cell control language, a place of a Petri net (denoted by a circle in the figure) is defined as an operation per step of a device (hereinafter, referred to as a unit) constituting a cell of a factory automation (FA) system. Then, each place is assigned a step number, which is the reference number of the step. (For example, S10
0). In addition, transition (in the figure,
Is defined as a transition condition to the next step. Further, a so-called safe Petri net, in which a place having a token (not shown in the figure) is set as an executing step, and each place includes at most one token, is considered.

Step NO. Of place 501 in FIG. Is S102, and the operation of the unit in that step is:
It is described as a command string using the sequence control program editing means 101 of FIG. Also, place 50
Transitions 502, 503, 504 on the output side of No. 1
Are the end conditions OK1 and OK in step S102, respectively.
2 and OK3 as transition conditions, and end conditions OK1 and OK
2, OK3 is a sequence control program editing means 10
1 is described as a conditional expression relating to input / output signals and the like. FIG. 5 shows only the sequence notation, and does not show these command strings and conditional expressions (examples of command strings and conditional expressions will be described later).

In the present invention, the use of the cell control language as described above is slightly extended to mark places requiring high-speed processing. For example, the place 505 has a square mark at the upper right of a normal place symbol (represented by a circle in the figure) such as the place 501, and a transition on the input side of the place (in the case of the place 505, This means that it is necessary to respond at high speed to the state transition of the transition 503). Let's call this mark the fast option for the place. As described above, when a part of the sequence requires a high-speed response, simply adding the high-speed option to a place will cause the step to be processed as a high-speed sequence. For example, in the place 505, the transition condition of the input transition 503, that is, step S
Monitoring whether the termination condition OK2 of 102 is satisfied,
This is performed in the interrupt processing 402 of FIG.
If 2 is satisfied, a command sequence that defines the operation in step S105 is executed, and a high-speed response to a state change is possible. In addition, a normal place step without the high-speed option is executed in a normal scan process.

Such a notation method in which a mark is added to a step requiring a high-speed response in a series of sequences to distinguish the steps is not prepared even in a conventional technique such as SFC. Therefore, an example of a similar extension to the SFC notation is shown in FIG.
Shown in In FIG. 6, the upper right corner of the SFC step element (denoted by □ in the figure) is painted in a triangular shape to give the same meaning as the high-speed option in FIG. For example, the step 601 (S105) has the high-speed option, and the monitoring of the condition described in the transition (t1022) on the input side is performed in the interrupt processing. In addition,
SFC is a notation that originates from Petri nets, and the following description using Petri nets as an example is also valid when SFC is used.

When describing a Petri net as shown in FIG. 5, the sequence control program editing means 101
It is assumed that the operation in each step is described by a command sequence and the transition condition of each transition is described by a conditional expression.Even if these are described by a conventional ladder diagram, function block diagram, etc., the high-speed sequence described below is used. The control method is likewise feasible.

FIG. 7 shows a coded version of the sequence control program 102 of FIG. 5, which has a structure corresponding one-to-one with the Petri net notation of FIG. The sequence control program editing means 101 shown in FIG. 1 edits the sequence control program 102 in the Petri net format shown in FIG. 5 and finally saves it in a code format as shown in FIG. Here, the conversion from the Petri net format to the code format is automatically performed by the processing of the sequence control program editing means 101. Further, it is assumed that the sequence control program conversion means 103 processes the sequence control program 102 in a code format as shown in FIG. 7 as an input.

The sequence control program shown in FIG. 7 is roughly composed of two blocks. One is a normal sequence block 701 and the other is an #INTERRUPT statement 7
It is a high-speed sequence block 702 that starts with 03. The high-speed sequence block 702 is a collection of descriptions of places with the high-speed option among the places of the Petri net in FIG. 5, and the normal sequence block 701 is a collection of descriptions of other places. . Further, a normal sequence block 701
The high-speed sequence block 702 includes a cell block 704 starting with a “cell” statement 706 and a “def” statement 7
It consists of a def block 705 starting with 07. ce
The 11 block 704 includes the connection relationship between places and transitions, that is, the structure of Petri nets, and the processing in each place. The cell label 708 includes
Step No. of each place. (S101) and the unit NO. (UNIT1) is described. The transition condition expression 709 includes the step number of the place connected as an input to the transition on the input side of the place. (S100) and the end condition name (OK1) are described. When there are a plurality of transitions on the input side as in S108 of FIG. 5, step NO. Of the place connected as an input to the transition is performed. And the end condition name are described after the symbol "|" meaning OR. In the command column 710, a command defining a process per step is described. def block 705
Contains a conditional expression that defines the end condition of the step of each place. A def label 711 has a step No. of each place. (S101) is described. In the end condition expression 712, the end condition name of each step (OK1)
And a conditional expression that defines it. In the case of a step having several termination conditions as in S102 of FIG. 5, a plurality of termination condition names and conditional expressions are described. Note that the description of the high-speed sequence block 702 is also
This is the same as the normal sequence block 701 described above.

The sequence control program shown in FIG. 7 (that is, FIG. 5) is modularized for each unit that is the subject of the sequence. For example, FIG.
3 shows a module of NIT1. As described above, each module of the sequence control program 102 has the unit No.
Are distinguished by

FIG. 8 is a flowchart showing the processing of the sequence control program conversion means 103 of FIG. The sequence control program conversion means 103 first analyzes the input sequence control program 102 (process 801), and generates a sequence control intermediate code based on the information obtained by this analysis (process 802). Next, the normal sequence control internal code 104 and the high-speed sequence control table 105 are generated from the sequence control intermediate code (steps 803 and 804).

FIG. 9 is a detailed flowchart of the sequence control program analysis processing 801. Assuming that the sequence control program of FIG. 7 has been input, first, a data area for storing the Petri net structure, the command sequence, and the end condition of the normal sequence block 701 is secured (process 901). Next, the normal sequence block 7
01 cell block 704, def block 705
Are analyzed in order. In the analysis of the cell block 704,
One unprocessed place is taken out (process 909), and the Petri net structure of the place is analyzed (process 902).
Further, the command sequence 710 and the like are analyzed (process 903).
Such an analysis is repeated until there is no description of the next place (process 904). In the analysis of the next def block 705, one unprocessed place is extracted (step 91).
0), the end condition expression 712 of the place is analyzed (step 905), and this is repeated until there is no description of the next place (step 906). With the above processing, the analysis of the normal sequence block 701 is completed.
If the PT statement 703 is described (processing 907), it is known that there is a high-speed sequence block 702. Therefore, a data area for the analysis is secured (processing 908), and thereafter, the same processing as the normal sequence block 701 is performed. I do.

FIG. 10 is a detailed flowchart of the net structure analysis processing 902 for each place in FIG. In this net structure analysis, the cell label 708 and the like and the transition condition expression 709 and the like are analyzed. cell label 70
In the analysis of the place No. 8 or the like, the step NO. Is extracted (process 1001), and the unit NO. (Process 10
02). In the analysis of the transition condition expression 709, one unprocessed transition condition expression is extracted (process 1006), and the transition connected as an input to the transition on the input side of the current place, that is, the immediately preceding place (hereinafter, the previous place) Step NO.) Is extracted (step 1003), and the end condition name of the previous place is extracted (step 1004). If there is another transition condition expression 709 in the current place, the processes 1003 and 1004 are repeated (process 1005). Note that the presence of a plurality of transition condition expressions 709 in the current place corresponds to the presence of a plurality of transitions on the input side of the current place.

FIG. 11 is a detailed flowchart of the command line analysis process 903 for each place in FIG. In this command string analysis, commands are extracted one by one from the command string 710 of the current place (step 110).
1) This is repeated until there is no next command (process 1102).

FIG. 12 is a detailed flowchart of the processing 905 of end condition analysis for each place in FIG. In this end condition analysis, the step number of the current place is determined based on the def label 711 and the like. Is extracted (processing 120
1) Take out one unprocessed OK condition (process 120
6) Further, an end condition expression 712 and the like are extracted (Process 1).
202). This process is repeated until the OK condition for the place disappears (process 1203). Note that the end condition expression 7
12 and the like are not only conditional expressions defining OKn termination conditions indicating normal termination (hereinafter referred to as OK conditional expressions), but also conditional expressions defining NGn termination conditions indicative of abnormal termination (hereinafter referred to as NG conditional expressions). In this case, processing 1207, 120
4, 1205, it is similarly analyzed. Each data extracted in the above sequence control program analysis processing 801 is stored in step NO. And stored as structured data that can be searched by the end condition name.

FIG. 13 is a flowchart showing details of the sequence control intermediate code generation processing 802 in FIG.
In the sequence control intermediate code generation, one unprocessed unit is first taken out (process 1311), and the data of the net structure, the command sequence, and the end condition of the normal sequence and the high-speed sequence are loaded (processes 1301, 1302). Next, step NO. One of the data of the place with the smaller value (processing 1312), and if this is a place with the high-speed option (processing 1303),
Select the high-speed sequence intermediate code buffer (Process 13
05), if there is no high-speed option (processing 130
3) Select a normal sequence intermediate code buffer (process 1304). Here, it is assumed that two intermediate code buffers are prepared for each unit: a normal sequence and a high-speed sequence. Next, an intermediate code for each place is generated and output to a buffer (processing 130
6). Further, step NO. If there is a place having a larger value, the process returns to step 1312 and the same process is repeated (step 1307). When there is no next place, the unit number is higher than the current unit. If there is a module of a larger unit, the process returns to step 1311 and the same processing is repeated (step 1308). As described above, after generating the intermediate codes for the modules of all the units, first, the intermediate code buffers of the normal sequence are combined and stored (process 1309). Further, the intermediate code buffers of the high-speed sequence are combined and saved (process 13).
10).

FIG. 14 is a flowchart showing details of the intermediate code generation processing 1306 for each place in FIG. In this process, first, one previous place is taken out (process 1406), and the step NO. (= I) (process 140)
1). Next, the step NO. And an end condition, and a conditional expression of the end condition of the previous place is obtained from the end condition data (Process 1).
402). Next, the first half of the IF statement, which is the basic form of the intermediate code, is generated from these data and output to the buffer (process 1403). Where "IF Sj == Exec
"uting & conditional expression->" means "if the conditional expression of the end condition is satisfied after execution of step j". Also, the command "TERM Sj" is "end step Sj", "EXEC
"Si" means "execute step Si". next,
The command string of the current place Si is output to the buffer continuously (process 1404). This completes the processing for one previous place, and if there is another previous place, that is, if there is another transition on the input side of step Si, the process returns to step 1406 and the same processing is repeated (step 1405). ).

FIG. 15 shows an intermediate code of the sequence control program 102 shown in FIG. Similarly to FIG. 7, the intermediate code is also composed of two blocks, a normal sequence block 1501 and a high-speed sequence block 1502. Here, the intermediate code has an IF sentence as shown in the IF sentence 1503 as a basic form, and a collection of these becomes a block.

FIG. 16 shows the sequence I code of the normal sequence intermediate code.
An example in which the normal sequence control internal code 104 is generated from the F statement is shown. The internal code is actually in a binary format, but is shown in a mnemonic format in FIG. IF statement 1
An internal code 1606 is generated from the condition part 1602 of 601, and an internal code 1607 is generated from the command sequence 1603. Thus, the internal code of IF statement 1601 is "STTi"
A block 1604 starts from the internal code 1605. The "STTi" internal code 1605 is used when executing the internal code.

FIG. 17 is a flowchart showing details of the processing 803 in FIG. 8 for generating the normal sequence control internal code 104 as shown in FIG. First,
The intermediate code of the normal sequence is loaded (processing 170
1) Then, unprocessed IF statements of the intermediate code are extracted one by one (processing 1709), and the step NO. (= I) is extracted (processing 1702).
In this step NO. If i is not the same as the condition part of the previous IF sentence (processing 1703), an "STTi" internal code is generated (processing 1704). Next, an internal code is generated from the conditional expression (processing 1705), and an internal code is generated from the command sequence (processing 1706). Thereafter, if there is the next IF statement, the process returns to step 1709, and the same processing is repeated (step 1707). After processing all IF statements, an address table indicating where each "STT" internal code is in the normal sequence control internal code 104 is generated (processing 1708). FIG. 18 shows a case where the normal sequence block 1501 of FIG. 15 is internally coded. A block 1801 is obtained by internally coding the IF statement 1503.

FIG. 19 is a diagram showing a high-speed sequence intermediate code I
An example in which the high-speed sequence control table 105 is generated from an F sentence is shown. As shown in FIG. 19, the high-speed sequence control table 105 includes three pieces of data: an entry table 1906, a control table 1907, and a command list 1908. The entry table 1906 is a table for storing an entry address in the control table 1907 when registering the content of the IF statement in the control table 1907. The entry table 1906 contains the step NO. Is a one-dimensional array subscripted with the current step NO. , The entry address of the control table 1907 can be uniquely specified. Step NO. Irrelevant to the high-speed sequence intermediate code , The entry table 19
In 06, a value meaning unregistered (FFFF in hexadecimal notation)
Is stored. In the control table 1907, the condition part of the IF statement and the step NO. A field for updating is stored, a field for storing the number of transitions on the output side (hereinafter, the number of branches), a field for storing a conditional expression, and a next step NO. And a field for storing an entry address to the command list 1908. The command list 1908 is an area in which a command string of an IF statement is internally coded and stored. The end code (CmdLis
tEndCode). By using the high-speed sequence control table 105 configured as described above, the current step NO. Can be called efficiently, and the processing time can be shortened. As described above, the high-speed sequence control table 105 is executed by interrupt processing.
That is, the interrupt processing time is determined by the time for processing the high-speed sequence control table 105. To improve the responsiveness of the system, shorten the interrupt processing time,
Further, it is necessary to shorten the interrupt cycle. Therefore, in the present embodiment, the high-speed sequence control table 105 as described above is used.

FIG. 20 is a flowchart showing details of the processing 804 of FIG. 8 for generating the high-speed sequence control table 105 as shown in FIG. Hereinafter, the flowchart will be described with reference to FIG. First, the high-speed sequence intermediate code is loaded (processing 200
1), fetch one unprocessed IF statement (Process 201)
1). Next, "IF Sj == ..." 1902 in the condition part of the IF statement
(FIG. 19), the step NO. (= J)
Is extracted (process 2002), and step NO. j is not the same value as the previously processed IF statement (processing 200
3) The entry address of the control table 1907 for newly registering data is stored at the j-th position in the entry table 1906 (process 2004). Here, it is assumed that the size of the field of the control table 1907 allocated per place is fixed, and the entry address can be uniquely calculated from the number of places already registered. Next, the number of branches in the control table 1907 is counted up (process 2005). The number of branches is 0 at the time of new registration, and it is assumed that a certain finite number can be registered. As described above, the number of branches is the number of transitions on the output side of the previous place that are connected as inputs to the place with the high-speed option. Next, a condition part of the control table 1907 is generated from other conditional expressions 1903 of the IF statement (processing 200).
6). The condition part of the control table 1907 has a simplified data format (hereinafter simply referred to as an abbreviated code) so that high-speed processing can be performed using a simple matching process. In order to enable such simplified coding, a conditional description of the IF statement may be restricted to some extent. For example, there may be restrictions such as limiting each side of the conditional expression to a monomial expression. Next, I
Step NO. Such as the command “EXEC Si” 1904 of the F statement.
i, and the next step NO. (Process 2007). Further, the remaining command sequence 190
5 is calculated, and the calculated entry address is stored in the command entry field of the control table 1907 (process 200).
8). Next, this command string is internally coded and stored in the command list 1908 (process 2009). In addition,
Since the internal code of each command sequence is not fixed length, CmdListEndCode is added so that the end of the command sequence can be recognized. Further, if there is a next IF statement, the process returns to the process 2011, and the same process is repeated (process 2010).

FIG. 21 shows a table generated from the high-speed sequence block 1502 in FIG. Here, as shown in the entry table 2101, the control table 210
The number of places registered in 2 is three, and the number of branches of the place S102 therein is two. This corresponds to S1 in FIG.
02 out of the three output transitions, two of which are connected as inputs to places with the high-speed option.

FIG. 22 is a flowchart showing the processing of the normal sequence control internal code execution means 106 of FIG. This normal sequence control internal code execution means 106
Is one of the tasks provided as firmware of the controller, and controls devices connected to the controller by interpreting and executing the normal sequence internal code 104 downloaded into the controller.

In FIG. 22, the normal sequence control internal code execution means 106 first scans the internal code for each unit. (=
n) is initialized (n = 0) (processing 2201). next,
n is increased by 1 and the next unit No. (Process 2
202). Note that the current step No. indicating the place being executed for each unit. This information can be referred to from the normal sequence control internal code execution means 106. Therefore, the current step NO. (= I) is acquired (process 2203), and the process jumps to the "STTi" internal code (process 2204). At this time, the jump destination address is obtained from the address table of the "STTi" internal code attached to the normal sequence control internal code 104.
After the jump, the internal codes are sequentially fetched and executed until the next "STT" internal code appears (process 2205).
Further, if n is not the predetermined maximum value and there is a next unit, the process returns to the process 2202, and the same process is repeated (process 2206). If n reaches the maximum value, that is, the number of registered units, and there is no next unit, the process returns to step 2201 (step 2206). As described above, the scan time can be reduced by selectively scanning only the block of the currently executing step of each unit of the normal sequence control internal code 104.

FIGS. 23 and 24 are flowcharts showing the processing of the high-speed sequence control table processing means 107 of FIG. These two figures constitute one flowchart, and the figures show the connection relationship between the two figures. The high-speed sequence control table processing unit 107 is an interrupt task provided as firmware of the controller, and controls devices connected to the controller by processing the high-speed sequence control table 105 downloaded into the controller. Note that the interrupt task is a task that is started by a timer for inputting an interrupt at a constant cycle or an external input signal, and is normally executed by the task of the sequence control internal code execution unit 106 with priority interrupted during execution. You. In FIGS. 23 and 24, the high-speed sequence control table processing means 107 also performs table processing for each unit. (= N) is initialized (step 2301). Next, the value of n is increased by 1 (process 2302), and the current step NO. (= I) is acquired (Step 230)
3). Further, the entry address of the control table 2102 is obtained from the i-th data of the entry table 2101 (processing 2304). Next, the control table 2102
Then, the number of branches is obtained from the field of the corresponding address (step 2305). To process the table for each branch,
Current branch NO. (= M) is initialized (m = 0) (processing 2306). m is increased by 1 and the next branch NO. (Step 2307). The simplified code of the condition part of the m-th branch in the corresponding field of the control table 2102 is evaluated (step 2308), and if the condition is satisfied (step 230)
9), the command list 210 from the control table 2102
3 is obtained (process 2401). Further, the internal code of the corresponding address of the command list 2103 is sequentially fetched until CmdListEndCode appears,
Execute (process 2402). Next, the control table 210
2 to the next step NO. (Process 2403), and U
Step NO. In the next step NO. (Step 2404). In addition, the current step No. of each unit is used. Is a normal sequence control internal code execution means 1
06 and the high-speed sequence control table processing unit 107 are shared data that can be referenced and rewritten. Thus, the normal sequence control internal code execution means 10
6 and the high-speed sequence control table processing means 107
The currently executed step No. By sharing
Both can be synchronized at the step level with each other. If the condition is not satisfied (step 230
9), branch NO. Has been reached, ie, whether there is a next branch. If there is a next branch, the process returns to step 2307 to repeat the same processing.
If there is no next branch, the process moves to the next unit (process 2310). Finally, if n is not the maximum value and there is a next unit, the flow returns to step 2302 to repeat the same processing. If there is no next unit, one cycle of interrupt processing is completed here (step 2405).

In the above embodiment, the high-speed sequence control table processing means 107 has been described as a process executed by an interrupt in this embodiment. It is apparent that the sequence control method of the present invention has the same effect even when the processing is performed by the method described above. Also, in place of the high-speed sequence control table, a method of generating a high-speed sequence control internal code having the same format as that of the normal sequence control internal code 104 and processing the same by a controller having a sufficient processing speed may be used. Can be realized.

[0038]

According to the present invention, when describing a series of sequences, a high-speed sequence control table can be automatically generated only by designating a step requiring a high-speed response with a mark. A mixed sequence can be easily described without deteriorating the visibility as a series of sequences, and as a result, there is an effect that program development efficiency and maintainability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a processing flow of a high-speed sequence control method according to the present invention.

FIG. 2 is a timing chart showing a relationship between a scan processing cycle and a cycle of a state change of an input signal in the programmable controller.

FIG. 3 is a timing chart showing a case where the cycle of the state change of the input signal in FIG. 2 is shorter than the scan time.

FIG. 4 is a timing chart showing a case where an interrupt process is used in combination to capture a change in the state of the input signal of FIG. 3;

FIG. 5 is a diagram showing an example of a sequence control program in Petri net notation.

FIG. 6 is a diagram showing an example of a sequence control program in SFC notation.

FIG. 7 is a diagram showing a code obtained by coding the sequence control program of FIG. 5;

FIG. 8 is a flowchart showing processing of a sequence control program conversion unit.

FIG. 9 is a flowchart showing a sequence control program analysis process of FIG. 8;

FIG. 10 is a flowchart showing a net structure analysis process for each place in FIG. 9;

11 is a flowchart showing a command sequence analysis process for each place in FIG. 9;

12 is a flowchart showing a process of analyzing an end condition for each place in FIG. 9;

FIG. 13 is a flowchart showing a sequence control intermediate code generation process of FIG. 8;

FIG. 14 is a flowchart showing a process of generating an intermediate code for each place in FIG. 13;

FIG. 15 is a diagram showing an intermediate code generated from the sequence control program of FIG. 7;

FIG. 16 is a diagram illustrating an example in which a normal sequence control internal code is generated from a normal sequence intermediate code.

FIG. 17 is a flowchart showing a process of generating a normal sequence control internal code in FIG. 8;

FIG. 18 is a diagram showing an internal code generated from the normal sequence block of FIG.

FIG. 19 is a diagram illustrating an example in which a high-speed sequence control table is generated from a high-speed sequence intermediate code.

FIG. 20 is a flowchart showing processing for generating a high-speed sequence control table in FIG. 8;

FIG. 21 is a diagram showing a table generated from the high-speed sequence block in FIG.

FIG. 22 is a flowchart showing processing of a normal sequence control internal code execution means.

FIG. 23 is a flowchart showing the processing of the high-speed sequence control table processing means.

FIG. 24 is a continuation of the flowchart in FIG. 23;

[Explanation of symbols]

101 Sequence control program editing means 102 Sequence control program 103 Sequence control program conversion means 104 Normal sequence control internal code 105 High-speed sequence control table 106 Normal sequence control internal code execution means 107 High-speed sequence control table processing means 501 Place 502, 503, 504 Transition 505 Place with high-speed option 601 Step element with high-speed option in SFC 701 Normal sequence block 702 High-speed sequence block 703 #INTERRUPT statement 704 cell block 705 def block 706 "cell" statement 707 "def" statement 708 cell label 709 Transition condition expression 710 Command sequence 711 def label 712 End condition expression 1501 Normal sequence Lock 1502 High-speed sequence block 1503 IF statement of intermediate code 1601 IF statement of intermediate code 1602 Condition part 1603 Command string 1604 Block of internal code 1605, 1606, 1607 Internal code 1801 Block of internal code 1901 IF statement of intermediate code 1902, 1903 Condition Part 1904, 1905 Command string 1906 Entry table 1907 Control table 1908 Command list 2101 Entry table 2102 Control table 2103 Command list

Claims (8)

[Claims] A mark is added to a step requiring high-speed processing among steps of a sequence control program, and a high-speed step to which the mark is added and a normal step to which the mark is not added are separated. And generating a normal intermediate code, further generating a high-speed execution program and a normal execution program from each of the intermediate codes, and synchronizing the steps during execution between the high-speed execution program and the normal execution program to execute the high-speed execution program. A high-speed sequence control method characterized by being executed. 2. The high-speed execution program includes a command list for storing a command sequence of the high-speed step, an end condition of a current step, a step number to be executed next, and a command list to be executed next to the command list. 2. A high-speed sequence control table comprising a control table for storing an entry address of a command string to be stored and an entry table for storing an entry address of the control table in each step. 2. The high-speed sequence control method according to 1. 3. The high-speed sequence control according to claim 1, wherein the high-speed execution program and the normal execution program are processed by the same processor, and the high-speed execution program is executed by interruption to the processor. Method. 4. A method for creating a sequence control program, wherein a step mark requiring high-speed processing is added to each step of the sequence control program. 5. The high-speed sequence according to claim 4, wherein the sequence control program is described by a Petri net or SFC, and the mark is a symbol added to a Petri net place or an SFC step element. How to make. 6. A high-speed sequence control apparatus for performing high-speed sequence control using a sequence control program created by the method for creating a sequence control program according to claim 4, wherein the high-speed step to which the mark is added is provided. Intermediate code generating means for generating a high-speed and normal intermediate code by separating a normal step to which the mark is not added, and generating an execution program for generating a high-speed execution program and a normal execution program from each intermediate code And a processor for executing the high-speed execution program while synchronizing the steps being executed between the high-speed execution program and the normal execution program. 7. The processor according to claim 1, wherein the processor executes the normal execution unit together with the high-speed execution program, and includes an interrupt unit for activating the high-speed execution program by interrupting the processor. Item 7. A high-speed sequence control device according to item 6. 8. The high-speed sequence control device according to claim 6, further comprising storage means for sharing the number of the step being executed by the high-speed execution program and the normal execution program.