JP3551760B2 - Digital signal generator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital signal generator used in an LSI test apparatus and the like, and more particularly, to a digital signal generator capable of improving timing accuracy, reducing leakage current, and improving output impedance.
[0002]
[Prior art]
2. Description of the Related Art A conventional digital signal generator applies various digital signals of "high level state", "low level state", and "high impedance state" to pins of an LSI under test based on a voltage setting signal of an output voltage. . That is, this is realized by applying a high-level voltage signal or a low-level voltage signal to the buffer circuit capable of high impedance output as the above-described voltage setting signal.
[0003]
FIG. 7 is a circuit diagram showing an example of a buffer circuit used in the digital signal generator. In FIG. 7, reference numerals 1, 2, 16 and 17 denote constant current sources capable of turning on / off the output current, 3 and 18 denote Zener diodes, 4, 5, 6, 7, 8, 9, 10, 11, 12 , 13, 14 and 15 are transistors, 19 is a resistor, 100 is a voltage setting signal for applying a high-level voltage signal or a low-level voltage signal, and 101 is an output voltage.
[0004]
The voltage setting signal 100 is connected to the bases of the transistors 6 and 7, the emitter of the transistor 6 is connected to the emitter of the transistor 5, and the collector of the transistor 5 is connected to the base of the transistor 5 and the emitter of the transistor 4, respectively. The collector of the transistor 4 is connected to the bases of the transistors 4 and 10, the output terminals of the constant current sources 1 and 17, and the anode of the Zener diode 3, respectively.
[0005]
On the other hand, the emitter of the transistor 7 is connected to the collector and the base of the transistor 8, and the emitter of the transistor 8 is connected to the collector and the base of the transistor 9. The emitter of the transistor 9 is connected to the base of the transistor 15, the output terminals of the constant current sources 2 and 16, and the cathode of the Zener diode 18, respectively.
[0006]
The emitter of the transistor 10 is connected to the collector and the base of the transistor 11, and the emitter of the transistor 11 is connected to the collector and the base of the transistor 12. The emitter of transistor 12 is connected to the collector and base of transistor 13 and one end of resistor 19, the emitter of transistor 13 is connected to the collector and base of transistor 14, and the emitter of transistor 14 is connected to the emitter of transistor 15. Further, the other end of the resistor 19 outputs an output voltage 101 as an output terminal.
[0007]
Further, the other ends of the constant current sources 1 and 2, the cathode of the Zener diode 3, and the collectors of the transistors 7 and 10 are connected to a positive voltage source, respectively, and the other ends of the constant current sources 16 and 17, the anode of the Zener diode 18, the transistor The collectors of 6 and 15 are respectively connected to a negative voltage source.
[0008]
Here, the operation of the buffer circuit shown in FIG. 7 will be described with reference to FIG. FIG. 8 is a timing chart showing a state transition from the “high impedance state” to the “high level state” or the “low level state”.
[0009]
In the "high impedance state", the constant current sources 1 and 16 turn off the output current by an internal switch circuit and the like, and the constant current sources 2 and 17 output the output current by an internal switch circuit and the like. When the outputs of the constant current sources 1 and 16 are turned "OFF", the transistors 4, 5, 6, 7, 8, and 9 are also turned "OFF".
[0010]
On the other hand, Zener voltages appear across Zener diodes 3 and 18 due to the output currents of constant current sources 2 and 17. Therefore, a voltage value obtained by subtracting the Zener voltage of the Zener diode 3 from the voltage of the positive voltage source appears at “P001” in FIG. 7, and the voltage of the Zener diode 18 is changed to “P002” in FIG. A voltage value obtained by adding the zener voltage appears.
[0011]
Further, as shown in FIG. 8, the output voltage is between the voltage “P002” in FIG. 7 and the voltage “P001” in FIG. 7, so that the transistors 10 and 15 are turned “OFF”, and the transistors 11, 12, and 13 are turned off. And 14 also become "OFF", so that the other end of the resistor 19, which is the output terminal, becomes high impedance.
[0012]
Therefore, the voltages of the positive voltage source and the negative voltage source are "VCC" and VEE, the Zener voltages of the Zener diodes 3 and 18 are "Vz3" and "Vz18", and the output voltage in the "high impedance state" is "Vo". For example, a voltage value as shown in FIG.
[0013]
From this state, when the constant current sources 2 and 17 are turned "OFF" and the constant current sources 1 and 16 output an output current, the transistors 4 to 9 are turned "ON" based on the voltage setting signal 100, and the output voltage 101 is set to "OFF". The state transits to a “high level state” or a “low level state”.
[0014]
At this time, points “P001” and “P002” in FIG. 7 change from the voltage in the “high impedance state” to the voltage determined based on the voltage setting signal 100. For example, when the voltage selection signal 100 is in the “high level state (Vh)”, the voltage of “P001” in FIG. 7 changes from “VCC-Vz3” to “Vh” as shown in “a” in FIG. Change.
[0015]
Then, the voltage of “P001” in FIG. 7 increases, and the transistor 10 turns “ON”. In other words, when the voltage of “P001” in FIG. 7 becomes larger than a certain value with reference to the voltage in the “high impedance state” of the output signal 101, the transistor 10 is turned “ON”. As a result, the transistors 11 and 12 are turned "ON", and the output signal 101 becomes equal to the voltage "P001" in FIG. (Strictly speaking, the voltage becomes lower by the voltage between the base and the emitter of the transistors 10 to 12.)
[0016]
Finally, when the voltage of "P001" in FIG. 7 becomes equal to the voltage setting signal 100 (strictly, the voltage becomes higher by the voltage between the base and the emitter of the transistors 4 to 6), the voltage of the output signal 101 becomes "high level". The state (Vh) "is equal to the voltage setting signal 100. The same operation is performed in the case of the “low level state”.
[0017]
As a result, based on the voltage setting signal 100, the output signal 101 can be set to “high level state”, “low level state” and “high impedance state”.
[0018]
However, in the conventional example shown in FIG. 7, the voltages at points "P001" and "P002" in FIG. 7 in the "high impedance state" are individually determined from the circuit constants of the buffer circuit, and external circuit constants such as the LSI under test. Is constant irrespective of the voltage of the output signal 101 determined by
[0019]
For example, when the voltage of the output signal 101 rises from “b” in FIG. 8 to “c” in FIG. 8 due to an external circuit constant, the “high-level state” occurs with the rise in the voltage of the reference output signal 101. Alternatively, the threshold voltage for switching to the “low level state” also changes from “d” in FIG. 8 to “e” in FIG. 8 or from “f” in FIG. 8 to “g” in FIG. For this reason, there is a problem that a delay time as shown by "h" in FIG. 8 is generated depending on whether the state transits to the "high level state" or the "low level state".
[0020]
That is, the switching time accuracy deteriorates depending on whether the state transits to the “high level state” or the “low level state”. Such switching time accuracy is important, for example, in a test of a RISC processor or the like having an I / O pin, and a deterioration in switching time accuracy results in a deterioration in test accuracy.
[0021]
FIG. 9 is a circuit diagram showing an example of a conventional buffer circuit which solves such a problem. 9, 20, 23, 24, 25, 30, 33, 34 and 35 are transistors, 21, 22, 31 and 32 are resistors, 26 and 29 are constant current sources, 27 and 28 are switch circuits, and 36 is a control circuit. , 100a are voltage setting signals, and 101a is an output signal.
[0022]
The voltage setting signal 100a is connected to one ends of the resistors 21 and 22 and the bases of the transistors 24 and 25, respectively, and the other ends of the resistors 21 and 22 are connected to the emitters of the transistors 20 and 23, respectively. The base of the transistor 20 is connected to the emitters of the transistors 24 and 35, the base of the transistor 33, and one output terminal of the switch circuits 27 and 28, respectively. The base of the transistor 23 is the emitter of the transistors 25 and 34, the base of the transistor 30, and the switch. It is connected to the other output terminals of the circuits 27 and 28, respectively.
[0023]
The emitter of the transistor 30 is connected to one end of the resistor 31, and the other end of the resistor 31 outputs an output signal 101 a as an output terminal and is connected to the bases of the transistors 34 and 35 and one end of the resistor 32. The other end of the resistor 32 is connected to the emitter of the transistor 33. The input terminals of the switch circuits 27 and 28 are connected to one ends of the constant current sources 26 and 29, and the control signal from the control circuit 36 is connected to the control terminals of the switch circuits 27 and 28, respectively.
[0024]
Further, the collectors of the transistors 20, 24, 30 and 34 and the other end of the constant current source 26 are connected to a positive voltage source, respectively, and the collectors of the transistors 23, 25, 33 and 35 and the other end of the constant current source 29 are connected to a negative voltage source. Connected to the respective sources.
[0025]
Here, the operation of the buffer circuit shown in FIG. 9 will be described with reference to FIG. FIG. 10 is a timing chart showing a state transition from the “high impedance state” to the “high level state” or the “low level state”. However, only the voltages at the points indicated by “P003” and “P004” in FIG. 9 in the “high impedance state” which is a problem in FIG. 7 will be described.
[0026]
In the "high impedance state", an output current is output from the current sources 26 and 29 to the "low" and "d" sides in FIG. 9 of the switch circuits 27 and 28, and the transistors 30 and 33 are turned "off". Become. Therefore, the transistors 34 and 35 are turned "ON", and the output signal 101a of the output terminal is fed back to "P003" and "P004" in FIG.
[0027]
That is, if the voltage of the output signal 101a is "Voa", the voltage "P003" in FIG. 9 becomes "Voa-Vbe34", which is lower by the base-emitter voltage "Vbe34" of the transistor 34. The voltage of the middle “P004” becomes “Voa + Vbe35” which is higher by the base-emitter voltage “Vbe35” of the transistor 35.
[0028]
As shown in FIG. 10, the voltages of "P003" and "P004" in FIG. 9 in the "high impedance state" are always the base-emitter voltage "Vbe34" with respect to the voltage "Voa" of the output signal 101a in the "high impedance state". Or "Vbe35".
[0029]
Therefore, the voltages of “P003” and “P004” in FIG. 9 in the “high impedance state” follow the change of the voltage “Voa” of the output signal 101a, so that the “high level state” or the “low level state” The threshold voltage for switching to "" does not change, and the above-described delay time can be prevented from occurring.
[0030]
However, in the conventional example shown in FIG. 9, since the bases of the feedback transistors 34 and 35 are connected to the output terminal in the "high impedance state", there arises a problem that the leak current increases. Further, adding a feedback circuit increases the circuit scale.
[0031]
Such an increase in the leak current in the “high impedance state” deteriorates the accuracy of the Iddq test, the DC parameter test, and the like.
[0032]
FIG. 11 is a circuit diagram showing an example of a conventional digital signal generator which has solved such a problem. In FIG. 11, 37 is a high level setting voltage source, 38 and 42 are diode circuits in which “n” diodes are connected in parallel, and 39 is an output current value of “0”, “m · I” and “(m + n) · I Current sources that can be switched to "", 40 and 41 are diode circuits in which "m" diodes are connected in parallel, 43 is an output current value of "0", "-m.I" and "-(m + n) .I" , A low-level setting voltage source 44, an output signal 101b, and control signals 102 and 103. Here, “m” and “n” are integers, and “I” is an arbitrary current value.
[0033]
The control signals 102 and 103 are connected to a high-level setting voltage source 37 and a low-level setting voltage source 44, respectively. The output of the high-level setting voltage source 37 is connected to the cathode of a diode circuit 38, and the anode of the diode circuit 38 is connected to a current source. 39 and the anode of the diode circuit 40, respectively.
[0034]
The cathode of the diode circuit 40 outputs the output signal 101b as an output terminal and is connected to the anode of the diode circuit 41. The cathode of the diode circuit 41 is connected to the cathode of the diode circuit 42 and one end of the current source 43, and the anode of the diode circuit 42 is connected to the output terminal of the low-level setting voltage source 44. The other end of the current source 39 is connected to a positive voltage source, and the other end of the current source 43 is connected to a negative voltage source.
[0035]
Here, the operation of the conventional example shown in FIG. 11 will be described with reference to FIG. FIG. 12 is a table showing the output current value of the current source and the state of the diode circuit in the “low level state”, “high level state”, and “high impedance state”.
[0036]
In the "high impedance state", the outputs of the high level setting voltage source 37 and the low level setting voltage source 44 are set to high impedance, and the output current values of the current sources 39 and 43 are set to "0A" and "0A" as shown in FIG. And Therefore, as shown in FIG. 12, the diode circuits 38, 40, 41 and 42 are each turned "OFF", and the output signal 101b is set to the "high impedance state".
[0037]
In the “high level state”, the high level setting voltage source 37 outputs the setting voltage “Vh”, and the output of the low level setting voltage source 44 is set to high impedance. As shown in FIG. 12, the output current values of the current sources 39 and 43 are “(m + n) · I” and “−m · I”. Therefore, as shown in FIG. 12, the diode circuits 38, 40, and 41 are each turned "ON", and the diode circuit 42 is turned "OFF".
[0038]
Among the output currents from the current source 39, “n · I” flows into the high-level setting voltage source 37 via a diode circuit 38 in which “n” diodes are connected in parallel, and “m · I” is “m”. Flows into the current source 43 via the diode circuits 40 and 41 connected in parallel. For this reason, the output signal 101b becomes equal to the output voltage of the high-level setting voltage source 37, and enters the “high-level state”.
[0039]
That is, the number of parallel diode circuits and the output current values of the current sources 39 and 43 are set so that the forward voltages of the diode circuits 38 and 40 become equal. Also, the same operation is performed in the “low level state”.
[0040]
As a result, according to the digital signal generator shown in FIG. 11 in the "high impedance state", the voltages of "P005" and "P006" in FIG. 11 are such that the voltage between the terminals of the diode circuits 40 and 41 is "0 V". As a result, the operation follows the change in the voltage "Vob" of the output signal 101b, and the delay time which is a problem in the conventional example shown in FIG. 7 does not occur. In addition, since the diode circuits 40 and 41 are turned "OFF", the leakage current from the output terminal does not increase.
[0041]
[Problems to be solved by the invention]
However, in the conventional example shown in FIG. 11, the load capacity of an external circuit such as an LSI under test is charged and discharged by the current sources 39 and 43 in the switching operation between the “high level state” and the “low level state”. There is a problem that the slew rate is deteriorated by the load capacity.
[0042]
Further, during the transition time from the “high level state” to the “low level state”, the impedance at the points “P005” and “P006” in FIG. 11 is high because the diode circuits 38 and 42 are simultaneously “OFF”. Therefore, there is a problem in that the output impedance is increased, the mismatch with the transmission circuit is generated, and the waveform quality is deteriorated.
Therefore, an object of the present invention is to realize a digital signal generator capable of improving timing accuracy, reducing leakage current and improving output impedance.
[0043]
[Means for Solving the Problems]
In order to achieve such an object, the invention according to claim 1 of the present invention is:
In a digital signal generator,
A first current source whose output current can be set to three states of 0, mI, and (m + n) I; an n-parallel connection of n diodes; a cathode connected to the high-level setting voltage source; and an anode connected to the first current A first diode circuit connected to a power source, a second diode circuit having m diodes connected in parallel, a cathode connected to the output terminal, and an anode connected to the first current source; , -MI,-(m + n) I, a second current source that can set three states, an n-parallel diode, an anode connected to the low-level setting voltage source, and a cathode connected to the second current source. A connected third diode circuit, a fourth diode circuit in which m diodes are connected in parallel, an anode is connected to the output terminal, and a cathode is connected to the second current source; Current Emitter follower circuit but the output is connected to two input terminals are connected to the output terminalAnd connecting two diodes in a forward connection and a reverse connection between a connection point of the second diode circuit and the fourth diode circuit and the output terminal,In the high level state, the output currents of the first and second current sources are (m + n) I and -mI. In the low level state, the output currents of the first and second current sources are mI and-(m + n) I. By setting the output currents of the first and second current sources to zero in the high impedance state,The timing accuracy can be improved, the leak current can be reduced, and the output impedance can be improved, and a sufficient current can be supplied to the load.
[0044]
The invention according to claim 2 is
In a digital signal generator,
A first current source capable of setting three states of output current of 0, mI, and (m + n) I, and two diodes connected in series, n in parallel, and a cathode connected to a high-level set voltage source A first diode circuit having an anode connected to the first current source, and m diodes connected in series connected in parallel to each other, and a cathode connected to an output terminal; and an anode connected to the first current source. A connected second diode circuit, a second current source whose output current can set three states of 0, -mI, and-(m + n) I, and two diodes connected in series, connected in parallel with n diodes A third diode circuit having an anode connected to the low-level setting voltage source and a cathode connected to the second current source, and two m series-connected diodes connected in parallel, and the anode is connected to the output terminal Connected to Caso A fourth diode circuit whose gate is connected to the second current source; and an emitter follower circuit whose first and second current sources are connected to two input terminals and whose output is connected to the output terminal. In addition, two diodes are connected in a forward direction and a reverse direction between a connection point of the second diode circuit and the fourth diode circuit and the output terminal, and the first and second diodes are connected in a high level state. 2 are (m + n) I and -mI, the output currents of the first and second current sources are mI and-(m + n) I in a low level state, and the first and second current sources are in a high impedance state. By setting the output current of the second current source to zero,,Improvement of timing accuracy, reduction of leakage current and output impedanceeven moreImprovements can be made, and sufficient current can be supplied to the load.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a digital signal generator according to the present invention.
[0048]
In FIG. 1, reference numerals 37 to 44, 102 and 103 denote the same reference numerals as in FIG. 11, 45 and 48 are transistors, 46 and 47 are resistors, and 101c is an output signal. Reference numerals 45 to 48 constitute the emitter follower circuit 200.
[0049]
The control signals 102 and 103 are connected to a high-level setting voltage source 37 and a low-level setting voltage source 44, respectively. The output of the high-level setting voltage source 37 is connected to the cathode of a diode circuit 38, and the anode of the diode circuit 38 is connected to a current source. One end of the transistor 39 is connected to the anode of the diode circuit 40 and the base of the transistor 45.
[0050]
The cathode of the diode circuit 40 outputs the output signal 101b as an output terminal and is connected to the anode of the diode circuit 41 and one end of the resistors 46 and 47. The cathode of the diode circuit 41 is connected to the cathode of the diode circuit 42, one end of the current source 43, and the base of the transistor 48, respectively, and the anode of the diode circuit 42 is connected to the output terminal of the low-level setting voltage source 44.
[0051]
The emitters of the transistors 45 and 48 are connected to the other ends of the resistors 46 and 47, respectively. The other end of the current source 39 and the collector of the transistor 45 are connected to the positive voltage source, respectively. Are respectively connected to a negative voltage source.
[0052]
Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. 2, 3 and 4. FIG. 2 is a table showing the output current values of the current sources and the states of the diode circuit and the emitter follower circuit in the "low level state", "high level state" and "high impedance state", and FIG. 3 shows the waveform of the output signal 101c. FIG. 4 is a characteristic curve diagram showing a leakage current in a “high impedance state”.
[0053]
In the “high-level state”, the high-level setting voltage source 37 outputs the setting voltage “Vh”, and the output of the low-level setting voltage source 44 has high impedance. Further, as shown in FIG. 2, the output current values of the current sources 39 and 43 are “(m + n) · I” and “−m · I”. As a result, as shown in FIG. 2, the diode circuits 38, 40 and 41 are turned "ON" and the diode circuit 42 is turned "OFF". Further, the emitter follower circuit 200 is turned “ON”.
[0054]
Of the output current from the current source 39, “n · I” flows into the high-level setting voltage source 37 via the diode circuit 38, and “m · I” flows into the current source 43 via the diode circuits 40 and 41. For this reason, the output signal 101c becomes equal to the output voltage of the high-level setting voltage source 37, and becomes the "high-level state". The same operation is performed for the “low level state”.
[0055]
In the “high impedance state”, the output current values of the current sources 39 and 43 are “0A” and “0A” as shown in FIG. Therefore, the diode circuits 38 and 42 are turned "OFF" as shown in FIG.
[0056]
At this time, since the output current values of the current sources 39 and 43 become “0 A”, the voltage between the terminals of the diode circuits 40 and 41 also becomes “0 V”, and the voltages at points “P007” and “P008” in FIG. It becomes substantially equal to the voltage "Voc" of the output signal 101c. Therefore, the emitter follower circuit 200 is also turned "OFF", so that the output signal 101c becomes "high impedance state".
[0057]
In addition, since the voltages of “P007” and “P008” in FIG. 1 operate so that the voltage between the terminals of the diode circuits 40 and 41 becomes “0 V”, it follows the change of the voltage “Voc” of the output signal 101c. become.
[0058]
That is, in the embodiment shown in FIG. 1, the emitter-follower circuit 200 is provided in the output stage, so that it is separated from the load capacitance of an external circuit such as an LSI under test. In operation, it is possible to improve that the slew rate is deteriorated by the load capacitance. In addition, an increase in leak current can be prevented.
[0059]
For example, as shown in FIG. 3, the deterioration of the slew rate due to the switching operation between the “high level state (5 V)” and the “low level state (0 V)” is not recognized, and the voltage of the output signal is reduced as shown in FIG. The leak current is stable against the change.
[0060]
Further, the diode circuits 38 and 42 are simultaneously turned "OFF" during the transition time from the "high level state" to the "low level state" as in the conventional example. However, if the output impedances of the current sources 39 and 43 are “ZIH” and “ZIL”, the current amplification factors of the transistors 45 and 48 are “hfe”, and the output impedance of the digital signal generator is “Zoc”,
Zoc = {ZIH × ZIL / (ZIH + ZIL)} / 2hfe (1)
It becomes. Here, if “hfe = 100”, the output impedance is reduced to about “1/200”.
[0061]
As a result, by providing the emitter follower circuit 200 in the output stage, it is possible to improve timing accuracy, reduce leakage current, and improve output impedance.
[0062]
FIG. 5 is a circuit diagram showing another embodiment of the digital signal generator according to the present invention. 5, reference numerals 37 to 48, 102, 103 and 200 denote the same reference numerals as in FIG. 1, reference numerals 49 and 50 denote diodes, and reference numeral 101d denotes an output signal. 49 and 50 constitute a diode circuit 201.
[0063]
The connection relationship is almost the same as that of the embodiment shown in FIG. 1 except that the connection point of the diode circuit 40 and the diode circuit 41 is connected to the cathode of the diode 49 and the anode of the diode 50. This is the point where the anode of the diode 49 and the cathode of the diode 50 are connected to the connection point of the resistor 47.
[0064]
Here, the operation of the embodiment shown in FIG. 5 will be described. The basic operation is the same as that of the embodiment shown in FIG. 1, and different points are as follows. That is, the output current of the emitter follower circuit is reduced by connecting the output terminal and the connection point of the diode circuit 40 and the diode circuit 41 via the diode circuit 201 instead of directly connecting the output terminal and the potential difference between them. Since the output current values of the sources 39 and 43 are no longer limited, a sufficient current can be supplied to an external load.
[0065]
As a result, by connecting the output terminal and the connection point between the diode circuit 40 and the diode circuit 41 via the diode circuit 201, it becomes possible to supply a sufficient current to the load.
[0066]
FIG. 6 is a circuit diagram showing another embodiment of the digital signal generator according to the present invention. In FIG. 6, reference numerals 37, 44 to 50, 102, 103 and 201 denote the same reference numerals as in FIG. , 40a and 41a are diode circuits in which two m series-connected diodes are further connected in parallel, 51 and 52 are diodes, 53 and 56 are transistors, 54 and 55 are resistors, and 101e is an output signal. 45 to 48 and 51 to 56 constitute the emitter follower circuit 202.
[0067]
Here, the operation of the embodiment shown in FIG. 6 will be described. The basic operation is the same as that of the embodiment shown in FIG. 5, and different points are as follows. That is, when the emitter follower circuit 200 has a two-stage configuration, the output impedances of the current sources 39 and 43 are "ZIH" and "ZIL", the current amplification factors of the transistors 45, 48, 53 and 56 are "hfe", respectively, If the output impedance of the generator is "Zoe",
Zoe = {ZIH × ZIL / (ZIH + ZIL)} / (2hfe × hfe) (2)
It becomes. Here, if "hfe = 100", the output impedance is further reduced to about "1/100" as compared with the output impedance shown in Expression (1).
[0068]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the invention of claim 1,By providing an emitter follower circuit in the output stage and connecting two diodes in the forward and reverse directions between the connection point of the two diode circuits and the output terminal, the timing accuracy is improved, the leakage current is reduced, and the output impedance is improved. Can be improved, and a sufficient current can be supplied to the load.
[0069]
According to the second aspect of the present invention, the emitter follower circuit has a two-stage configuration, and each diode circuit is composed of two diodes connected in series, and a connection point between the two diode circuits and an output terminal are provided. By connecting the two diodes in the forward and reverse directions, the timing accuracy can be improved, the leakage current can be reduced, and the output impedance can be further improved, and sufficient current can be supplied to the load. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a digital signal generator according to the present invention.
FIG. 2 is a table showing output current values of current sources and states of a diode circuit and an emitter follower circuit in a “low level state”, a “high level state”, and a “high impedance state”.
FIG. 3 is a characteristic curve diagram showing a waveform of an output signal.
FIG. 4 is a characteristic curve diagram showing a leakage current in a “high impedance state”.
FIG. 5 is a circuit diagram showing another embodiment of the digital signal generator according to the present invention.
FIG. 6 is a circuit diagram showing another embodiment of the digital signal generator according to the present invention.
FIG. 7 is a circuit diagram showing an example of a buffer circuit used in the digital signal generator.
FIG. 8 is a timing chart showing a state transition from a “high impedance state” to a “high level state” or a “low level state”.
FIG. 9 is a circuit diagram showing an example of a conventional buffer circuit that solves the problem.
FIG. 10 is a timing chart showing a state transition from a “high impedance state” to a “high level state” or a “low level state”.
FIG. 11 is a circuit diagram showing an example of a conventional digital signal generator which has solved the problem.
FIG. 12 is a table showing an output current value of a current source and a state of a diode circuit in a “low level state”, a “high level state”, and a “high impedance state”;
[Explanation of symbols]
1,2,16,17,26,29 Constant current source
3,18 Zener diode
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 23, 24, 25, 30, 33, 34, 35, 45, 48, 49, 50, 53, 56 transistors
19, 21, 22, 31, 32, 46, 47, 54, 55 Resistance
27,28 switch circuit
36 Control circuit
37 High level setting voltage source
38, 38a, 40, 40a, 41, 41a, 42, 42a, 201 Diode circuit
39, 43 current source
44 Low level setting voltage source
51, 52 Diode
100,100a Voltage setting signal
101, 101a, 101b, 101c, 101d, 101e Output voltage
102, 103 control signal
200,202 Emitter follower circuit

Claims (2)

In a digital signal generator,
A first current source whose output current can set three states of 0, mI, and (m + n) I;
A first diode circuit in which n diodes are connected in parallel, a cathode is connected to the high-level setting voltage source, and an anode is connected to the first current source;
A second diode circuit in which m diodes are connected in parallel, a cathode is connected to the output terminal, and an anode is connected to the first current source;
A second current source whose output current can set three states of 0, -mI, and-(m + n) I;
A third diode circuit in which n diodes are connected in parallel, the anode is connected to the low-level setting voltage source, and the cathode is connected to the second current source;
A fourth diode circuit in which m diodes are connected in parallel, an anode is connected to the output terminal, and a cathode is connected to the second current source;
An emitter follower circuit in which the first and second current sources are connected to two input terminals and an output is connected to the output terminal ;
Connecting two diodes in a forward connection and a reverse connection between a connection point of the second diode circuit and the fourth diode circuit and the output terminal;
In the high level state, the output currents of the first and second current sources are (m + n) I and -mI, and in the low level state, the output currents of the first and second current sources are mI and-(m + n) I. A digital signal generator wherein the output currents of the first and second current sources are set to zero in a high impedance state. In a digital signal generator,
  A first current source whose output current can set three states of 0, mI, and (m + n) I;
  A first diode circuit in which n diodes connected in series are connected in parallel, a cathode is connected to a high-level setting voltage source, and an anode is connected to the first current source;
  A second diode circuit in which m diodes connected in series are connected in parallel, a cathode is connected to an output terminal, and an anode is connected to the first current source;
  A second current source whose output current can set three states of 0, -mI, and-(m + n) I;
  A third diode circuit in which two diodes connected in series are connected in parallel, an anode is connected to the low-level setting voltage source, and a cathode is connected to the second current source;
  A fourth diode circuit in which m diodes connected in series are connected in parallel, an anode is connected to the output terminal, and a cathode is connected to the second current source;
  An emitter follower circuit in which the first and second current sources are connected to two input terminals and an output is connected to the output terminal;
  Connecting two diodes in a forward connection and a reverse connection between a connection point of the second diode circuit and the fourth diode circuit and the output terminal;
  In the high level state, the output currents of the first and second current sources are (m + n) I and -mI. In the low level state, the output currents of the first and second current sources are mI and-(m + n) I. A digital signal generator wherein the output currents of the first and second current sources are set to zero in a high impedance state.

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