JP3551594B2 - Active matrix substrate - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix substrate for a liquid crystal display device. More specifically, the present invention relates to the structure of each pixel formed on an active matrix substrate.
[0002]
[Prior art]
In an active matrix substrate used in a liquid crystal display device, as shown in FIG. 12, a pixel region 5A is defined by a data line 3A and a gate line 4A extending in directions orthogonal to each other, and each pixel region 5A has a pixel area. A liquid crystal cell 6A to which an image signal is input via a thin film transistor (hereinafter, referred to as a TFT) 10A is configured. Therefore, one pixel corresponds to the intersection of the data line 3A and the gate line 4A. In the pixel region 5A, a storage capacitor 51A is formed between the pixel region 5A and the preceding gate line 4A or between the pixel region 5A and a storage capacitor line (not shown) for the purpose of enhancing the storage characteristics of the liquid crystal cell 6A. Generally, it is done.
[0003]
Here, as shown in FIGS. 13 and 14, the TFT 10A is connected to the source region 11A and the pixel electrode 19A which are electrically connected to the data line 3A via the contact hole 17A of the interlayer insulating film 16A on the substrate 20A. On the other hand, a drain region 12A electrically connected via a contact hole 18A of the interlayer insulating film 16A, a channel region 13A for forming a channel between the drain region 12A and the source region 11A, and a gate insulating film for the channel region 13A It is composed of gate electrodes 15A facing each other via 14A.
[0004]
[Problems to be solved by the invention]
However, in the conventional active matrix substrate 2A, if the operation of the TFT 10A is abnormal in any of the pixel regions 5A, the display operation is not completely performed in the pixel region 5A to which the TFT 10A corresponds, and the display has a point defect. There is a problem that occurs. In addition, if there is an abnormality in the gate signal, the operation of the entire pixel region 5A for one line corresponding to the gate line 4A occurs, causing a fatal abnormality such as a display line defect. .
[0005]
Further, in the conventional active matrix substrate 2A, every time the TFT 10A switches from the ON state to the OFF state, the capacitance is caused by the coupling between the capacitance parasitic between the gate and the drain (pixel electrode) of the TFT 10A and the capacitance of the liquid crystal cell 6A. Then, as shown in FIG. 15, a push-up or a push-down corresponding to ΔV occurs in the gap voltage (pixel potential Vp) of the liquid crystal cell 6A, and a flicker (screen flicker) and the like occur in the display. There is a problem. Therefore, conventionally, a method is employed in which the potential Vcom of the common electrode is shifted by a voltage value corresponding to the average value of ΔV with respect to the central potential Vc of the image signal transmitted via the data line 3A. The method has a problem that the counter electrode cannot be set to the ground potential and the circuit configuration becomes complicated.
[0006]
In view of the above problems, an object of the present invention is to provide an active matrix substrate and a liquid crystal display device capable of improving the structure in a pixel region, preventing the occurrence of display defects, and performing high-quality display. To provide.
[0007]
Still another object of the present invention is to provide an active matrix substrate and a liquid crystal display device which can improve the holding characteristics of the pixel cells by adding a holding capacitor for each pixel cell and perform high-quality display. is there.
[0008]
In order to solve the above problems, an active matrix substrate according to the present invention comprises an intersection between a data line formed on the substrate and a first gate line, and an intersection between the data line and a second gate line. One pixel is configured to correspond to two intersections, and each of the pixels is driven by a first gate signal applied from the first gate line, and a source region is electrically connected to the data line. An N-type thin film transistor, a first pixel electrode electrically connected to a drain region of the N-type thin film transistor, and a source region electrically connected to the same data line as the N-type thin film transistor, from the second gate line. A P-type thin film transistor driven together with the N-type thin film transistor by a second gate signal which is applied and has an inverted relationship with respect to the first gate signal. And data, and a second pixel electrode electrically connected to the drain region of the P-type thin film transistor, the N-type thin film transistor and the P-type thin film transistor characterized in that it is on-off controlled at the same timing.
[0009]
In the active matrix substrate thus configured, in the pixel region, the N-type TFT and the P-type TFT are turned on / off at the same timing by the first gate signal and the second gate signal. Therefore, in a normal state, the N-type TFT and the P-type TFT are turned on at the same timing, and the same image information is written in the first liquid crystal cell and the second liquid crystal cell, respectively. Further, even if one of the N-type TFT and the P-type TFT has an abnormal operation, the image information is written into the liquid crystal cell via the normally operating TFT. Therefore, complete point defects do not occur in the display. Further, even if one of the first gate signal and the second gate signal has an abnormality, since the display drive is performed by the normal gate signal, a fatal error such as a complete line defect does not occur. No defects occur.
[0010]
Further, even in a normal state, when the first gate signal and the second gate signal shift from the on level to the off level, a push-down occurs in the first liquid crystal cell, and the second liquid crystal cell includes: Although the push-up occurs, in the present invention, since the timings match, the push-up compensates for the display disturbance caused by the push-down, and the push-down compensates the display disturbance caused by the push-up. Therefore, even if the potential of the counter electrode is not shifted from the center level of the image signal, display disturbance such as flicker does not occur. Therefore, in the liquid crystal display device using the active matrix substrate of the present example, the circuit configuration can be simplified, for example, the counter electrode can be set to the ground potential. Further, even if a complementary TFT is formed in one pixel region, the TFT in the pixel region may be formed in the driver portion by using the process of forming the CMOS circuit as it is, so that the number of manufacturing steps is increased. Absent.
[0011]
In the present invention, the first pixel electrode includes a first storage capacitor between the first pixel electrode and the second gate line corresponding to an adjacent pixel, and the second pixel electrode corresponds to an adjacent pixel. It is preferable that a storage capacitor be provided between the first gate line and the first gate line.
[0012]
In the present invention, instead of the above-described storage capacitor, a first storage capacitor line forming a first storage capacitor between the first pixel electrode and each of the pixels, and the second pixel electrode And a second storage capacitor line forming a second storage capacitor.
[0013]
In this case, the first storage capacitor line supplies a signal having the same phase and opposite polarity as the first gate signal for driving the N-type TFT of the pixel corresponding to the storage capacitor line, The second storage capacitor line may be configured to supply a signal having the same phase and opposite polarity as the second gate signal for driving the P-type TFT of the pixel corresponding to the storage capacitor line. preferable.
[0014]
Further, in the present invention, instead of the above storage capacitor, the first pixel electrode is provided between the first gate electrode and the second gate line for driving the P-type TFT of a pixel to which the pixel electrode belongs. And the second pixel electrode is configured to have a second storage capacitance between the second pixel electrode and the first gate line for driving the N-type TFT of the pixel to which the pixel electrode belongs. May be.
[0015]
When a storage capacitor is configured for each pixel electrode in this manner, the storage characteristics of each liquid crystal cell are improved, so that high-quality display can be performed. In particular, in the case where the storage capacitor is formed by using the overlap with the gate line, the aperture ratio in the pixel region is not deteriorated.
[0016]
In the present invention, the data line includes a pixel region in each of the pixels, a first pixel region in which the first pixel electrode is located in a direction in which the first gate line and the second gate line extend. It is preferable that the first pixel electrode and the second pixel region are located so as to be divided into two.
[0017]
In this case, in each of the pixels, it is preferable that a formation region of the N-type TFT and a formation region of the P-type TFT are included in a formation region of the data line.
[0018]
With this structure, the data line forming region is used as it is as the TFT forming region, so that the opening can be expanded by the area occupied by the TFT in the conventional structure. Is improved. Furthermore, since the data line covers the entire region where the TFT is formed, light does not leak from the boundary between the channel region and the source / drain region and the channel region, so that the display quality is high.
[0019]
In this case, the N-type TFT and the P-type TFT include a channel region connecting a source region and a drain region, a gate electrode facing the channel region via a gate insulating film, A first interlayer insulating film formed in an upper layer and the data line formed in an upper layer of the first interlayer insulating film are electrically connected to the source region via the first interlayer insulating film and the gate insulating film. A first contact hole for making an electrical connection, a second interlayer insulating film formed above the data line, the first pixel electrode formed above the second interlayer insulating film, and the second interlayer insulating film. Preferably, the second pixel electrode has the second interlayer insulating film, the first interlayer insulating film, and a second contact hole for electrically connecting to the drain region via the gate insulating film. .
[0020]
In the active matrix substrate configured as described above, since the pixel electrodes are in the upper layer, the alignment of the liquid crystal can be effectively controlled. Moreover, since the data lines are covered with the second interlayer insulating film, the potential applied to the data lines does not affect the alignment of the liquid crystal, so that the display quality is high.
[0021]
The second contact hole includes a lower contact hole formed with respect to the first interlayer insulating film and the gate insulating film, and the second interlayer insulating film at a position corresponding to the lower contact hole. An upper contact hole formed in the film, and a metal layer forming the data line is left insulated and separated from the data line inside the lower contact hole. It is preferable that the first pixel electrode and the second pixel electrode are electrically connected to the drain region.
[0022]
In the active matrix substrate configured as described above, the pixel electrode is electrically connected to the drain region via the metal layer remaining inside the second contact hole, so that the silicon film and the ITO film are directly electrically connected. The problem that the connection resistance generated in such a case is large can be solved.
[0023]
Further, instead of the above-described TFT structure, the second contact hole corresponds to a lower contact hole formed with respect to the first interlayer insulating film and the gate insulating film, and corresponds to the lower contact hole. And a region corresponding to the upper contact hole formed in the second interlayer insulating film at a position, and a region corresponding to the upper contact hole may be a window opening region of the data line.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0025]
[Example 1]
FIG. 1A is an explanatory diagram schematically showing a configuration of an active matrix substrate of the liquid crystal display device of the present example.
[0026]
In FIG. 1A, the liquid crystal display device 1 of the present example is basically located on the active matrix substrate 2 at a position corresponding to the intersection of the data line 3 and the gate line 4, similarly to the conventional liquid crystal display device. Each of the pixel regions 5 has a liquid crystal cell to which an image signal is input via a pixel TFT. However, in this example, since the gate line 4 is configured by two gate lines (the first gate line 42N and the second gate line 42P), the first gate line 42N and the data line 3 One pixel corresponds to the intersection and the two intersections consisting of the intersection of the second gate line 42P and the data line 3.
[0027]
A data driver unit 7 including a shift register 71, a level shifter 72, a video line 73, and an analog switch 74 is configured for the data line 3, and a scan driver including a shift register 81 and a level shifter 82 is configured for the gate line 4. The unit 8 is configured. Here, in the data driver section 7 and the scanning driver section 8, as shown in FIG. 1B, a multi-stage CMOS circuit is constituted by N-type TFTs n1, n2... And P-type TFTs p1, p2. Have been.
[0028]
In particular, in this example, as will be described later, it is necessary to generate two types of gate signals having the same phase and opposite polarities. Therefore, as shown in FIG. The non-inverting circuit 83N and the inverting circuit 83P are arranged at the subsequent stage of the shift register 81 and the NAND gate buffer 82. Here, in FIG. 2B, when the signal output from the NAND gate buffer 82 is represented by a signal A, the signals output from the non-inverting circuit 83N and the inverting circuit 83P are as shown by signals B and C, respectively. , The waveforms are inverted.
[0029]
In FIG. 1, the active matrix substrate 2 includes only the active matrix unit 9 formed on the substrate, the one in which the data driver unit 7 is formed on the same substrate as the active matrix unit 9, and the active matrix unit 9. The scanning driver unit 8 is configured on the same substrate as the above, and the data driver unit 7 and the scanning driver unit 8 are both configured on the same substrate as the active matrix unit 9. Further, even in the case of the active matrix substrate 2 with a built-in driver, the shift register 71, the level shifter 72, the video line 73, the analog switch 74, and the like included in the data driver unit 7 are all formed on the active matrix substrate 2. There are a type with a built-in driver and a type with a built-in partial driver in which a part of them is formed on the active matrix substrate 2. The present invention can be applied to any type of active matrix substrate.
[0030]
In this example, since all the pixel regions 5 have the same configuration, only the pixel region 52 will be described.
[0031]
For the pixel region 52, the gate line 4 is composed of two gate lines consisting of a first gate line 42N and a second gate line 42P, and at the two intersections of these gate lines and the data line 3 On the other hand, one pixel is configured. Further, the scan driver section 8 outputs a first gate signal G2N and a second gate signal G2P for each gate line. Here, a non-inverting circuit 83N and an inverting circuit 83P are configured in the scan driver unit 8 so that the first gate signal G2N and the second gate signal G2P are signals having an inverted relationship. ing.
[0032]
In the pixel region 52, complementary N-type TFTs 10N and P-type TFTs 10P driven by the respective gate signals G2N and G2P supplied from the first gate line 42N and the second gate line 42P are formed. A first pixel electrode 62N and a second pixel electrode 62P made of an ITO film are connected to the drain region of each TFT. Therefore, in one pixel region 52, the first liquid crystal cell 32N is formed between the first pixel electrode 62N and the counter substrate (not shown), and the second pixel electrode 62P and the counter substrate (not shown). (Not shown)) in a state where the second liquid crystal cell 32P is formed.
[0033]
However, the source regions of the N-type TFT 10N and the P-type TFT 10P are both connected to the same data line 3.
[0034]
As shown in an enlarged view of the pixel region 52 in FIG. 3A, the first pixel electrode 62N has an end 620N extending to the adjacent pixel region 51 across the first gate line 42N. The first storage capacitor 92 </ b> N is configured by overlapping with the second gate line 41 </ b> P for the pixel region 51. Similarly, the end 620P of the second pixel electrode 62P extends to the adjacent pixel region 53 across the second gate line 42P, and the second pixel electrode 62P is connected to the first gate line 43N for the pixel region 53. The overlap constitutes a second storage capacitor 92P.
[0035]
In the pixel region 52 of the active matrix substrate 2 configured as described above, as shown in FIG. 3B, an N-type TFT 10N is formed by the first gate signal G2N and the second gate signal G2P having an inverted signal relationship. And the P-type TFT 10P are turned on / off at the same timing. Therefore, in a normal state, the N-type TFT 10N and the P-type TFT 10P are turned on at the same timing, and the first liquid crystal cell is turned on via the data line 3, the first pixel electrode 62N, and the second pixel electrode 62P. The same image information is written into 32N and the second liquid crystal cell 32P, respectively.
[0037]
In addition, even if any of the N-type TFT 10N and the P-type TFT 10P has an abnormal operation, in the pixel region 52, the liquid crystal cell (the liquid crystal cell 32N or the second liquid crystal cell 32P) is passed through the normally operating TFT. Image information is written in the. Therefore, complete point defects do not occur in the display. Further, even if one of the first gate signal G2N and the second gate signal G2P has an abnormality, the display drive is performed by the normal gate signal, so that a fatal defect such as a complete line defect is generated. Does not occur.
[0038]
Further, even in a normal state, when the first gate signal G2N and the second gate signal G2P shift from the on level to the off level, a push-down occurs in the first liquid crystal cell 32N, and the second liquid crystal cell 32N Although the push-up occurs in the 32P, in this example, since the timings match, the push-up compensates for the display disorder caused by the push-down, and pushes down the display disorder caused by the push-up. Supplements. Therefore, even if the potential of the counter electrode is not shifted from the center level of the image signal, display disturbance such as flicker does not occur. Therefore, in the liquid crystal display device using the active matrix substrate 2 of the present example, the circuit configuration can be simplified, for example, the counter electrode can be set to the ground potential.
[0039]
Further, in the pixel region 52, for the first liquid crystal cell 32N, a first storage capacitor 92N is formed between the first pixel electrode 62N and the second gate line 41P of the adjacent pixel region 51. Then, as shown in FIG. 3B, when the first gate signal G2N in the pixel region 52 is at a level (high level) that turns on the N-type TFT 10N (when a positive-direction pulse is applied). The second gate signal G1P supplied from the second gate line 41P to the pixel region 51 is at an off level (low level). Similarly, in the pixel region 52, a second storage capacitor 92P is provided between the second pixel electrode 62P and the first gate line 43N of the adjacent pixel region 53 for the second liquid crystal cell 32P. When the second gate signal G2P in the pixel region 52 is at a level (low level) for turning on the P-type TFT 10P (when a pulse in the negative direction is applied), the first gate signal G2P is The first gate signal G3N supplied from the gate line 43N is at the off level (high level). Therefore, electric charges are accumulated in the first storage capacitor 92N and the second storage capacitor 92P in synchronization with the timing at which image information is written in the first liquid crystal cell 32N and the second liquid crystal cell 32P. Both the liquid crystal cell 32N and the second liquid crystal cell 32P have high retention characteristics. Therefore, high quality display can be performed.
[0040]
Moreover, in the pixel region 52, the storage capacitors (the first storage capacitor 92N, the second storage capacitor 92N, the second storage capacitor 92N, Since the storage capacitor 92P) is configured, the aperture ratio in the pixel region 52 is not impaired.
[0041]
Further, in this example, even though complementary TFTs (N-type TFT 10N and P-type TFT 10P) are formed in one pixel region 52, the data driver unit 7 and the scan driver unit 8 form an N-type CMOS circuit. Since the complementary TFT is formed in the pixel region 52 by utilizing the process of forming the type TFT and the P-type TFT as they are, the number of manufacturing steps does not increase.
[0042]
[Modification of First Embodiment]
In the first embodiment, in configuring the first storage capacitor 92N and the second storage capacitor 92P, the first pixel electrode 62N and the second pixel electrode 62P are extended to the adjacent pixel regions 51 and 53, Although the structure in which the interlayer insulating film overlaps with the gate line as a dielectric is used, a structure as shown in FIG. 4 may be used. That is, in the pixel region 52, the N-type TFTs 10N and 10N are overlapped with the second gate line 42P and the first gate line 41P via the gate insulating film at the ends of the adjacent pixel regions 51 and 53, respectively. And the high concentration regions SUB2N and SUB2P are formed in the same process as the source / drain regions of the P-type TFT 10P, and these high concentration regions SUB2N and SUB2P are formed by the first pixel electrode 62N and the second pixel electrode 62P. May be electrically connected to each other via contact holes in the interlayer insulating film and the gate insulating film. In such a structure, the second gate line 42P and the first gate line 41P and the high-concentration regions SUB2N and SUB2P each have a structure in which a gate insulating film is used as a dielectric, so that the first pixel A first storage capacitor 92N and a second storage capacitor 92P can be formed between the electrode 62N and the second pixel electrode 62P, and the second gate line 42P and the first gate line 41P, respectively.
[0043]
[Example 2]
FIG. 5 is an explanatory diagram schematically showing the configuration of the active matrix substrate of the liquid crystal display device of this example. Since the basic configuration of the active matrix substrate of this example is the same as that of the first embodiment, corresponding portions are denoted by the same reference numerals and description thereof will be omitted.
[0044]
In FIG. 5, also in the active matrix substrate 2 of this example, one pixel region 5 (pixel) corresponds to two intersections of the data line and the two gate lines, and any of the pixel regions 5 Since they have the same configuration, only the pixel region 52 will be described.
[0045]
For the pixel region 52, the gate line 4 is composed of two gate lines including a first gate line 42N and a second gate line 42P, and for each of these gate lines, the scanning driver unit 8 The first gate signal G2N and the second gate signal G2P are respectively output. Here, the first gate signal G2N and the second gate signal G2P have the same phase and opposite polarity.
[0046]
Further, in the pixel region 52, complementary N-type TFTs 10N and P-type TFTs 10P driven by the respective gate signals G2N and G2P supplied from the first gate line 42N and the second gate line 42P are formed. A first pixel electrode 62N and a second pixel electrode 62P are connected to the drain region of each TFT. Therefore, in one pixel region 52, the first liquid crystal cell 32N is formed between the first pixel electrode 62N and the counter substrate (not shown), and the second pixel electrode 62P and the counter substrate (not shown). (Not shown)) in a state where the second liquid crystal cell 32P is formed. However, the source regions of the N-type TFT 10N and the P-type TFT 10P are both connected to the same data line 3.
[0047]
Further, in the pixel region 52, two storage capacitance lines including a first storage capacitance line 42CN and a second storage capacitance line 42CP parallel to the first gate line 42N and the second gate line 42P are configured. Have been. Here, each of the first storage capacitor line 42CN and the second storage capacitor line 42CP is a layer formed simultaneously with the gate line, and an inversion circuit 83P is configured for the first storage capacitor line 42CN. A non-inverting circuit 83N is formed on the second storage capacitor line 42CP. Therefore, the signals C2N and C2P supplied from the first storage capacitor line 42CN and the second storage capacitor line 42CP have the same phase and opposite polarities.
[0048]
In addition, a first storage capacitor 92N and a second storage capacitor are provided between the first storage capacitor line 42CN and the second storage capacitor line 42CP and the first pixel electrode 62N and the first pixel electrode 62N. Each of the capacitors 92P is configured. That is, as shown in an enlarged view of the pixel region 52 in FIG. 6A, the end 620N of the first pixel electrode 62N has a first storage capacitor via an interlayer insulating film (not shown). The first storage capacitor 92N is formed by overlapping with the line 42CN, and the end 620P of the second pixel electrode 62P is connected to the second storage capacitor line 42CP via an interlayer insulating film (not shown). , A second storage capacitor 92P is configured.
[0049]
In the active matrix substrate 2 thus configured, for example, in the pixel region 52, as shown in FIG. 6B, the first gate signal G2N and the second gate signal G2P having an inverted signal relationship are N-type. The TFT 10N and the P-type TFT 10P are turned on / off at the same timing, and image information is written in the first liquid crystal cell 32N and the second liquid crystal cell 32P, respectively. Even if any of the N-type TFT 10N and the P-type TFT 10P has an operation abnormality, in the pixel region 52, the liquid crystal cell (the liquid crystal cell 32N or the second liquid crystal cell 32P) is passed through the normally operating TFT. Since the image information is written into the image data, the same effect as that of the first embodiment can be obtained, for example, no complete point defect or line defect occurs.
[0050]
Further, in the pixel region 52, for the first liquid crystal cell 32N, a first storage capacitor 92N is formed between the first pixel electrode 62N and the first storage capacitor line 42CN, and a second storage capacitor 92N is formed. For the liquid crystal cell 32P, a second storage capacitor 92P is formed between the second pixel electrode 62P and the second storage capacitor line 42CP. Moreover, as shown in FIG. 6B, the first gate signal G2N and the signal C2N output from the first storage capacitor line 42CN have the same phase and opposite polarity. The second gate signal G2P and the signal C2P output from the second storage capacitor line 42CP have the same phase and opposite polarity. Therefore, when the first gate signal G2N in the pixel region 52 is at a level (high level) that turns on the N-type TFT 10N (when a positive-direction pulse is applied), the first gate signal G2N A negative pulse (low-level signal) is output as the signal C2N from the storage capacitor line 42CN, and the second gate signal G2P in the pixel region 52 has a level (low level) that turns on the P-type TFT 10P. At some point (when a negative-direction pulse is applied), a positive-direction pulse (high-level signal) is output as a signal C2P from the second storage capacitor line 42CP to the pixel region 52. Therefore, electric charges are accumulated in the first storage capacitor 92N and the second storage capacitor 92P in synchronization with the timing at which image information is written to the first liquid crystal cell 32N and the second liquid crystal cell 32P. Both the liquid crystal cell 32N and the second liquid crystal cell 32P have high retention characteristics. Therefore, high quality display can be performed.
[0051]
Here, when the amplitude of the first gate signal G2N is V1 (V) and the amplitude of the signal C2N is V2 (V), when the levels of V1 and V2 are set so as to satisfy the following equation, In the liquid crystal cell 32N, the feedthrough can be minimized, and even if present, the feedthrough can be offset between the first liquid crystal cell 32N and the second liquid crystal cell 32P.
[0052]
C1 << C2 <C3
V1 · (C1 + C2) = V2 · C3
V1 = V2
Here, C1 is the capacitance between the gate and the source of the N-type TFT 10N, C2 is the capacitance between the gate and the drain of the N-type TFT 10N, C3 is the capacitance value of the first storage capacitor 92N, The same applies to the type TFT 10P.
[0053]
In addition, also in this example, as shown in a modification example of the first embodiment, the high-concentration region formed simultaneously with the source / drain regions of the TFT, the first pixel electrode 62N and the second pixel electrode 62P are formed. The structure may be such that the high-concentration regions and the storage capacitance lines are electrically connected via contact holes, and the gate insulating film is overlapped with the dielectric film as a dielectric film.
[0054]
[Example 3]
FIG. 7 is an explanatory diagram schematically showing the configuration of the active matrix substrate of the liquid crystal display device of the present example. Since the basic configuration of the active matrix substrate of this example is the same as that of the first embodiment, corresponding portions are denoted by the same reference numerals and description thereof will be omitted.
[0055]
In FIG. 7, in the active matrix substrate 2 of the present example, as for the pixel region 52, the gate line 4 is composed of two gate lines including a first gate line 42N and a second gate line 42P. For each gate line, the scan driver section 8 outputs a first gate signal G2N and a second gate signal G2P, respectively. Here, the scan driver unit 8 applies a non-inverting circuit to the common clock signal so that the first gate signal G2N and the second gate signal G2P have the same phase and opposite polarity. 83N and an inverting circuit 83P are configured.
[0056]
Further, in the pixel region 52, complementary N-type TFTs 10N and P-type TFTs 10P driven by the respective gate signals G2N and G2P supplied from the first gate line 42N and the second gate line 42P are formed, A first pixel electrode 62N and a second pixel electrode 62P are connected to the drain region of each TFT, respectively. Therefore, in one pixel region 52, the first liquid crystal cell 32N is formed between the first pixel electrode 62N and the counter substrate (not shown), and the second pixel electrode 62P and the counter substrate (not shown). (Not shown)) in a state where the second liquid crystal cell 32P is formed. However, the source regions of the N-type TFT 10N and the P-type TFT 10P are both connected to the same data line 3.
[0057]
8A, the data line 3 corresponding to the pixel region 52 is formed in the pixel region 52 in the extending direction of the first gate line 42N and the second gate line 42P. Is divided into a first pixel region 52N where the first pixel electrode 62N is located and a second pixel region 52P where the second pixel electrode 62P is located. The N-type TFT 10N and the P-type TFT 10P are connected to the data line 3 from both sides.
[0058]
The end 620N of the first pixel electrode 62N overlaps the second gate line 42P corresponding to the same pixel region 52 to form a first storage capacitor 92N, and the end 620N of the second pixel electrode 62P The portion 620P constitutes a second storage capacitor 92P by overlapping with the first gate line 43N corresponding to the same pixel region 52.
[0059]
In the active matrix substrate 2 configured as described above, in the pixel region 52, as shown in FIG. 8B, the N-type TFT 10N and the N-type TFT 10N are switched by the first gate signal G2N and the second gate signal G2P having an inverted signal relationship. The P-type TFTs 10P are turned on and off at the same timing. Therefore, the same image information is written in the first liquid crystal cell 32N and the second liquid crystal cell 32P, respectively. Here, even if one of the N-type TFT 10N and the P-type TFT 10P has an operation abnormality, the image information is stored in the liquid crystal cell (the liquid crystal cell 32N or the second liquid crystal cell 32P) via the normally operating TFT. Will be written. Therefore, the display has the same effect as that of the first embodiment, such that a fatal defect such as a complete point defect or a line defect does not occur.
[0060]
In the pixel region 52, for the first liquid crystal cell 32N, a first storage capacitor 92N is formed between the first pixel electrode 62N and the first storage capacitor line 42CN, and a second storage capacitor 92N is formed. For the liquid crystal cell 32P, a second storage capacitor 92P is formed between the second pixel electrode 62P and the second storage capacitor line 42CP. Further, as shown in FIG. 8B, when the first gate signal G2N in the pixel region 52 is at a level (high level) for turning on the N-type TFT 10N, the second gate signal G2P becomes low level. It is in. Conversely, when the second gate signal G2P is at a level (low level) that turns on the P-type TFT 10P, the first gate signal G2N is at a high level. Therefore, electric charges are accumulated in the first storage capacitor 92N and the second storage capacitor 92P in synchronization with the timing at which image information is written to the first liquid crystal cell 32N and the second liquid crystal cell 32P. Both the liquid crystal cell 32N and the second liquid crystal cell 32P have high retention characteristics. Therefore, high quality display can be performed.
[0061]
Here, instead of the first gate signal G2N and the second gate signal G2P having the waveform shown in FIG. 8B, the first gate signal G2N and the second gate signal G2N having the waveform shown in FIG. The gate signal G2P may be used. In this case, the amplitude when the first gate signal G2N and the second gate signal G2P turn on the TFT is V3 (V), and the amplitude of the pulse which is inverted before that is V4 (V). In this case, when the levels of V3 and V4 are set so as to satisfy the following equation, the feedthrough can be minimized in each of the liquid crystal cells 32N and 32P. Between the liquid crystal cell 32N and the second liquid crystal cell 32P.
[0062]
C1 << C2 <C3
V3 · (C1 + C2) = V4 · C3
Here, C1 is the capacitance between the gate and the source of the TFT, C2 is the capacitance between the gate and the drain of the TFT, and C3 is the capacitance value of the storage capacitance.
[0063]
In addition, also in this example, as shown in a modification example of the first embodiment, the high-concentration region formed simultaneously with the source / drain regions of the TFT, the first pixel electrode 62N and the second pixel electrode 62P are formed. The structure may be such that the high-concentration regions and the storage capacitance lines are electrically connected via contact holes, and the gate insulating film is overlapped with the dielectric film as a dielectric film.
[0064]
[Example 4]
FIG. 9 is an explanatory diagram schematically showing the configuration of the active matrix substrate of the liquid crystal display device of this example. Note that the basic configuration of the active matrix substrate of this example is the same as that of the third embodiment, and is therefore represented by the same equivalent circuit as that of FIG. That is, for the pixel region 52, the gate line 4 is composed of two gate lines including the first gate line 42N and the second gate line 42P, and the scanning driver unit 8 is provided for each of these gate lines. Output the first gate signal G2N and the second gate signal G2P, respectively. Here, the scan driver unit 8 applies a non-inverting circuit to the common clock signal so that the first gate signal G2N and the second gate signal G2P have the same phase and opposite polarity. 83N and an inverting circuit 83P are configured.
[0065]
Further, in the pixel region 52, an N-type TFT 10N and a P-type TFT 10P driven by the respective gate signals G2N and G2P supplied from the first gate line 42N and the second gate line 42P are formed. The first pixel electrode 62N and the second pixel electrode 62P are respectively connected to the drain region. Therefore, in one pixel region 52, the first liquid crystal cell 32N is formed between the first pixel electrode 62N and the counter substrate (not shown), and the second pixel electrode 62P and the counter substrate (not shown). (Not shown)) in a state where the second liquid crystal cell 32P is formed.
[0066]
As shown in an enlarged view of the pixel region 52 in FIG. 9, the data line 3 corresponding to the pixel region 52 divides the pixel region 52 in the extending direction of the first gate line 42N and the second gate line 42P. It extends straight so as to be divided into two parts, a first pixel area 52N where one pixel electrode 62N is located, and a second pixel area 52P where the second pixel electrode 62P is located.
[0067]
The end portion 620P of the first pixel electrode 62N overlaps the second gate line 42P corresponding to the same pixel region 52 to form a first storage capacitor 92N, and the end portion 620P of the second pixel electrode 62P. Overlaps with the first gate line 43N corresponding to the same pixel region 52 to form a second storage capacitor 92P.
[0068]
Here, the overlapping widths of the first pixel electrode 62N and the second pixel electrode 62P and the second gate line 42P and the first gate line 42N are ΔNP and ΔPN, respectively. The other end 621N of the first pixel electrode 62N also overlaps with the first gate line 42N corresponding to the same pixel region 52, and the second pixel electrode 62P has the other end 621P. Although the second gate line 43P corresponding to the same pixel region 52 also overlaps, their overlapping widths are ΔNN and ΔPP, respectively, which are significantly smaller than the aforementioned ΔNP and ΔPN. Therefore, the first storage capacitor 92N and the second liquid crystal cell 32P sufficiently function as storage capacitors for the first liquid crystal cell 32N and the second liquid crystal cell 32P.
[0069]
The same applies to the P-type TFT 10P, except that the source-drain capacitance of the N-type TFT 10N is C5, the other end 621N of the first pixel electrode 62N is the first gate line 42N corresponding to the same pixel region 52. When the capacitance caused by the overlap is C6 and the capacitance value of the first storage capacitor 92N is C7, C5, C6, and C7 are represented by the following equations.
C5 <C6 <C7
(C5 + C6) = C7
Is satisfied, the feedthrough can be minimized even when the parasitic capacitance of the N-type TFT 10N varies. Even if the parasitic capacitance exists, the first liquid crystal cell 32N and the second liquid crystal cell 32P Can be offset between.
[0070]
In this example, the channel length direction of the N-type TFT 10N and the P-type TFT 10P is set along the direction in which the data line 3 extends, and the N-type TFT 10N and the P-type TFT 10P are formed in the formation region of the data line 3. ing.
[0071]
Further, in this example, since the formation region of each TFT is covered with the data line 3, the structure is shown in FIGS. 10A and 10B so that the data line 3 can be used as a black matrix. .
[0072]
That is, in FIGS. 10A and 10B, in both the N-type TFT 10N and the P-type TFT 10P, the source region 11 electrically connected to the data line 3 and the pixel electrode 19 are formed on the substrate 20. It comprises a drain region 12 to be electrically connected, a channel region 13 for forming a channel between the drain region 12 and the source region 11, and a gate electrode 15 facing the channel region 13 via a gate insulating film 14. The gate electrode 15 has the same structure as a conventional TFT in that it is configured as a part of a gate line.
[0073]
However, in this example, a first interlayer insulating film 16 is formed on the gate electrode 15, and the data line 3 formed on the first interlayer insulating film 16 is formed on the first interlayer insulating film 16. It is electrically connected to the source region 11 via a contact hole 17 formed in the gate insulating film 16 and the gate insulating film 14.
[0074]
In addition, a second interlayer insulating film 18 is formed on the data line 3, and the first pixel electrode 62 </ b> N and the second pixel electrode 62 </ b> P formed on the second interlayer insulating film 18 are It is electrically connected to the drain region 12 through a second contact hole 19 formed in the second interlayer insulating film 18, the first interlayer insulating film 16, and the gate insulating film 14.
[0075]
Here, the second contact hole 19 has a lower contact hole 191 formed with respect to the first interlayer insulating film 16 and the gate insulating film 14, and a second contact hole 19 at a position corresponding to the lower contact hole 191. And an upper contact hole 192 formed in the interlayer insulating film 18.
[0076]
In this example, a metal layer 30 formed simultaneously with the metal forming the data line 3 is left at the bottom of the second contact hole 19 in a state of being insulated and separated from the data line 3. The first pixel electrode 62N and the second pixel electrode 62P are electrically connected to the drain region 12 via the metal layer 30.
[0077]
In the active matrix substrate 2 configured as described above, the first pixel electrode 62N and the second pixel electrode 62P are electrically connected to the drain region 12 via the metal layer 30 remaining inside the second contact hole 19. Therefore, the problem that the connection resistance generated when the silicon film (drain region 12) and the ITO film are directly electrically connected can be solved.
[0078]
Further, in the active matrix substrate 2 of the present example, since the first pixel electrode 62N and the second pixel electrode 62P are in the upper layer, the alignment of the liquid crystal can be effectively controlled. Moreover, since the data line 3 is covered with the second interlayer insulating film 18, the potential applied to the data line 3 does not affect the orientation of the liquid crystal, so that the display quality is high.
[0079]
Furthermore, since the formation region of the data line 3 is used as the formation region of the TFT as it is, the opening can be expanded by the region occupied by the TFT in the conventional structure, and the display quality is also improved from this point. . Furthermore, since the data line 3 covers the entire TFT formation region, light from the channel region 13, the boundary between the source region 11 and the channel region 13, and the boundary between the drain region 12 and the channel region 13 is emitted. Display quality is high because there is no leakage.
[0080]
The active matrix substrate 2 of this example having such a configuration can be manufactured by, for example, the following manufacturing method. First, a normal manufacturing process is performed until the first interlayer insulating film 16 is formed. After the first interlayer insulating film 16 is formed, first, the first interlayer insulating film 16 and the gate insulating film 14 are formed. On the other hand, a lower contact hole 191 and a first contact hole 17 are formed, and thereafter, an aluminum layer for forming the data line 3 is formed on the surface of the first interlayer insulating film 16.
[0081]
Next, when patterning the aluminum layer, the metal layer 30 is left in a state of being insulated and separated from the data line 3.
[0082]
Next, after forming the second interlayer insulating film 18, an upper contact hole 192 is formed in the second interlayer insulating film 18 at a position corresponding to the lower contact hole 191.
[0083]
Thereafter, an ITO layer is formed on the surface of the second interlayer insulating film 18, and then patterned to form a first pixel electrode 62N and a second pixel electrode 62P.
[0084]
[Modification of Embodiment 4]
In the fourth embodiment, a TFT having a structure shown in FIGS. 11A and 11B can be used instead of the TFT having a structure shown in FIGS. 10A and 10B. That is, in this example, the source region 11 electrically connected to the data line 3 and the drain region 12 electrically connected to the pixel electrode 19 are formed on the substrate 20 in both the N-type TFT 10N and the P-type TFT 10P. , A channel region 13 for forming a channel between the drain region 12 and the source region 11, and a gate electrode 15 opposed to the channel region 13 via a gate insulating film 14. , And has the same structure as the conventional TFT in that it is configured as a part of the gate line 4.
[0085]
However, in this example, a first interlayer insulating film 16 is formed on the gate electrode 15, and the data line 3 formed on the first interlayer insulating film 16 is formed on the first interlayer insulating film 16. It is electrically connected to the source region 11 via a contact hole 17 formed in the gate insulating film 16 and the gate insulating film 14. In addition, a second interlayer insulating film 18 is formed on the data line 3, and the first pixel electrode 62 </ b> N and the second pixel electrode 62 </ b> P formed on the second interlayer insulating film 18 are It is electrically connected to the drain region 12 through a second contact hole 19 formed in the second interlayer insulating film 18, the first interlayer insulating film 16, and the gate insulating film 14.
[0086]
Here, the second contact hole 19 has a lower contact hole 191 formed with respect to the first interlayer insulating film 16 and the gate insulating film 14, and a second contact hole 19 at a position corresponding to the lower contact hole 191. And an upper contact hole 192 formed in the interlayer insulating film 18. In addition, a region corresponding to the second contact hole 19 is a window opening region 130 where the data line 3 does not exist.
[0087]
Also in the active matrix substrate 2 configured as described above, since the first and second pixel electrodes 62N and 62P are in the upper layer, the alignment of the liquid crystal can be effectively controlled. Further, since the data line 3 is covered with the second interlayer insulating film 18, the potential applied to the data line 3 does not affect the alignment of the liquid crystal. Furthermore, since the formation region of the data line 3 is used as the formation region of the TFT as it is, the opening can be expanded by the region occupied by the TFT in the conventional structure, and the display quality is also improved from this point. . Furthermore, since the data line 3 covers substantially the entire TFT formation region, the data line 3 extends from the boundary between the channel region 13, the source region 11 and the channel region 13, and the boundary between the drain region 12 and the channel region 13. Since there is no light leakage, the display quality is high.
[0088]
The active matrix substrate 2 of this example having such a configuration can be manufactured by, for example, the following manufacturing method. First, a normal manufacturing process is performed until the first interlayer insulating film 16 is formed. After the first interlayer insulating film 16 is formed, first, the first interlayer insulating film 16 and the gate insulating film 14 are formed. On the other hand, a lower contact hole 191 and a first contact hole 17 are formed, and thereafter, an aluminum layer for forming the data line 3 is formed on the surface of the first interlayer insulating film 16.
[0089]
Next, the data line 3 is left by patterning the aluminum layer. At this time, a window opening region 130 for the data line 3 is formed in a region corresponding to the lower contact hole 191 and the upper contact hole 192.
[0090]
Next, after forming the second interlayer insulating film 18, an upper contact hole 192 is formed in the second interlayer insulating film 18 at a position corresponding to the lower contact hole 191.
[0091]
Thereafter, an ITO layer is formed on the surface of the second interlayer insulating film 18, and then patterned to form a first pixel electrode 62N and a second pixel electrode 62P.
[0092]
[Other Examples]
In the first to fourth embodiments, a liquid crystal display device having a high viewing angle can be realized by changing the rubbing direction between each pixel electrode by utilizing the fact that each pixel has two pixel electrodes. Good.
[0093]
【The invention's effect】
As described above, in the active matrix substrate of the liquid crystal display device according to the present invention, the intersection between the data line formed on the substrate and the first gate line and the intersection between the data line and the second gate line are provided. And a pixel driven by a first gate line and a second gate line, and a pixel electrode connected to the TFT are provided for each of the pixels. Therefore, the two TFTs are turned on at the same timing, and the same image information is written in each liquid crystal cell. Therefore, even if one of the TFTs has an abnormal operation, image information is written to the liquid crystal cell via the normally operating TFT. Therefore, according to the present invention, a fatal display defect does not occur. Further, even if push-down and push-up occur in the two liquid crystal cells, they cancel each other out, so that display disturbance such as flicker does not occur even if the potential of the counter electrode is not shifted from the center level of the image signal. Furthermore, even if a complementary TFT is formed in one pixel region, the number of manufacturing steps can be reduced by forming the TFT in the pixel region in the driver portion on the same substrate by using the process of forming the CMOS circuit as it is. Will not Increase.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating an equivalent circuit of an active matrix substrate of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a scan driver circuit configured on the active matrix substrate shown in FIG.
FIG. 3A is an enlarged explanatory view showing one of the pixels formed on the active matrix substrate shown in FIG. 1, and FIG. 3B is a waveform diagram of a gate signal for driving the pixel; is there.
FIG. 4 is an explanatory diagram showing, on an enlarged scale, pixels formed on an active matrix substrate of a liquid crystal display device according to a modification of the first embodiment of the present invention.
FIG. 5 is an explanatory diagram showing an equivalent circuit of an active matrix substrate of a liquid crystal display device according to a second embodiment of the present invention.
6 (a) is an enlarged explanatory diagram showing a pixel formed on the active matrix substrate shown in FIG. 5, and FIG. 6 (b) is a waveform diagram of a gate signal and the like for driving this pixel.
FIG. 7 is an explanatory diagram showing an equivalent circuit of an active matrix substrate of a liquid crystal display device according to a third embodiment of the present invention.
8A is an explanatory diagram showing an enlarged view of a pixel formed on the active matrix substrate shown in FIG. 7, FIG. 8B is a waveform diagram of a gate signal for driving the pixel, and FIG. FIG. 9 is a waveform diagram of another gate signal.
FIG. 9 is an explanatory diagram showing, on an enlarged scale, one of pixels formed on an active matrix substrate of a liquid crystal display device according to Example 4 of the present invention.
10A is a plan view of a TFT formed in a pixel of the active matrix substrate shown in FIG. 9, and FIG. 10B is a cross-sectional view thereof.
11A is a plan view of a TFT configured as a pixel of an active matrix substrate according to a modification of the fourth embodiment, and FIG. 11B is a cross-sectional view thereof.
FIG. 12 is an explanatory diagram showing an equivalent circuit of a conventional active matrix substrate.
FIG. 13 is a cross-sectional view of a TFT configured as a pixel on a conventional active matrix substrate.
FIG. 14 is a plan view showing a pixel region of a conventional active matrix substrate.
FIG. 15 is an explanatory diagram showing a driving method in a conventional active matrix substrate.
[Explanation of symbols]
1 ... Liquid crystal display device
2 Active matrix substrate
3 ... data line
4 ... Gate line
5, 51, 52, 53 ... pixel area
10N ... N-type TFT
10P ... P-type TFT
11 ... source area
12 ... Drain region
13 ... channel formation region
14 ... Gate insulating film
15 ... Gate electrode
16 first interlayer insulating film
17 First contact hole
18 second interlayer insulating film
19: second contact hole
30 ... Metal layer in contact hole
32N: first liquid crystal cell
32P ... second liquid crystal cell
42N: first data line
42P... First data line
62N: first liquid crystal cell
62P: Second liquid crystal cell
83N ... non-inverting circuit
83P ··· Inverting circuit
92N: first storage capacity
92P: second storage capacity
130: Data line window opening area
191 ・ ・ ・ Lower contact hole
192 ··· Upper contact hole

Claims (11)

One pixel corresponds to an intersection between a data line formed on a substrate and a first gate line, and two intersections formed from intersections between the data line and a second gate line. For each of the
An N-type thin film transistor driven by a first gate signal applied from the first gate line and having a source region electrically connected to the data line, and a first electrically connected to a drain region of the N-type thin film transistor A second gate signal electrically connected to the pixel electrode and the same data line as the N-type thin film transistor, applied from the second gate line, and having an inverse relationship to the first gate signal; A P-type thin film transistor driven together with the N-type thin film transistor, and a second pixel electrode electrically connected to a drain region of the P-type thin film transistor,
An active matrix substrate, wherein the N-type thin film transistor and the P-type thin film transistor are turned on / off at the same timing. 2. The device according to claim 1, wherein the first pixel electrode includes a first storage capacitor between the first pixel electrode and the second gate line corresponding to an adjacent pixel, and the second pixel electrode corresponds to an adjacent pixel. An active matrix substrate comprising a storage capacitor between the active matrix substrate and the first gate line. 2. The pixel according to claim 1, wherein, for each of the pixels, a first storage capacitor line that forms a first storage capacitor between the first pixel electrode and a second storage capacitor line, An active matrix substrate, comprising: a second storage capacitor line forming a storage capacitor. 4. The method according to claim 3, wherein the first storage capacitor line supplies a signal having the same phase and opposite polarity as the first gate signal for driving the N-type thin film transistor of a pixel corresponding to the storage capacitor line, The second storage capacitor line is configured to supply a signal having the same phase and opposite polarity as the second gate signal for driving the P-type thin film transistor of the pixel corresponding to the storage capacitor line. An active matrix substrate, characterized in that: One pixel corresponds to an intersection between a data line formed on a substrate and a first gate line, and two intersections formed from intersections between the data line and a second gate line. For each of the
An N-type thin film transistor driven by a first gate signal applied from the first gate line and having a source region electrically connected to the data line, and a first electrically connected to a drain region of the N-type thin film transistor A pixel electrode, a P-type thin film transistor having a source region electrically connected to the same data line as the N-type thin film transistor, and driven together with the N-type thin film transistor by a second gate signal applied from the second gate line; A second pixel electrode electrically connected to a drain region of the P-type thin film transistor;
The first pixel electrode includes a first storage capacitor between the first pixel electrode and the second gate line for driving the P-type thin film transistor of a pixel to which the pixel electrode belongs. An active matrix substrate comprising a second storage capacitor between the pixel electrode and a first gate line for driving the N-type thin film transistor of a pixel to which the pixel electrode belongs. 6. The data line according to claim 1, wherein the first pixel electrode extends in a pixel region in each of the pixels in a direction in which the first gate line and the second gate line extend. An active matrix substrate, wherein the active matrix substrate is configured to be divided into a first pixel region where the first pixel electrode is located and a second pixel region where the first pixel electrode is located. 7. The active matrix substrate according to claim 6, wherein in each of the pixels, a formation region of the first thin film transistor and a formation region of the second thin film transistor are included in a formation region of the data line. 9. The semiconductor device according to claim 7, wherein the first thin film transistor and the second thin film transistor have a channel region connecting a source region and a drain region, a gate electrode facing the channel region via a gate insulating film, A first interlayer insulating film formed above the gate electrode, and the data line formed above the first interlayer insulating film are connected to the source via the first interlayer insulating film and the gate insulating film. A first contact hole for electrical connection to a region, a second interlayer insulating film formed on the data line, and the first pixel formed on the second interlayer insulating film A second contact hole for electrically connecting an electrode and the second pixel electrode to the drain region via the second interlayer insulating film, the first interlayer insulating film, and the gate insulating film; Active matrix substrate and having and. 9. The device according to claim 8, wherein the second contact hole is a lower contact hole formed in the first interlayer insulating film and the gate insulating film, and the second contact hole is located at a position corresponding to the lower contact hole. And an upper-stage contact hole formed in the interlayer insulating film, and inside the lower-stage contact hole, a metal layer constituting the data line is left in a state of being insulated and separated from the data line. An active matrix substrate, wherein the first pixel electrode and the second pixel electrode are electrically connected to the drain region via a metal layer. 9. The device according to claim 8, wherein the second contact hole is a lower contact hole formed in the first interlayer insulating film and the gate insulating film, and the second contact hole is located at a position corresponding to the lower contact hole. An active matrix substrate comprising: an upper-stage contact hole formed in an interlayer insulating film of (1), wherein a region corresponding to the upper-stage contact hole is a window opening region of the data line. A liquid crystal display device using the active matrix substrate defined in any one of claims 1 to 10.

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