JP3547411B2 - Storage system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage system including a storage control device that controls a storage device such as a magnetic disk device, a magnetic tape device, a semiconductor storage device, or an optical disk device connected to a large-scale computer system or a network system. The present invention relates to a storage system that has high expandability of the system and is capable of performing degraded operation and hot-swap.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a storage system connected to a large-sized computer, for example, an interface (host adapter) for a higher-level device (CPU), a cache memory, a magnetic disk device, etc. There is known a device in which interfaces (disk adapters) to the storage devices are connected by a hot line (dedicated line).
[0003]
FIG. 20 is a diagram showing an outline of a configuration of a conventional storage system. In the figure, reference numerals 201-1 to 201n denote host adapters (upper logical modules) connected to a plurality of higher-level hosts (CPUs), respectively, and reference numerals 202-1 to 202-n connect to a shared large disk device 205. A disk adapter (storage medium connection logical module) 203 is a cache memory shared by a plurality of host adapters, and 206 is a shared management memory similarly. In the conventional device, management is performed between each host adapter 201-1 to 201-n and the cache memory 203, between the cache memory 203 and each disk adapter 202-1 to 202-n, and between each host adapter 201-1 to 201-n. The hot lines 207-1 to 207-n and 208-1 to 208-n are connected to each other between the memories 206 and between the management memory 206 and each of the disk adapters 201-2 to 201-n. A maintenance processor (SVP, not shown) for monitoring and maintaining these host adapters and disk adapters is also connected to each host adapter and disk adapter via a dedicated line.
[0004]
[Problems to be solved by the invention]
In the above prior art, a hot line is connected between a host adapter (upstream connection logical module) for a host device, a disk adapter (storage medium connection logic module) for a storage device, and a cache memory (cache memory module). As a result, the device configuration becomes complicated, and a so-called scalable (expandable and contractible) system configuration such as a host adapter, a cache memory, a disk adapter, a disk device, and the like, having poor expandability as a device, cannot be obtained. In addition, by multiplexing the system, degraded operation (such as stopping one of the two units and operating with only one other unit) or hot-swapping (for example, when the system is running) No consideration has been given to making it possible to replace circuit components, etc.). Therefore, when replacing a component in the event of a failure or upgrading the system control program, the system must be temporarily stopped to respond. There was a problem that had to be done.
[0005]
Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art and adopt a common bus system, so that each logical module such as a host adapter and a storage device adapter, a cache memory, and a storage device according to the system configuration (scale). A scalable system can be realized by connecting media, and multiplexing of each logical module, storage medium and common bus enables degeneration operation and hot swapping of each logical module and storage medium. Another object of the present invention is to provide a storage system that can be maintained without interruption.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention mainly employs the following configuration.
An upper connection logic device connected to a higher device and constituting an interface to the higher device;
A storage device for storing information transferred from the higher-level device,
A storage device-side connection logic device connected to the storage device and constituting an interface to the storage device;
A cache memory for temporarily storing data transferred between the upper connection logic and the storage connection logic, a cache memory for temporarily storing data transferred between the upper connection logic and the storage connection logic and the cache memory; A cache memory device having a shared memory for storing control information for
A multiprocessor bus connected to the upper connection logic device, the storage device connection logic device, and the shared memory for transferring control information, the upper connection logic device and the storage device connection logic; Two I / O buses connected to the device, the cache memory, and the shared memory, for performing data transfer between the upper connection logic device, the storage device connection logic device, and the cache memory device; And a common bus,
A storage system having
When a failure occurs in the multiprocessor bus, control information is transferred on one of the two I / O buses, and data is transferred on the other I / O bus.
If a failure occurs in one of the two I / O buses, data transfer is performed on the remaining I / O buses,
Information indicating the degraded operation status at the time of occurrence of the failure is written in the shared memory that stores the control information.
[0007]
According to the present invention, a plurality of upper connection logic devices constituting an interface to an upper device, a storage device, a plurality of storage device connection logic devices constituting an interface to the storage device, and A cache memory device (a cache memory device shared by a plurality of upper connection logic devices and a plurality of storage device connection logic devices) for temporarily storing data transferred by The connection logic device, the plurality of storage connection logic devices, and the cache memory device are configured to be connected to each other by a common bus shared by these devices, so that the upper connection logic device and the storage device connection logic device are connected. And adding or changing cache memory simply add or change these on the common bus In good, it can be upgraded by adding get easily achieved can scalable system configuration.
[0008]
Further, since these upper connection logic device, storage device connection logic device, and cache memory device are modularized and attached to a platter provided with a common bus so as to be freely inserted and removed (detachable), these devices are provided. It is easy to increase the required number of units.
[0009]
In addition, the upper connection logic device, the storage device connection logic device, the cache memory device, and the common bus connecting these devices are duplicated and wired in two systems. Even when a failure occurs in one of these devices, degenerate operation can be performed using the other device. Note that information indicating the degraded operation status at the time of occurrence of a failure is written to the shared memory.
[0010]
In this case, the upper-level connection logical device, the storage-device-side logical device, and the cache memory device all have connectors for hot-swapping, so that maintenance and inspection can be performed without stopping the system for failure. It is possible to replace parts or add additional parts.
[0011]
The cache memory device is composed of a cache memory module (cache memory package) directly attached to a common bus and an additional cache unit, and the additional cache unit is an additional cache port directly attachable to and removable from the common bus. Since the required number of connections are made via the package, the number can be easily increased or decreased.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0013]
FIG. 1 shows a conceptual diagram of the present invention. An outline of the present embodiment will be described with reference to FIG.
[0014]
1 is a host adapter unit which is a logic module for connection to a host CPU (host), 2 is a disk adapter unit which is a logic module for connection to a storage medium, and 3 is a memory for temporarily storing data transferred between both modules. A cache memory package (cache memory module), 4 is a common bus for controlling data transfer between the host adapter 1, disk adapter 2, and cache memory package 3, and 5 is a group of magnetic disks as storage media arranged vertically and horizontally in an array. (Hereinafter referred to as “array disk”). The host adapter 1 has means for converting the data format and address format on the upper interface side into the data format and address format for the storage medium interface, and a duplicated microprocessor for controlling and managing these. The disk adapter 2 has an address calculation function for storing data in a storage medium, a function for generating redundant data for guaranteeing storage data, a function for recognizing storage medium configuration information, and a microprocessor for controlling and managing these. are doing.
[0015]
In FIG. 1, write data sent from a higher-level device (CPU) is written once to a cache memory package 3 from a host adapter 1 via a common bus 4 to report an end to a higher-level device. Data is written from the package 3 to the array disk 5 via the disk adapter 2.
[0016]
Also, in response to a data read command from the host device, if data exists on the cache memory package 3, the data on the cache memory package 3 is not read from the array disk 5, but is transferred to the host device. On the other hand, if there is no data on the cache memory package 3, the data is once written into the cache memory package 3 from the array disk 5 by the disk adapter 2 via the common bus 4 and then similarly to the host device via the host adapter 1. Forward.
[0017]
The number of host adapters 1, disk adapters 2, and cache memory packages 3 on the common bus 4 can be arbitrarily changed. If the number of mounted host adapters 1 is changed, the number of paths connected to the host changes, and the data transfer capability to the host can be increased. If the number of mounted disk adapters 2 is changed, the number of paths connected to the storage medium changes, and the transfer capability of writing / reading data to / from the storage medium can be increased. At the same time, the number of storage media can be increased. If the number of mounted cache memory packages 3 is changed, the capacity of the cache memory, which is a temporary data storage location, changes, and the ratio of the capacity of the cache memory to the total capacity of the storage medium can be increased. It is possible to realize a scalable device configuration such as increasing the probability that data exists in the cache memory (hereinafter referred to as “cache hit ratio”).
[0018]
FIG. 2 shows a detailed configuration diagram of the conceptual diagram of FIG. FIG. 2 shows only one of each of the plurality of host adapters and the plurality of disk adapters in FIG. 1 and omits the others.
[0019]
In the host adapter 1, reference numeral 6 denotes a signal conversion unit for converting an optical signal of the host interface into an electric signal, and reference numeral 7 denotes a format conversion unit for converting an upper data format into a format for the array disk 5. Reference numeral 8 denotes a data transfer control unit which controls the transfer of data to and from the common bus 4, and has a built-in storage buffer for storing data in packet transfer units. Reference numeral 9 denotes a small-amplitude current-driven bus driver (hereinafter, referred to as "BTL") capable of hot-swapping.
[0020]
The data transfer request from the host is taken over by ten microprocessors (hereinafter, referred to as “MP”), and data transfer control in the host adapter 1 is performed under the management of the MP10.
[0021]
The MP10 is duplicated to ensure high reliability, for example, by detecting a fault occurrence in the MP. The 11 checker units compare and check the duplicated MP10 and MP10 'that perform the same operation. .
[0022]
Reference numeral 12 denotes a boot device for storing a control program of the MP 10. The boot device 12 employs a rewritable large-capacity flash memory, and the MP 10 copies the control program to a local memory 13 as needed. The memory access time of the MP10 can be shortened by using the channel adapter module 29 in a portion surrounded by a broken line in the figure. The host adapter 1 has two modules 29 mounted thereon. is there.
[0023]
In the disk adapter 2, 14 is a buffer memory for storing data to be written to the array disk in sector units, 15 is a data control buffer unit for controlling the buffer memory 14 and controlling data transfer, and 16 is assuring data to be written to the array disk 5. And a redundant data generation unit 17 for generating redundant data for use as an initiator (SCSI master side interface) for the array disk 5 (target).
[0024]
The data transfer control in the disk adapter 2 is performed in the MP peripheral section having the same configuration as that of the host adapter 1 (including the MP 10, MP 10 ', the checker 11, the boot device 12, and the local memory 13 and mounting a control program for the disk adapter). It is performed under the control of.
[0025]
Although only four disks (targets) are shown in FIG. 2 for the array disk 5, actually, for example, 4 (horizontal) × 4 (vertical) to 4 (horizontal) × 7 (vertical) for one disk adapter 2. ) Consists of two disks. The rows form an ECC group (Error Correction Group), and each ECC group includes, for example, three data disks and one parity disk. Further, as will be described later, a set of such array disks 5 can be accessed by a certain CPU through a duplicated host adapter and a duplicated disk adapter. When a failure occurs in one of the host adapters, the same CPU can access the same array disk through the other host adapter or the other disk adapter.
[0026]
In the cache memory package 3, reference numeral 18 denotes a shared memory unit that can be commonly accessed by the MPs 10 of the respective adapters and stores various management information; 19, a shared memory control unit; 20, a cache memory unit; and 21, a cache memory control unit. Each of the memory control units 19 and 21 has a built-in ECC generation circuit for guaranteeing memory write data, a read data inspection and correction circuit, and realizes a maximum cache capacity of 1 GB in the entire cache memory package 3. In terms of configuration, it is mounted in two planes.
[0027]
In order to further increase the cache memory capacity, a cache port package indicated by 22 is mounted instead of (or in addition to) the cache memory package 3 and a connection cable 23 between platters (substrate insertion plate) (That is, the cache memory in the extension unit 24 is configured to be accessible via the cache port package 22 and the cable 23), whereby up to a maximum of 8 GB2 The cache capacity can be increased. FIG. 2 shows a case where, in addition to the two cache memory packages 2 provided, a cache port package 22 is mounted, and several cache units 24 are connected thereto via cables 24.
[0028]
The host adapter 1, disk adapter 2, and cache memory package 3 described above are connected via a common bus 4. In this common bus, reference numeral 25 denotes a multiprocessor bus (hereinafter referred to as "multiprocessor bus") for the MP 10 of each adapter to access the shared memory. Reference numeral 26 denotes a high-speed I / O bus (hereinafter, referred to as an "F bus") for performing high-speed data transfer.
[0029]
The high-speed I / O bus 26 normally operates simultaneously in two systems with a width of 64 bits. However, when a failure occurs, the degeneration operation can be performed by only one of the two systems, and when a failure occurs in the M bus 25. Can operate using either one of the F buses 26.
[0030]
In addition, the BTL 9 that is compatible with hot-swapping (by inserting / extracting while inserting / extracting components with a reduced load on the components to be inserted / extracted while the system is operating) is used as the interface of the common bus 4 so that the host adapter can be used. If a failure occurs in the system disk 1, the system automatically closes the failed path and continues to access the array disk 5 from the host (the same CPU) using the path of another host adapter. The maintenance staff removes the failed host adapter 1 in the system operation state, inserts the normal host adapter 1 into the system, and recovers the data from the 27 maintenance processor (hereinafter referred to as “SVP”) via the 28 LAN. By giving an instruction, the system checks the operation of the replaced host adapter 1 and, if normal, restores the closed path, thereby realizing non-stop operation. Note that LANC in the figure is a LAN Controller (SVP interface controller). The SVP 27 is similarly connected to other host adapters and disk adapters so that monitoring and maintenance are performed.
[0031]
If there is a change in the control program of each adapter, a non-stop upgrade is possible by rewriting the contents of the control program in the boot device 12 from the SVP 27 via the LAN 28.
[0032]
That is, when upgrading the control program of the system, first, each module of the host adapter / disk adapter is closed one by one, and the control program is upgraded and reconnected. By repeating the control program switching operation for each module as described above, the control program of the entire system is switched.
[0033]
FIG. 3 is a diagram showing a data flow and data guarantee along the configuration diagram shown in FIG.
[0034]
When data is written to the array disk from the upper level, for example, first, physical address information (hereinafter, referred to as “PA”) on the write destination storage space is sent from ESCON (trade name of an optical channel, IBM Corporation), Data (CKD (Count Key Data) format) + CRC code is sent. These optical signals are converted into an electrical signal by the signal conversion unit 6 and a parity is generated. The format conversion unit 7 converts the data format into an FBA (Fired Blocked Architecture) format and an LRC (Longitudinal Redundancy Check, longitudinal redundancy). Check) code is added, PA is taken in as a part of data, and a logical address (hereinafter, referred to as “LA”) on the array disk is generated. Sent to
[0035]
In the cache package 3, an error-correctable ECC is added to the data from the F bus 26 and the data is written to the cache memory 20.
[0036]
In the disk adapter 2, a CRC code is further added to the data from the F bus, sent to the array disk 5 via the data SCSI interface, and ECC is added to each magnetic disk device to guarantee the write data. I have.
[0037]
Similarly, when reading data from the array disk 5, the read data is inspected / corrected based on each check code to improve reliability.
[0038]
As described above, the check code is duplicated by a horizontal check for each length in the data length direction and a vertical check (for example, in byte units) for the vertical (width) direction of the data. In addition, between the areas where transfer is performed (indicated by a dashed line in the figure), one of the duplicated check codes is always transferred as data to ensure data security.
[0039]
FIG. 4 is an external view of an apparatus for realizing the scalability described in FIG. 1. Reference numeral 41 denotes a control unit for controlling an array disk. Reference numeral 42 denotes an array unit for mounting an array disk. It consists of.
[0040]
5A and 5B are mounting diagrams of the control unit 41, wherein FIG. 5A is a front view and FIG. 5B is a side view. 51 is a logical frame for mounting the host adapter 1, disk adapter 2, and cache memory package 3, 52 is a battery for supplying power to the cache memory which is a volatile memory at the time of power failure, 53 is the cache unit 24 and A cache memory expansion unit for mounting an additional battery for an additional memory, 54 is an SVP mounting unit, 55 is a switching power supply for a logical rack that supplies power to a logical rack, and 56 is a switch when the configuration (capacity) of the array disk is small. An array disk mounting unit, 57 is an array disk switching power supply for supplying power to the array disk unit, and 58 is a commercial power supply control unit for supplying power to both switching power supplies 55, 57.
[0041]
FIGS. 6A and 6B are mounting views of an array unit portion when a large-capacity array disk is configured. FIG. 6A is a front view, and FIG. 6B is a side view.
[0042]
The array disk mounting section 56 can mount a maximum of 112 magnetic disk devices (8 rows × 7 columns × 2). In order to facilitate replacement of devices when a failure occurs in each magnetic disk device, the array disk mounting section 56 has a front surface. And a mounting method that allows insertion and removal from both sides of the back.
[0043]
Reference numeral 61 denotes a cooling fan for releasing heat generated by the entire unit. The cooling fan 61 has a structure in which the cooling effect is enhanced, and a small cooling fan is used to reduce the noise from the viewpoint of noise suppression, and the air is sent from the floor to the ceiling.
[0044]
FIG. 7 is a connection system diagram of the logical frame unit described in FIG.
[0045]
Reference numeral 71 denotes a platter (a board for inserting a board) on which the common bus 4 is printed and wired, and reference numeral 72 denotes a connector for connecting each of the adapters and packages to the platter 71.
[0046]
Since data transfer between the host adapter 1, the disk adapter 2 and the cache memory package 3 is performed via the common bus 4, each adapter and package can be connected at any arbitrary position on the connector 72. , The number of mounted disk adapters 2 can be changed freely.
[0047]
On the other hand, when increasing the cache capacity, the cache memory package 3 is replaced with the cache port package 22 and mounted, or as shown in FIG. By connecting the cache unit 43 to the cache unit 43 (corresponding to 24 in FIG. 2) via the connection cable 23, the cache memory capacity for a maximum of 8GB2 planes can be further expanded in addition to the original 2GB capacity.
[0048]
FIG. 8 is a mounting image diagram of the logical frame shown in FIG.
[0049]
In FIG. 8, the common bus 4 is printed on the platter 71 in the left-right direction. The mounting portion of the board (CP) of the cache port package 22 and the board (C) of the cache memory package 3 are attached to the platter 71. , A host adapter module board (H) mounting section, and a disk adapter module board (D) mounting section. As shown by arrows 84 in FIG. It is designed to be attached and detached, and is electrically connected to the common bus 4 when inserted into the platter 71.
[0050]
Reference numeral 81 denotes an optical connector unit mounted on the lower part of the host adapter 1 on the board and controls the upper interface, and reference numeral 82 denotes a SCSI connector mounted on the lower part of the disk adapter 2 on the board and connected to the array disk 5. Reference numeral 83 denotes a connection connector for the connection cable 23 when the cache port package 22 is mounted. Reference numeral 85 denotes a cache memory body (the cache memory 20 in FIG. 2) attached to a lower portion of the substrate (C) of the cache memory package 3.
[0051]
In order to improve the operability when inserting and removing each adapter and package in the event of a failure or the like, each connector is mounted on the connection side of the platter 71 without being mounted on the operation surface 84, except for the connector 83. ing.
[0052]
FIG. 9 is a diagram showing a software configuration of the present invention.
[0053]
Reference numeral 91 denotes a channel adapter control program (hereinafter referred to as “CHP”) written to the boot device 12 of the host adapter 1. Among the disk adapter control programs written in the boot device 12 of the disk adapter 2, 92 is a disk adapter master control program (hereinafter, referred to as "DMP") that performs processing unique to the array disk and data transfer control between the cache memory and the array disk. ) And 93 are disk adapter slave control programs (hereinafter, referred to as “DSP”) which are responsible for controlling data transfer between the cache memory 20 and the array disk 5 under the control management of the DMP 92.
[0054]
Although two types of DMP 92 and DSP 93 are written in the boot device 12 of the disk adapter 2, when n sets of disk adapters are used to access an array disk, two sets of them operate as the DMP 92 (duplicate). Then, the remaining n-2 disk adapters operate as the DSP 93.
[0055]
Reference numeral 94 denotes an SVP control program mounted on the SVP 27. The SVP control program monitors and maintains the CHP 91, the DMP 92, and the DSP 93. When each control program is updated, the control program of the MP to be updated is controlled from the SVP 27 directly or from another MP. The program can be updated.
[0056]
FIG. 10 is a diagram showing the function allocation of the software configuration shown in FIG. 9 based on the data flow.
[0057]
The CHP 91 converts the address format and the data format from the upper order into the lower address format and the data format, and writes them into the cache memory. 101 is a segment, 102 is a block, and 103 is a stripe representing the amount of data to be written per magnetic disk on the array disk 5. The DMP 92 reads data from the cache memory in stripe units, converts the lower address into row NO, column NO, FBA, block number of the array disk, and writes the data to the array disk by the DSP 93.
[0058]
The DMP 92 also manages the configuration information of the array disk 5.
[0059]
As described above, by sharing the functions of the respective control programs, when the upper interface is changed to SCSI, Fiber Channel, or the like, only the CHP 91 or the array disk configuration is changed (the number of rows / columns of the disk, RAID (Redundant Array). Inexpensive Disk) method, etc., can be dealt with only by changing the DMP92. Rewriting each control program according to the connection change of the host adapter 1 and the disk adapter 2 realizes scalability and software development. The load of is also reduced.
[0060]
FIG. 11 is a diagram for explaining the concept of duplication of the common bus 4 and the degeneration operation.
[0061]
Reference numeral 111 denotes a bus master (host adapter 1 or disk adapter 2 equipped with the MP 10) that can acquire the right to use the common bus 4, and 112 denotes a bus slave (cache memory package) that receives an access request from the bus master 111.
[0062]
In the normal operation state, the F bus 26 operates two 64-bit buses (200 MB / S) simultaneously to realize 400 MB / S, and each bus system can detect a failure by parity check or timeout. When a failure occurs, the bus master 111 enters a self-degenerate state, accesses the bus slave using the remaining one system, and the degeneration information at this time is registered in the management area on the shared memory 18.
[0063]
In addition, system control signals (bus reset, etc.) in the common bus have tripled signal lines, and three lines match during normal operation and two lines match (decision majority) during degenerate operation to improve reliability. ing.
[0064]
FIG. 12 is a diagram showing multiplexing and degenerate operation in each part of the apparatus.
[0065]
Reference numeral 121 denotes a two-port channel path. The host adapter 1 includes two channel adapters 29 and four upper-level channel paths. When a failure occurs, an alternate channel adapter (CHP) is used. Enter degenerate operation using the channel path.
[0066]
Reference numeral 122 denotes a SCSI path for controlling an interface between the disk adapter 2 and the array disk 5, which is duplicated so that a group of magnetic disks in one row can be accessed from another disk adapter 2; Occurs, a degenerate operation is started using the alternate SCSI path. Further, the DMP 92 for performing the array disk master control is also duplicated, and when a failure occurs, the switching operation is started by using the replacement DMP 92.
[0067]
The shared memory 18 and the cache memory 20 are also duplicated, and if a failure occurs in the shared memory, the remaining memory is used to start the degenerate operation. If a failure occurs in the cache memory, the write pending data (cache memory) is used. The remaining data is destaged to a disk, and a degenerate operation is performed in the memory excluding the memory area where the failure occurred.
[0068]
When a failure occurs in the magnetic disk on the array disk 5, the read / write operation is performed while disconnecting the magnetic disk and restoring the spare magnetic disk.
FIG. 13 is a diagram showing multiplexing and degenerate operation of the power supply system of the apparatus.
[0069]
The commercial power control unit 58 is duplexed with independent AC inputs and supplied to the switching power supply 55 for the logical frame and the switching power supply 57 for the array disk. Therefore, when a failure occurs, the other commercial power control unit 58 is used. To enter degenerate operation.
[0070]
Reference numeral 131 denotes a power supply control circuit (hereinafter, referred to as “PCI”) that controls power supply ON / OFF from a higher-level host, a commercial power supply control unit 58, and a power supply circuit such as both switching power supplies.
[0071]
The switching power supply 55 for a logical frame is mounted for redundant operation by mounting two more circuits than necessary and supplied to the logical frame 51 and the battery 52 via a power supply common bus, so that the switching power supply 55 can operate even if two circuits fail. is there.
[0072]
Similarly, the array disk switching power supply 57 is also provided with two circuits for redundant operation and supplied via the power supply common bus to supply to the magnetic disk group in a column unit. It is operable, and it is possible to finish the switching power supply 55 and 57 in a configuration that is less expensive than duplicating.
[0073]
In the event of a power outage, the redundant battery 52 is supplied to the cache memory, which is a volatile memory in the logical rack, and the PCI 131 via the power supply common bus, and can operate even if one of the batteries fails.
[0074]
FIGS. 14 and 15 are diagrams comparing the system performance when an array disk is configured according to the storage capacity of a single magnetic disk device used for the array disk.
[0075]
FIG. 14 shows a configuration in which array disks of the same capacity are realized by using different magnetic disk devices, respectively, where item 141 is a 3 GB magnetic disk device (using a disk with a 3.5 inch diameter). Item 142 uses a 4.0 GB magnetic disk device (using a 5-inch diameter disk), and item 143 uses a 8.4 GB magnetic disk device (using a 6.4 inch diameter disk). The array configuration is such that the disk device 141 has two parity disks of 14 data disks, the disk device 142 has 14 data disks and 4 parity disks, and the disk device 143 has 14 data disks and 2 parity disks. This is a case where the disk is configured.
[0076]
FIG. 15 shows the relationship between the number of I / O commands issued per second and the average response time for each of the magnetic disk devices 141, 142, and 143. In order to improve transaction performance as an array disk system, a small capacity is required. The use of a (small-diameter) magnetic disk drive to increase the array configuration can bring out the best performance. Therefore, in the present invention, a 3.5-inch magnetic disk drive 141 is used to realize an array disk system. I have. Therefore, when the magnetic disk drive having the same storage capacity is formed by one large magnetic disk drive as in the related art, or by an array of a plurality of small magnetic disk drives, the latter small magnetic disk drive is required. Are more advantageous in that the average access time can be reduced.
[0077]
FIGS. 16 to 19 show examples of device model configurations that can be realized using the scalable architecture described above.
[0078]
FIG. 16 shows a high-performance, large-capacity storage system in which the number of disk adapters 2 mounted on the common bus 4 is reduced, the cache port package 22 is mounted, and the cache unit 24 is connected to the cache unit 24 via the connection cable 23. FIG. 2 is a configuration diagram when a small disk array with a cache memory is realized.
[0079]
When the disk adapter 2 is not mounted and the host adapter 1 and the cache memory alone are used (the configuration in the broken line in the figure), the storage medium is changed from a magnetic disk to a semiconductor memory, and high-speed data transfer is possible. Is realized.
[0080]
FIG. 17 shows a large disk array with a high-performance large-capacity cache memory by maximizing the disk adapter 2 and mounting the cache package 3 or mounting the cache port 22 and connecting the cache unit via the connection cable 23. It is a block diagram at the time of realization.
[0081]
FIG. 18 shows an example in which the host adapter 1 is replaced by an interface such as SCSI / fiber channel, etc., the number of disk adapters 2 is reduced, and the bit width of the F bus 26 is reduced by half to constitute two systems. FIG. 1 is a configuration diagram of a non-stop operation high-performance fault-tolerant (high reliability) server system targeted at an open market.
[0082]
FIG. 19 is a block diagram showing a case where a server system for an inexpensive open market is realized by adopting the simplest configuration based on the configuration of FIG. 18 without considering redundancy and hot swapping. In the drawing, 4D + 1P means that four data disks and one parity disk are used.
[0083]
In the above embodiment, an optical disk device is further connected to the common bus 4 via an optical disk adapter (optical disk connection logic module), and a magnetic tape device is connected via a magnetic tape control device (magnetic disk connection logic module). Alternatively, a semiconductor memory device can be connected via a semiconductor memory device connection logic module. In addition, a workstation can be connected to the common bus 4 via another type of host adapter. Thus, storage media adapters for various types of storage devices can be connected on the common bus.
[0084]
【The invention's effect】
As described in detail above, according to the present invention, a plurality of upper connection logic devices constituting an interface to a higher device, a storage device, and a plurality of storage device connection logic devices constituting an interface to the storage device And a cache memory device for temporarily storing data transferred between these devices (a cache memory device shared by a plurality of upper connection logic devices and a plurality of storage device connection logic devices). The plurality of host-side connection logic devices, the plurality of storage-device-side connection logic devices, and the cache memory device are configured to be mutually connected by a common bus shared by these devices. Expansion or change of the storage side connection logical device and the cache memory is only required for these devices on the common bus. Need only go add or change the can upgrade by adding get easily achieved can scalable system configuration. Further, since these upper connection logic device, storage device connection logic device, and cache memory device are modularized and attached to a platter provided with a common bus so as to be freely inserted and removed (detachable), these devices are provided. This has the effect that the work of increasing the required number of units is easy.
[0085]
Further, since the upper connection logic device, the storage device connection logic device, the cache memory device, and the common bus connecting these devices are duplicated and wired in two systems, one of these devices has a failure. Even when the error occurs, the degenerate operation can be performed using the other device. In this case, the upper-level connection logical device, the storage-device-side logical device, and the cache memory device all have connectors for hot-swapping, so that maintenance and inspection can be performed without stopping the system for failure. There is an effect that it is possible to replace parts or add additional parts.
[0086]
Further, the storage device is an array type in which a plurality of small storage devices are combined, which has the effect that the access time can be reduced as compared with a conventional storage device using one large disk device.
[0087]
The cache memory device includes a cache memory module (cache memory package) directly attached to the common bus and an additional cache unit. The additional cache unit is directly attached to and removable from the common bus. Since the required number of connections are made via the cache port package, the effect of being able to easily increase or decrease is obtained.
[0088]
As described above, a highly reliable storage system can be obtained.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing an outline of an embodiment of the present invention.
FIG. 2 is a detailed configuration diagram of a storage system according to an embodiment of the present invention.
FIG. 3 is a diagram showing a data flow and a data format along the configuration diagram of FIG. 2;
FIG. 4 is an external view of an apparatus according to an embodiment of the present invention.
FIG. 5 is a mounting scheme diagram of a control unit in the apparatus according to the embodiment of the present invention.
FIG. 6 is a mounting system diagram of an array disk unit in the apparatus according to the embodiment of the present invention.
FIG. 7 is a connection system diagram of a logical frame unit in the apparatus according to one embodiment of the present invention.
FIG. 8 is a diagram illustrating a mounting method of a logical frame in the apparatus according to the embodiment of the present invention.
FIG. 9 is a software configuration diagram applied to the embodiment of the present invention.
FIG. 10 is a diagram showing a data flow and software function allocation according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating duplexing and degeneration operations of a common bus according to an embodiment of the present invention.
FIG. 12 is a diagram showing a duplex operation and a degenerate operation of each part of the apparatus according to the embodiment of the present invention.
FIG. 13 is a diagram showing multiplexing and degenerate operation of the power supply system of the device according to the embodiment of the present invention.
FIG. 14 is a diagram showing a disk configuration of a single magnetic disk device used for an array disk.
FIG. 15 is a diagram showing the storage capacity of a magnetic disk device and the system performance of an array disk.
FIG. 16 is a configuration diagram of a small disk array with a high-performance large-capacity cache memory.
FIG. 17 is a configuration diagram of a large disk array with a high-performance large-capacity cache memory.
FIG. 18 is a configuration diagram of a high-performance fault-tolerant server system.
FIG. 19 is a configuration diagram of a low-cost server system.
FIG. 20 is a schematic configuration diagram of a conventional storage system.
[Explanation of symbols]
1 Host adapter
2 disk adapter
3 Cache memory package
4 Common bus
5 Array disk
18 Shared memory
20 cache memory
22 Cache Port Package
24 Additional cache unit
25 Multiprocessor bus
26 High-speed I / O bus

Claims (2)

An upper connection logic device connected to a higher device and constituting an interface to the higher device;
A storage device for storing information transferred from the higher-level device,
A storage device-side connection logic device connected to the storage device and constituting an interface to the storage device;
A cache memory for temporarily storing data transferred between the upper connection logical device and the storage device connection logical device ; a cache memory for temporarily storing data transferred between the upper connection logical device and the storage device side connection logical device; A cache memory device having a shared memory for storing control information for
One multiprocessor bus connected to the upper connection logic, the storage connection logic, and the shared memory for transferring control information; and the upper connection logic and the storage connection logic. Two I / O buses connected to the device, the cache memory, and the shared memory, for performing data transfer between the upper connection logic device, the storage device connection logic device, and the cache memory device ; And a common bus,
A storage system having
When a failure occurs in the multiprocessor bus, control information is transferred on one of the two I / O buses, and data is transferred on the other I / O bus.
If a failure occurs in one of the two I / O buses, data transfer is performed on the remaining I / O buses,
A storage system , wherein information indicating a degraded operation state at the time of occurrence of the failure is written in a shared memory for storing the control information . The I / O bus normally operates two systems of a 64-bit bus (200 MB / S) simultaneously to transfer data at 400 MB / S. 3. The storage system according to claim 1, wherein data transfer is performed in S.

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