JP3234211B2 - Disk array system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a disk array system capable of performing high-performance input / output operations.

[0002]

2. Description of the Related Art In a current computer system, data required by a host such as a CPU is stored in a secondary storage device, and the data is stored in the secondary storage device when the CPU requires it. Writing and reading are being performed. A non-volatile storage medium is generally used as the secondary storage device, and typical examples include a magnetic disk device (hereinafter referred to as a drive) and an optical disk.

In recent years, with the advancement of information, there has been a demand for higher performance secondary storage devices in computer systems. As one solution, a disk array constituted by a number of drives having a relatively small capacity has been considered.

[0004] "D. Patterson, G. Gibson, and RHKartz; A
Case for Redundant Arrays of Inexpensive Disks (RA
ID), in ACM SIGMOD Conference, Chicago, IL, (June198
8) ”, the results of a study on the performance and reliability of a disk array (level 3) that divides data and processes data in parallel and a disk array (level 5) that distributes data and handles data independently are reported. ing. Currently, the method described in this paper is considered to be the most common disk array.

Hereinafter, a description will be given of a disk array (level 5) in which data is distributed and handled independently. Level 5
In this type of disk array, individual data is handled independently without being divided, and the data is distributed and stored in a number of relatively small-capacity drives. At present, in a secondary storage device of a general-purpose large-sized computer system generally used, since the capacity per drive is large, the drive is used for another read / write request, and the drive cannot be used and waits. Many things happened. In this type of disk array, the general-purpose large-scale computer system 2
The large-capacity drive used in the secondary storage device is composed of a large number of relatively small-capacity drives and data is stored in a distributed manner. Read / write requests are reduced due to the distributed processing performed by the other drives. However, since the disk array is composed of such a large number of drives, the number of components increases and the probability of occurrence of a failure increases. Therefore, it is necessary to prepare a parity for the purpose of improving reliability.

This parity makes it possible to restore the data in the failed drive when a failure occurs in the drive storing the data. In a disk array, parity is created from data and stored in a drive in the same way as data. At this time, the parity is stored in a drive different from the data involved in creating the parity.

[0007] In these disk arrays, similar to general-purpose large-sized computer systems generally used today,
In the secondary storage device, the storage location (address) of each data is fixed to an address designated in advance, and when reading or writing the data from the CPU, the fixed address is accessed. I have. In this distributed disk array (level 5),
A product announcement has been made by Storage Technology Corporation (hereinafter referred to as STK). US Patent WO 91
/ 20076, a method of dynamically converting addresses in a track unit in a data writing process by preparing a table of addresses that can be dynamically changed in a level 5 basic architecture. Is disclosed.

Japanese Patent Application Laid-Open No. Hei 4-230512 discloses a method of writing data to be written at the time of writing and parity updated by the writing at different locations in level 5. Further, in the IBM disk array (9337), it has been announced that a WAD (write assist device) is provided at level 5.

[0009]

In a current general-purpose large-scale computer system, etc., in a secondary storage device constituted by a drive, data transferred from a CPU has a storage location (address) of each data in advance. When the data is fixed to a specified address and the CPU reads or writes the data, the CPU accesses the fixed address. This is the same in the disk array. In a disk array in which data is divided and processed in parallel (level 3), fixing addresses in this way has no effect, but in a disk array in which data is distributed and handled independently (level 5), addresses are fixed. Is fixed, a large processing overhead is required at the time of writing. Hereinafter, this will be described.

[0010] FIG. 11 is a data distribution method described in the RAID proposed by D. Patterson et al.
It shows the data address inside the disk array (level 5) that is handled independently. The data at each address is
Each data is independent in a unit of one read / write process. In the architecture described in RAID, addresses for data are fixed. As described above, in such a system, it is essential to set parity in order to improve reliability. In this system, a parity is created by data of the same address in each drive. That is, a parity is created from the data at the address (1, 1) of the drives # 1 to # 4, and is stored in (1, 1) of the drive that stores the parity. In this system,
In the writing process, the data is accessed for each drive as in the current general-purpose large-scale computer system.

In such a disk array, for example, when updating the data at the address (2, 2) of the drive # 3, first, the (2, 2) of the drive # 3 before being updated is updated.
The data of (2) and the parity of (2, 2) of the drive storing the parity are read (1), and an exclusive OR is performed with these and new data to be updated to create a new parity ( 2). After the creation of the parity is completed, the new data to be updated is stored in (2, 2) of the drive # 3, and the new parity is stored in (2, 2) of the drive storing the parity (3).

[0012] As shown in FIG. 12, such level 5
In order to read old data and parity from a drive storing data and a drive storing parity, the disk array waits 平均 of the disk on average, and then reads the parity to create parity. One more rotation is required to write the newly created parity, and at least 1.5 rotations must be waited when rewriting data. In a drive, waiting for the rotation of a 1.5 turn disk is a very large overhead. In order to reduce the overhead at the time of writing, a method of dynamically converting the address of the writing destination has been considered, which is disclosed in WO 91/2076.

Also, in the above-mentioned Japanese Patent Application Laid-Open No. 4-230512, at the time of writing,
A method is disclosed in which write overhead is reduced by writing to an address other than the address where the write data is written. When data to be written is sent from the CPU side, the parity is updated immediately, and the updated parity is written. As described above, in the disk array of level 5, the overhead of generating the parity and writing the generated parity is much larger at the time of writing than at the time of reading.
When there are many read and write requests from the CPU,
This processing overhead is a major cause of performance degradation.

An object of the present invention is to improve the performance of a disk array device of level 5 by reducing the processing overhead during writing.

It is another object of the present invention to effectively use drive resources by using a data restoration spare drive in a failed drive to improve the performance of the apparatus.

[0016]

According to the present invention, a logical group is constituted by a drive constituting a parity group and a drive in a duplex area (space area), and the space area is effectively utilized to achieve high reliability. In addition, the start time of the parity update at the time of writing is delayed while maintaining the parity, and the parity is generated when there is little read or write request from the CPU later.

More specifically, at the time of writing, data to be written (new data) is temporarily stored in the space area in the SCSI drives 12 constituting the logical group 10 in a duplicated manner. At this point, the CPU 1 is notified that the writing process has been completed.

In addition, parity generation and the SCSI
Writing the parity to the drive 12 is performed by writing the new data S
Processing is performed at a timing independent of writing to the CSI drive. Specifically, the MP1 20 of the ADC 2 counts the number of read / write requests from the CPU 1 to the logical group 10 and if the number is smaller than the number set in advance by the user or the system administrator,
Parity is created when no read or write request has been issued to the drive 12, and after the parity has been created, the parity is written to the SCSI drive 12.

As another method of writing the parity, the parity may be written by an interrupt process at fixed time intervals. C in the day
A time zone in which the number of read or write requests from the PU is small or a small day in a month may be predicted and scheduled.

Before the creation of the parity and the writing of the parity to the SCSI drive 12 are completed, any one of the S
If a failure occurs in the CSI drive and data inside the CSI drive cannot be read, the SCSI drive 12 storing data other than the duplicated data is
It is possible to recover the data in the failed SCSI drive 12 from the previous parity and the remaining data, and in the duplicated new data, the data in the non-failed SCSI drive 12 can be recovered. It is possible to recover with new data.

[0021]

According to the present invention, as described above, the writing of data and the creation of parity and the writing to the SCSI drive 12 are made independent from each other, so that there is no overhead from the user (CPU) due to parity creation at the time of writing. This is because the number of read or write requests from the CPU fluctuates over time, so when the number of read or write requests is large, the parity is not updated each time in the write process, and the CPU is not updated when the data write is completed. Reports the end and delays the parity update until a relatively small number of read or write requests. The update of the parity is performed by the disk array controller 2 independently of the CPU side.

For this reason, when viewed from the CPU side, in the conventional disk array (RAID system), as shown in FIG. 12, an average of 1.5 rotation waiting time was required at the time of writing. According to the above, a rotation waiting time of 0.5 rotation on average is sufficient. Further, from the viewpoint of reliability, it is possible to improve the same as compared with the conventional disk array (RAID method).

[0023]

<Embodiment 1> An embodiment of the present invention will now be described with reference to FIG.
This will be described with reference to FIGS. In FIG. 1, the present embodiment includes a CPU 1, a disk array controller (hereinafter, ADC) 2, a disk array unit (hereinafter, ADU) 3,
It consists of. ADU3 has a plurality of logical groups 1
0, each logical group 10 includes m SCSI drives 12 and each SCSI drive 12
And the ADC 2 and drive paths 9-1 to 9-4. The number of the SCSI drives 12 is not particularly limited for obtaining the effects of the present invention. The logical group 10 is a failure recovery unit, and the logical group 10
The parity is created by each data in each SCSI drive 12 in the. In this embodiment, m-1 individual SCSs
Each parity is created from the data in the I drive 12.

Next, the internal structure of the ADC 2 will be described with reference to FIG. The ADC 2 includes a channel path director 5, two clusters 13, and a cache memory 7 which is a non-volatile semiconductor memory such as a battery backup. The cache memory 7 stores data and an address conversion table. The cache memory 7 and the address conversion table therein are used in common by all clusters in the ADC 2. The cluster 13 is a set of paths that can operate independently in the ADC 2, and the power supply and the circuit are completely independent between the clusters 13. The cluster 13 includes a channel path 6 which is a path between the channel and the cache memory 7, and a drive path 8-1 to 8- which is a path between the cache memory 7 and the SCSI drive 12.
4 are each composed of two pieces. Each of the channel paths 6-1 to 6-4 and the drive path 8
It is connected via a cache memory 7. CPU1
The issued command is issued to the channel path director 5 of the ADC 2 through the external interface path 4. The ADC 2 is configured by two clusters 13 and each cluster is configured by two paths. Therefore, the ADC 2 is configured by a total of four paths. Thus, the ADC 2 can simultaneously receive up to four commands from the CPU 1. So, C
When a command is issued from the PU1, the channel path director 5 in the ADC 2 determines whether the command can be accepted.

FIG. 2 shows the channel path director 5 of FIG.
FIG. 3 is a diagram showing an internal structure in one cluster 13-1. As shown in FIG. 2, the command sent from the CPU 1 to the ADC 2 is an interface adapter (hereinafter referred to as I / O).
F Adp) 15 and the microprocessor MP1 20 checks whether there is a usable external interface path 4 among the external interface paths 4 in the cluster.
The P1 20 switches the channel path switch 16 to perform a command accepting process. If the command is not accepted, the P1 20 sends an unacceptable response to the CPU 1.

In this embodiment, the SCS constituting the ADU 3
The I drive 12 uses a drive of the SCSI interface. When the CPU 1 is a large-scale general-purpose computer such as the IBM System 9000 Series, commands are issued from the CPU 1 according to a channel interface command system operable by an IBM operating system (OS). Therefore, when a SCSI interface drive is used as the SCSI drive 12, it is necessary to convert a command from the CPU 1 into a command conforming to the SCSI interface command system. This conversion is roughly divided into protocol conversion of the command and address conversion. Hereinafter, the address conversion will be described.

The address specified by the CPU 1 is shown in FIG.
As shown in FIG. 2, the position of the cylinder to which the track in which the data is stored belongs, the head address for determining the track in which the data is stored in the cylinder, and the position of the record in the track are specified. I do. Specifically, the number of the drive in which the requested data is stored (the drive number designated by the CPU) and the cylinder address (CC) which is the cylinder number in the drive
And a CCHHR comprising a head address (HH), which is the number of a head for selecting a track in the cylinder, and a record address (R).

In a conventional magnetic disk subsystem (IBM 3990-3390) compatible with the CKD format,
The drive may be accessed according to this address.
However, in the present embodiment, a plurality of SCSI drives 12 logically emulate a conventional magnetic disk subsystem compatible with the CKD format. That is, AD
C2 appears to the CPU 1 so that the plurality of SCSI drives 12 correspond to one drive used in a conventional magnetic disk subsystem compatible with the CKD format. Therefore, the MP1 20 converts the address (CCHHR) specified by the CPU 1 into the address of the SCSI drive. This address conversion uses an address conversion table 40 (hereinafter referred to as an address table) as described below.

The cache memory 7 in the ADC 2 stores an address table 40 as shown in FIG. In this embodiment, the drive specified by the CPU 1 is a single drive compatible with the CKD format. However, in the present invention, the drive that the CPU 1 recognizes as a single unit is actually defined by a plurality of SCSI drives 12, and is therefore defined as a logical drive. Therefore, the MP1 20 of the ADC 2
Converts the address (CPU-designated drive number 41 and CCHHR 46) designated by the CPU 1 into the SCSI drive address 42 (SCS
I drive number 43 and its SCSI drive address (hereinafter referred to as SCSI Addr) 44).

The address table 40 includes a CPU designated drive number 41 designated by the CPU 1 and a SCSI drive address 42. The SCSI drive address 42 is an address of the SCSI drive 12 S
The CSI drive number 43 and the SCSI address which is the address where data is actually stored in the SCSI drive
SCSI drive number (parity drive number 50) storing the parity in the parity group determined by the SCSI Addr 44 within the logical group 10, and the SCSI storing the duplex area (space area) in the logical group 10. It is composed of a drive number (space drive number 51). In this address table 40, the logical address 45
Drive number 43 and SCSI Add
Determine r44. Logical group 1 is performed by the SCSI drive 12 of the SCSI drive number 43 registered in the SCSI drive address 42 of the address table 40.
0 is configured.

In the Addr 44 within the same SCSI in the logical group 10, the SC in which parity is stored
The SI drive number 43 is registered in the parity drive number 50, and the SCSI drive number 43 in which the space area is secured is registered in the space drive number 51. The space drive number 51 is constituted by an SD flag 53 in addition to the SCSI drive number for which the space area is secured. The SD flag 53 is turned on (1) when the data stored in the space area is valid and cannot be used as the space area in the write process, and is off (0) when the data is invalid and can be used as the space area.
Becomes The logical group 10 includes a parity group including data and parity associated with the data, and a space area.

The logical address 45 includes a CPU designated drive number 41 which is an address designated by the CPU 1,
If the CCHHR 46 is registered in the CCHHR and the data of the logical address 45 exists in the cache memory 7, the cache address 4 for storing the address of the data in the cache memory 7.
7, a cache flag 48 in which ON (1) is registered when data of the logical address 45 is held in the cache memory 7, and ON when a space area is secured in the logical address 45. An invalid flag 49 which is (1) and a drive flag 52 which is turned on (1) when the write data in the cache memory 7 is written to the drive.

As described above, the CPU-designated drive number 41 and CCHHR 46 are converted into the logical address 45 by the address table 40, and the SCSI drive number 43 where the data is actually stored and the Addr 4 in SCSI.
4 is determined.

For example, in FIG.
Drive # 1, CC as PU designated drive number 41
When the HHR 46 issues a request for ADR8 data, in the address table 40, the CPU-designated drive number 41 checks the CCHHR 46 in each logical address 45 of the Drive # 1 area, and the CCHHR 46 checks the ADR8 logical address 45. look for. In FIG.
As the logical address 45, Data # 23 (D # 23)
CCHHR46 is ADR8, and Data #
23 (D # 23) is the logical address 45.

This Data # 23 (D # 23) is obtained from the address table 40 by using the Addr in SCSI in the SCSI drive 12 of the SCSI interface of SD # 2.
As 44, it is found that it corresponds to DADR8, and it is converted to a physical address. Also, this Data # 23
From the parity drive number 50, the parity corresponding to (D # 23) is the same as that of Data # 23 (D # 23).
SCS of SD # 4 of DADR8 of Addr44 in CSI
Since the SD flag 53 is ON (1) based on the spare drive number 51, the SD #
Data in which the Addr 44 in SCSI Nos. 4 and 5 are duplicated and stored in the DADR 8 is valid, and use of this area as a duplicated area (spare area) is prohibited.

As described above, the address specified by the CPU 1 is converted into the logical address 45, and is converted into the physical address of the SCSI drive 12 for actually reading / writing.
A read or write request is issued to ta # 23 (D # 23). At this time, in the address table 40, the logical address 45 of Data # 23 (D # 23)
Since the cache flag 48 is ON (1), this data exists in the CADRs 2 and 1 in the cache memory 7. If the cache flag 48 is off (0), the data does not exist in the cache memories 7 of the CADRs 2 and 4. This data is invalid flag 4
Since 9 is off (0), this data is valid. Further, since the drive flag 52 is ON (1), this data has already been written from the cache memory 7 to the drive.

The address table 40 is automatically read from the specific SCSI drive 12 in the logical group 10 into the cache memory 7 by the MP 1 20 without the CPU 1 when the system power is turned on. . On the other hand, when the power is turned off, the address table 40 in the cache memory 7 is
Is automatically stored at a predetermined location in the SCSI drive 12 from which the data has been read, without being aware of it.

Next, specific I / O processing in the ADC 2 will be described with reference to FIGS. The command issued from the CPU 1 is sent to the AD
The request is read by C2, and is read by MP1 20 as a read request or a write request. First, a processing method for a read request will be described below.

When the MP1 20 recognizes the read request command, the MP1 20 refers to the address table 40 for the CPU-designated drive number 41 and CCHHR 46 sent from the CPU 1 (both will be referred to as a CPU-designated address). Then, the data is converted into the logical address 45, and the cache flag 48 is checked to determine whether or not the data exists in the cache memory 7 registered at the logical address 45.

When the cache flag 48 is on and stored in the cache memory 7 (cache hit)
Starts the control for reading the data from the cache memory 7 by the MP1 20. If the data is not in the cache memory 7 (cache miss), the control for reading the relevant data from the drive 12 is started.

At the time of a cache hit, the MP1 20 determines from the address table 40
The PU specified address is converted into a logical address 45, and is converted into an address in the cache memory 7 by the cache address 47 in the logical address 45.
To read the data. Specifically, MP12
0, the cache adapter circuit (C Ad
The data is read from the cache memory 7 by p) 24.

The C Adp 24 is a circuit for reading and writing data to and from the cache memory 7 in accordance with the instruction of the MP 120, and for monitoring the state of the cache memory 7 and performing exclusive control on each read and write request. . The data read by the C Adp 24 is transferred to the channel interface circuit (CH IF) 21 under the control of the data control circuit (DCC) 22. The CH IF 21 converts the data into the protocol of the channel interface in the CPU 1 and adjusts the speed to a speed corresponding to the channel interface. Specifically, when the channel interface between the CPU 1 and the ADC 2 is an optical interface, the protocol of the optical interface is converted into a protocol for electrical processing in the ADC 2. After the protocol conversion and the speed adjustment in the CH IF 21, the channel path switch 16 in the channel path director 5 selects the external interface path 4, and transfers data to the CPU 1 by the IF Adp 15.

On the other hand, at the time of a cache miss, the CPU-designated address is converted into the logical address 45 by the address table 40 in the same manner as at the time of the cache hit, and the logical address 45 is used to determine the relevant SCSI drive number and the actual data in the SCSI drive. A in SCSI where is stored
ddr44 is recognized, and MP120
Instructs the Drive IF 28 to issue a read request to the drive 12. Drive
The IF 28 issues a read command via the drive unit path 9-1 or 9-2 according to the SCSI read processing procedure. The SCSI drive 12 to which the read command has been issued from the drive IF 28 performs seek and rotation wait access processing to the specified SCSI Addr 44. The SCS
After the access processing in the I drive 12 is completed, the SCSI drive 12 reads the data and transfers the data to the Drive IF 28 via the drive unit path 9.

The drive IF 28 transfers the transferred data to the cache adapter circuit (C Adp) 14 on the SCSI drive side, and the (C Adp) 1
In step 4, data is stored in the cache memory 7. At this time, the C Adp 14 reports to the MP 1 20 that data is to be stored in the cache memory 7, and the MP 1 20
Turns on the cache flag 48 of the logical address 45 corresponding to the CPU-specified address to which the CPU of the address table 40 has issued the read request based on this report (1).
In the cache address 47, the cache memory 7
Register the address where the data in is stored. After the data is stored in the cache memory 7, the cache flag 48 of the address table 40 is turned on (1), and the address in the cache memory 7 is updated. Then, the data is transferred to the CPU 1 in the same procedure as at the time of the cache hit. I do.

On the other hand, at the time of writing, processing is performed as follows. In the writing process, the user specifies a write destination address (CPU-specified address), and recognizes that the user is writing data at that position. That is, the user recognizes that the address is specified at the fixed position.

From the CPU 1, a designated address, that is,
In the address table 40 shown in FIG. 3, the drive number 41 designated by the CPU is drive # 1 and the CCHHR 46 is A
It is assumed that a write command has been issued to DR8. First, the MP1 20 of the ADC 2 receives the command of the write request to the ADR 8 by the CCHHR 46 of the drive # 1 from the CPU 1, and then receives the command from the MP1.
Each channel path 6 in the cluster 13 to which 1 20 belongs
It is checked whether or not processing is possible, and if possible, a response indicating that processing is possible is returned to the CPU 1. After receiving a response indicating that processing is possible, the CPU 1 transfers data to the ADC 2. At this time, in the ADC 2, the channel path switch 16 in the channel path director 5 connects the external interface path 4 and the IF Adp 15 to the channel path 6 in accordance with the instruction of the MP 1 20,
The connection between the CPU 1 and the ADC 2 is established.

After establishing the connection between CPU 1 and ADC 2, C
Data transfer from PU1 is accepted. Write data transferred from CPU 1 (hereinafter referred to as new data)
Performs the protocol conversion by the CH IF 21 in accordance with the instruction of the MP1 20 and outputs the external interface path 4
The speed is adjusted from the transfer speed in step (2) to the processing speed in ADC2. After the completion of the protocol conversion and the speed control in the CH IF 21, the data is subjected to data transfer control by the DCC 22, transferred to the C Adp 24, and transferred to the C Adp 2
4 is stored in the cache memory 7.

At this time, if the information sent from the CPU 1 is a CPU-specified address, the CPU-specified address is always transferred from the CPU 1 before data is transferred. To convert the address into a logical address 45. If the information sent from the CPU 1 is data, the address stored in the cache memory 7 is registered in the cache address 47 of the logical address 45 converted by the address conversion. At this time, when the write data is held in the cache memory 7, the cache flag 48 of the logical address 45 is turned on (1). When not held, the cache flag 48 is turned off (0).

When a new write request is issued from the CPU 1 to the new data stored in the cache memory 7, the new data stored in the cache memory 7 is rewritten.

For the new data stored in the cache memory 7, the parity is newly updated with the new data (hereinafter, the updated parity is referred to as a new parity), and the SCSI drive 12 in the logical group 10 is updated as follows. To store new data and new parity.

As shown in FIG. 3, the space area and the parity are handled in the same manner as the data, and are distributed and stored in each SCSI drive 12 in the logical group 10. The data in each SCSI drive 12 that constitutes the logical group 10 is written in the row direction (Addr4 in the same SCSI).
4) A parity group is formed, and parity is created for data in the parity group. That is, the parity group is configured by data and parity, and the logical group 10 is configured by the parity group and the space area.

FIG. 3 shows a specific example. SCSI
Of which Addr44 is DADR1, S of SD # 1
Data # 1 (D stored in the CSI drive 12)
# 1), Data # 2 (D # 2) stored in the SCSI drive 12 of SD # 2, and SCSI of SD # 3.
Data # 3 (D # 3) stored in drive 12
Creates a parity. This parity is SD #
6 of the SCSI drives 12, and these constitute a parity group. Further, the logical group 10
The space area (S) secured in the SCSI drive 12 of D # 4, the space area (S) secured in the SCSI drive 12 of SD # 5, and the parity group.

The MP1 20 refers to the address table 40 and recognizes the SCSI drive 12 in which data, space area, and parity are stored. Specifically, in the area corresponding to the CPU-designated drive number 41 specified by the CPU-specified address in the address table 40, the logical address 45 registered in the SCSI drive address 42 that matches the CCHHR 46 specified by the CPU-specified address. MP1 20 looks for MP1
20 is the logical address 45 after the conversion from the CPU-specified address to the logical address 45.
Is the SCSI drive number 43 in which the
SCS which is a physical address in the CSI drive 12
Convert to Addr44 in I.

The parity is stored in each SCSI drive 12 constituting the logical group 10 in each SCSI Add.
r44 is created for the same data, and its parity is also stored in the same Addr 44 in SCSI as the data.
For this reason, in the parity drive number 50 and the space drive number 51 of the address table 40, the parity and the space area indicate the SCs in which the respective areas are stored.
Only the SI drive number 43 is registered. Therefore,
In the MP 1 20, the parity drive number 50 and the space drive number 51 can be determined from the address table 40. That is, by determining the parity drive number 50 and the space drive number 51, the parity and the space area are set to the same S as the data.
Since they are stored in the Addr 44 in the CSI, their addresses are determined. Thus, the SCSI in which the data, the space area, and the parity are stored
After recognizing the drive 12, it instructs the Drive IF 28 to perform a write process on each of the SCSI drives 12.

The write processing in the present invention means that in the logical group 10, new data is actually written from the cache memory 7 to the SCSI drive 12, and parity must be newly created by writing new data. A process of reading data before writing (hereinafter, old data) for generating parity and a parity before writing (hereinafter, referred to as old parity) to create a new parity, and actually writing the new parity after writing to the SC
This refers to a series of processing for writing to the SI drive 12. FIG. 5 shows a flowchart of a series of write processing after storing the new data in the cache memory 7.

As shown in FIG. 4, the CPU 1 sends SD # 1
When a write request for ND # 1 data is issued to the logical address of Data # 1 (D # 1) of the SCSI drive 12, the new data is temporarily stored in the cache memory 7 from the CPU 1 as described above. Is stored. After storing the new data in the cache memory 7, the writing process is performed in the following procedure. New data (N
After D # 1) is stored, the MP1 20 enters a write process, and according to the address table 40, the SC of SD # 1
In the logical group 10 to which the SI drive 12 belongs, Da
D which is Addr44 in SCSI of ta # 1 (D # 1)
SD # for which space area is reserved for ADR1
The use right is acquired for the SCSI drives 12 of 4 and 5.

After obtaining the right to use the SCSI drives 12 of SD # 4 and SD # 5, the write processing 500 is performed as shown in the flowchart of FIG. First, MP1
20 checks the SD flag 53 of the space drive number 51 in the address table 40, and judges that the SD flag 53 can be used as a space area when the SD flag 53 is off (0) and cannot be used when the SD flag 53 is on (1) (502). ). M
P1 20 determines that SD # 4,
It is determined whether a space area is secured in the fifth SCSI drive 12. When the SD flag 53 is off (0), the N stored in the cache memory 7 is
D # 1 is duplicated and written to SD # 4 and SD # 5 (50)
4), MP1 20 reports the completion of writing to CPU 1 (508).

On the other hand, by checking at step 502,
When the SD flag 53 is ON (1), as shown in FIG. 13, after writing new data (ND # 1) to be written to the cache memory 7, the MP1 20 preferentially creates a parity in the previous write processing. Is written to the SCSI drive 12 (131).
0). When the parity creation in the previous write process is completed and the write to the SCSI drive is completed,
The MP 1 20 turns off (0) the SD flag 53 for the space drive number 51 in the address table 40 (1308), and stores the N stored in the cache memory 7.
D # 1 is duplicated and written (1316), MP1 2
0 reports write completion to the CPU 1 (132
0).

Next, a method of writing new data (ND # 1) to the SCSI drive 12 will be described. MP1
After confirming that the SD flag 53 of the address table 40 is off (0), the drive IF 28
New data (ND # 1) which is the data to be written to the SCSI of SD # 4 and SD # 5 in which a space area is secured
Instructs the drive 12 to write. Drive I
In F28, according to the SCSI writing procedure, S is executed via two of the drive unit paths 9-1 to 9-4.
A write command is issued to the SCSI drives 12 of D # 4 and SD # 5.

In the SCSI drive 12 to which the write command has been issued from the Drive IF 28,
e The CPU 1 sent from the IF 28 converts the CPU-specified address specified as the write destination address into the logical address 45, and converts the logical address 45, Data #
The access to the DRDR1 of the Addr 44 in the SCSI corresponding to No. 1 is performed for the seek and rotation wait. SD # 4,5
As soon as the access processing is completed in the SCSI drive 12 and writing becomes possible, the C Adp 14 reads out the new data (ND # 1) to be written from the cache memory 7 and transfers it to the Drive IF 28, whereupon the Drive
The IF 28 transfers the transferred new data (ND # 1) to the SCSI drives 12 of SD # 4 and SD # 5 via two of the drive unit paths 9-1 to 9-4.
When writing of the new data (ND # 1) to the SCSI drives 12 of SD # 4 and SD # 5 is completed, the SCS of SD # 4 and SD # 5 are completed.
The I drive 12 reports the completion to the Drive IF 28, and the Drive IF 28 reports to the MP 120 that the completion report has been received.

At this time, in the address table 40,
Logical address 45 (Data #) of old data before writing
1, D # 1) is turned on (1), and C in the logical address 45 (Data # 1, D # 1) before writing is set.
The address of the CHHR 46 is registered in the CCHHR 46 of the two logical addresses 45 in the space area where the new data (ND # 1) is duplicated and written, the invalid flag is turned off (0), and the drive flag 52 is turned on (1). I do.
Further, new data (ND
When holding the # 1), the address where the new data (ND # 1) in the cache memory 7 is stored is registered in the cache address 47 in the two logical addresses 45 after writing, and the cache flag 48 is set. Turn on (1). If this new data (ND # 1) is not left in the cache memory 7, the MP1 20 turns off (0) the cache flag 48 of the address table 40 based on this report.
To Further, the SD flag of the space drive number 51 is turned on (1) for the Addr 44 in SCSI in the logical group 10 in which the writing has been performed.

When the update of the address table 40 is completed as described above, the MP 120 receives the completion reports from the SCSI drives 12 of both SD # 4 and SD # 5, and then performs a pseudo write process on the CPU 1. Report the end of. Even when the storage of the new data (ND # 1) in the SCSI drives 12 of SD # 4 and SD # 5 is completed, the new data (ND # 1) exists in the cache memory 7, and
The parity is updated with new data (ND # 1) stored in the cache memory 7.

As described above, after the MP1 20 gives a false end report to the CPU 1, the CPU 1 recognizes that the writing process has been completed.
Since the new parity has not been created and has not been written to the SCSI drive 12, the writing process has not been completed yet. Then, after the MP1 20 reports the completion to the CPU 1, the MP1 20 independently creates a new parity and writes it into the SCSI drive 12. This method will be described below.

After notifying the CPU 1 of the end of the writing process, the MP 1 20 sends the CPU 1, as shown in FIG.
The status (IO status) of the read / write request from 1 is monitored (510). Specifically, the MP1 20 reads the logical group 10 from the CPU 1,
Count the number of write requests per unit time. This number of times for the logical group 10 is smaller than the number set in advance by the user or the system administrator, and the parity is created and the created parity is written in the SCSI.
If the CPU 1 has not issued a read / write request to the logical group 10 to which the drive 12 belongs, the process of creating a parity and writing the parity to the SCSI drive 12 is started.

When creating a new parity, the CPU 1
, The data (old data) written to the address specified as the write destination and the parity to be updated (old parity) are read, and the newly created parity (new parity) is written to the SCSI drive 12. At this time, the SCSI drive 12 for reading the old data and the old parity,
The MP1 20 issues a pseudo read / write request similar to the read / write request from the CPU 1 to the SCSI drive 12 to which the new parity is written. When a read or write request is issued from the CPU 1 to the SCSI drive 12 to which the pseudo read or write request has been issued, MP1
Reference numeral 20 receives a read / write request from the CPU 1 and sets a processing queue.

Next, the creation of a new parity and the corresponding SCS
A method of writing the created parity to the I drive 12 will be specifically described. The MP1 20 issues a read request of old data to the SCSI drive 12 of SD # 1,
The drive IF 28 is instructed to issue an old parity read request to the SCSI drive # 12 (514).

In the SCSI drive 12 to which the read command has been issued from the Drive IF 28,
addr4 in SCSI sent from ve IF28
4 to perform seek and rotation wait access processing. The new data (ND # 1) exists in the cache memory 7, and the parity is updated with the new data (ND # 1) stored in the cache memory 7.

If the new data (N
If D # 1) does not exist, the data duplicated and written in the space area is read out to the cache memory 7.

In the SCSI drives 12 of SD # 1 and SD # 6, as soon as the seek and rotation wait access processing is completed and the old data (D # 1) and the old parity (P # 1) can be read, the old data is read. (D # 1) and the old parity (P # 1) are read and stored in the cache memory 7. The old data (D
# 1), the old parity (P # 1) is read from the SCSI drive 12 of SD # 6, and each of them is stored in the cache memory 7. After that, the MP1 20 writes the new data (written in the cache memory 7). ND # 1)
Then, the new parity after updating (NP #
The PG 36 is instructed to create 1), and the PG 36 is created.
Creates a new parity (NP # 1) and stores it in the cache memory 7 (516).

After the new parity (NP # 1) is stored in the cache memory 7, the new parity (N
The new parity (NP) in the cache memory 7 is stored in the cache address 47 of the logical address 45 storing the P # 1).
The address storing # 1) is registered, the cache flag 48 is turned on (1), and the invalid flag 49 and the drive flag 52 are turned off (0) (518). New parity (N
Recognizing that the creation of P # 1) has been completed,
When no IO request has been issued to the CSI drive 12, the drive IF 28 is instructed to write the updated new parity (NP # 1).

Writing method of new parity (NP # 1) after update to SCSI drive 12 of SD # 6 (520)
Converts the new data (ND # 1) to be written into SD #
This is the same as the method written in the SCSI drives 12 of 4 and 5. When the creation of the new parity (NP # 1) is completed,
The MP1 20 instructs the Drive IF 28 to issue a write command to the SCSI drive 12 of SD # 6.
The seek process is performed on the Addr 44 in the CSI, and an access process for waiting for rotation is performed. The new parity (NP # 1) is already created and stored in the cache memory 7, and the SCSI of SD # 6 is
When the access processing in the drive 12 is completed, C
The Adp 14 reads the new parity (NP # 1) from the cache memory 7 and transfers it to the Drive IF 28. The Drive IF 28 transfers the transferred new parity (NP # 1) to the SCSI drive 12 of SD # 6 via one of the drive unit paths 9-1 to 9-4 (522).

SC of SD # 6 of new parity (NP # 1)
When the writing to the SI drive 12 is completed, the SCSI drive 12 of SD # 6 reports the completion to the Drive IF 28, and reports to the MP 120 that the Drive IF 28 has received the completion report. At this time, M
If the new data (ND # 1) is not to be left in the cache memory 7, the P1 20 turns off (0) the cache flag 48 of the address table 40 based on this report. Turn on (1). Further, in the address table 40, the invalid flag of the logical address 45 of the new parity (NP # 1) after writing is turned off (0), and the drive flag 52 is turned on (1) (524).

After the newly created new parity (NP # 1) is written to the SCSI drive 12, the old data of the SCSI drive 12 of SD # 1 in which the old data (D # 1) is stored is stored. (D # 1) and SD # in which new data (ND # 1) duplicated is stored.
The new data (ND # 1) stored in the SCSI drive 12 of SD # 4 having the smaller SCSI drive number among the SCSI drives 12 of 4 and 5 is released as a space area, and the space area is used for the next write processing. Register as In this registration method, the MP1 20 checks whether the address table 40 has the A # in the SCSI of the SD # 1 and the SD # 4.
The ddr 44 sets the invalid flag to ON (1) at the logical address 45 storing one of the old data (D # 1) of the DADR1 and the new data (ND # 1) that has been duplicated, and further sets the space drive number. SD # 51
1 and SD # 4 are registered, and the SD flag is turned off (0) (526).

As described above, the new data (ND # 1) to be written at the time of the write processing is temporarily duplicated to make the logical group 1
0, and when a read / write request from the CPU 1 is relatively small later, the new parity (NP #
1) is created and stored in the SCSI drive 12, thereby shortening the response time at the time of the write process.
Waiting for the writing process is reduced.

If the new parity (NP # 1) is
If a failure occurs in the SCSI drive 12 in the logical group 10 before writing to the SI drive 12, FIG.
A recovery process is performed as shown in FIG. As shown in FIG. 4A, before writing the new parity (NP # 1) to the SCSI drive 12 of SD # 6 (1402),
If a failure occurs in any one of the SCSI drives 12 among 2 and 3 (1406), the S which has not failed
It is possible to recover the data in the failed SCSI drive 12 from the data from the CSI drive 12 and the old parity (1410). For example, if a failure occurs in the SCSI drive 12 of SD # 1, the SD #
From the old parity (P # 1) from the SCSI drive 1 of SD # 6, the SC # 1
It is possible to recover D # 1, which is data in the SI drive 12. Further, when a failure occurs in one of the SD # 4 and SD # 5 in which the new data (ND # 1) is duplicated and stored, it is possible to recover with one of the duplicated data (1412). ).

As shown in FIG. 4B, the SC of SD # 6
After writing the new parity (NP # 1) to the SI drive 12, the SCSI drives 12 of SD # 2, SD # 3, SD # 5
A new parity (NP # 1) is created for the data (D # 2, 3, ND # 1) in the SD drive and stored in the SCSI drive 12 of SD # 6. When a failure occurs in one of the SCSI drives 12 among the SCSI drives 12, the data in the failed SCSI drive 12 is determined by the data in the remaining normal SCSI drive 12 and the parity in the SCSI drive 12 of SD # 6. Is recovered.

For example, the SCSI drive 12 of SD # 2
If a failure occurs, the SCSI drive 1 of SD # 2
The data (D # 2) in the SCSI drive 12 of SD # 3, the data (ND # 1) in the SCSI drive 12 of SD # 4, and the
From the parity (NP # 1) in the SI drive 12, the data (D # 2) in the SCSI drive 12 of the failed SD # 2 is recovered.

As in the present invention, in the writing process,
The write data (new data) is duplicated and stored in the space area for the time being, and the end of the write processing is reported to the CPU 1 at this stage. It's time. In the conventional array disk, as shown in FIG. 12, a rotation waiting time of 1.5 rotations on average was required at the time of writing. However, if the rotations of the SCSI drives 12 constituting the logical group 10 were synchronized, , The average rotation wait is 0.5 rotation. Also, even if a failure occurs in the SCSI drive 12 that constitutes the logical group 10 before writing the new parity to the SCSI drive 12, as described above, the old parity and the new data duplicated with the conventional array disk cause the failure. Similarly, failure recovery can be performed.

In this embodiment, the parity and the data and space area involved in the creation of the parity are stored in each SCSI drive 12 constituting the logical group 10 in each S drive.
Addr44 in CSI was the same. However, by adding the address of the logical group 10 to each logical address 45, parity drive number 50, and space drive number 51 of the address table 40, each SCSI drive 12 configuring the logical group 10
The Addr 44 in the SCSI can be arbitrarily set.

In this embodiment, in order to reduce the rotation waiting time at the time of writing, the write data is temporarily duplicated and written to the SCSI drive 12, and the parity is updated at an appropriate timing later. The method of releasing one of the written data has been described. The present invention, apart from the viewpoint of performance improvement as described above,
The following application examples are also conceivable.

In the reliability due to parity and the reliability due to duplication, the reliability due to duplication requires a larger capacity for improving the reliability, but the reliability is higher. Taking advantage of this feature, as an application of the present invention, the most recently written data, or data for which a write request is frequently issued, is duplicated, so it is highly reliable,
For data for which few write requests are issued,
It is not as reliable as duplexing, but requires less capacity to improve reliability than duplexing. Parity ensures reliability. In other words, the reliability of data for which few write requests are issued is not as high as that of duplexing, but it is only necessary to attach parity. For data issued, more capacity is required to improve reliability compared to parity, but it is possible to set two levels of reliability, which is highly reliable with high reliability and redundancy It is.

<Embodiment 2> Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, in the system shown in the first embodiment, when a failure occurs in the SCSI drive 12, data in the failed SCSI drive 12 is recovered, and a space area is set in an area for storing the data. Here is an example of use.

In the present invention, as shown in FIG. 3, in each SCSI drive 12 in the logical group 10, a parity group is formed by the data of the corresponding Addr 44 in the same SCSI. Specifically, SD #
Data # 1 in the SCSI drive 12 of 1, 2, 3
The parity # 1 (P # 1) is created by the PG 36 at 2, 3 (D # 1, 2, 3) and stored in the SCSI drive 12 of SD # 6. In this embodiment, the parity is an odd parity, and Data # 1, 2, 3 (D # 1, 2, 3)
The number of 1 is counted for each corresponding bit in each of the data, and is set to 0 for an odd number and to 1 for an even number (exclusive OR). It is assumed that a failure has occurred in the SCSI drive 12 of SD # 1. At this time, Data # 1 (D #
1) cannot be read.

In this embodiment, since there is only one parity per parity group, data can be restored when one SCSI drive 12 fails, but one more drive must be restored before data restoration is completed. SCSI drive 12
Cannot be restored if a failure occurs. Therefore, in such a case, the remaining Data # 2, 3 (D # 2, 3) and parity # 1 (P # 1) are transferred to the cache memory 7 before the failure of the second SCSI drive 12 occurs. And MP
120 instructs the PG 36 to immediately perform a recovery process for restoring Data # 1 (D # 1). After performing this recovery process and restoring Data # 1 (D # 1), MP1 20 converts this Data # 1 (D # 1) into S
D # 4 or 6 is stored in the space area.

As a result, the space area is not only used to reduce the rotation waiting time during the writing process as described in the first embodiment, but also when the SCSI drive 12 fails, the restored data is stored. Also used as a spare area. Thus, MP1 20
After storing the recovered Data # 1 (D # 1) in the space area, in the address table 40 of the cache memory 7 shown in FIG. The number 51 is deleted, and the contents of the recovered logical address 45 of Data # 1 (D # 1) are copied to the logical address 45 corresponding to the deleted drive number.

As shown in FIG. 6, in the SCSI drive 12 of SD # 1, in addition to Data # 1 (D # 1), a space area, parity, Data # 13, 16, 19, and 22 are provided.
(D # 13, 16, 19, and 22) are stored. There is no need to perform recovery processing to restore the space area. Parity # 3 (P # 3) is SD # 3, 4, 5
Data # 7, 8, 9 from the SCSI drive 12
(D # 7, 8, 9) is read out and newly created, and SD #
The data is stored in the space area of the SCSI drive 12 of 2 or 6. Data # 13 (D # 13) is SD # 3,5,6
Parity # 5 (P # 5) from the SCSI drive 12 of
Data # 14, 15 (D # 14, 15) are read out and restored by performing recovery processing, and the SC # 2 or 4 SC
The data is stored in the space area of the SI drive 12. Data
# 16 (D # 16) reads out Data # 17 (D # 17), parity # 6 (P # 6), and Data # 18 (D # 18) from the SCSI drives 12 of SD # 2, SD # 4, SD # 6. , Perform recovery processing and restore, and execute SD # 3 or 5 S
It is stored in the space area of the CSI drive 12. Less than,
Similarly, recovery processing is performed with Data # 19 and Data # 22 (D # 19 and D # 22), and data is stored in the space area in the logical group 10.

As described above, S # of SD # 2, 3, 4, 5, and 6
In the space area in the CSI drive 12, the SD # 1 S
After storing all the recovery data of the CSI drive 12,
Since there is only one space area in the logical group 10, the rotation wait during writing as described in the first embodiment cannot be shortened, so that the processing is performed at RAID level 5, which is a conventional array disk. Also, SD # 1
After all the recovery data of the SCSI drives 12 of the SD # s 2, 3, 4, 5, and 6,
In the case where another SCSI drive 12 fails, the data in the failed SCSI drive 12 is similarly subjected to recovery processing, stored in the remaining space area, and processed.

As described above, when all the space areas in the logical group 10 have been used up, the failure SCS
The I drive 12 is replaced with a normal SCSI drive 12, and all the replaced normal SCSI drives 12 reconfigure the logical group as a space area.

The failed SCSI drive 12 is replaced with a normal SCS
Immediately after replacing with the I drive 12, the space area is concentrated on the specific SCSI drive 12,
Since the SCSI drive 12 cannot be used and is often kept waiting, which causes a bottleneck, the effect of reducing the rotation waiting time shown in the first embodiment cannot be efficiently exhibited. However, as time elapses, the space area is dispersed and returns to the state before the failure of the SCSI drive 12, and is gradually resolved. If this time is a problem, if it is detected that a failure has occurred in the SCSI drive 12, it is replaced with a normal SCSI drive 12, and the failed SCSI drive in the replaced normal SCSI drive 12 is replaced. It is also possible for the user to restore the data and parity in 12. At this time, the space area is left as a space area without being restored.

In this embodiment, the MP 120 performs this recovery process and the process of writing the restored data to the space area independently. By doing this independently, the SCS
In the present invention, when a failure occurs in the I drive 12, the failed SCSI drive 12 is replaced with a normal SCSI drive 12 and the recovered data is written. When a failure occurs in the drive 12, it is not necessary to replace it with a normal SCSI drive 12 immediately, so that the burden on the user is reduced.

<Embodiment 3> A third embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. In this embodiment, as shown in FIGS. 7 and 8, a sub DKC 11 is provided for each logical group 10, and an address table 40 in the cache memory 7 shown in the first and second embodiments as shown in FIG.
And an RPC 27, a PG 36, a sub-cache 32, and a microprocessor MP3 29 for controlling them. The data processing procedure in this embodiment is the same as that shown in the first and second embodiments. Hereinafter, only portions different from the processing procedures described in the first and second embodiments will be described with reference to FIGS. 10 and 11. In this embodiment, FIG.
As shown in (1), the address table 40 in the cache memory 7 shown in the first and second embodiments is stored in the data address table (DAT) 30 in the sub DKC 11. DAT
Reference numeral 30 is similar to the first and second embodiments in the format and function of the stored table, except that the SCSI drive address 42 for storing data is limited to the logical group 10 and that the memory This is a dedicated memory different from that for storing data for storing the address table 40. A
The GAT 23 in the DC 2 stores the CP designated by the CPU 1.
It is only necessary to determine from the U-specified address which logical group 10 in the ADU 3 the location indicated by the CPU-specified address is. In the special area of the cache memory 7, a logical group table (L
GT) 60 is stored.

As shown in FIG. 10, the LGT 60
CPU designated drive number 41 designated by U1 and CC
The table is such that the logical group address 61 can be determined corresponding to the HHR 46. When data corresponding to the CPU-specified address exists in the cache memory 7, the address of the data in the cache memory 7 can be registered in the cache address 47 in the LGT 60, and the data exists in the cache memory 7. If so, a cache flag 48 is prepared which is turned on (1), and turned off (0) if not present in the cache memory 7. The user reserves an area for his or her available capacity at the time of initial setting.
2 MP1 20 is logical group 1 by LGT 60
Assign 0. At this time, the MP1 20 registers an area corresponding to the CPU-specified address specified by the user in the LGT 60.

Therefore, in the actual read / write processing, the GAT 23 uses the LGT 60 to
It is possible to recognize the logical group 10 corresponding to the CPU-specified address specified from. At the time of reading, the GAT 23 determines the logical group 10 by LGC, reports the determined result to the MP 120,
120 instructs the Drive IF 28 to issue a read request to the logical group 10. Drive IF2 instructed from MP1 20
8 is for the sub DKC 11 of the logical group 10
A read request and a CPU-specified address specified by the CPU 1 are issued. In the sub DKC 11, the microprocessor MP3 29 receives the read request command and the CPU-specified address, and performs the D
The CPU-designated address sent from the drive IF 28 is converted into a logical address 45 in the logical group 10 in which the data is stored by referring to the DAT 30, and the logical address 45 is converted to the SCSI drive address 4
2 (SCSI drive number 43 and SCSI A in it)
ddr44) is determined.

After this address is determined, MP3 29
A read request is issued to the SCSI drive 12. SC issued a read request from MP3 29
The SI drive 12 seeks to the Addr 44 in the SCSI and waits for rotation. As soon as the data can be read, the data is transferred to the drive adapter circuit (Dri).
ve Adp) 34 and the Drive Adp 34
Is stored in the sub-cache memory 32. After the storage of the data in the sub-cache memory 32 is completed,
The live Adp 34 reports the storage to the MP3 29, and the MP3 29 turns on (1) the cache flag 48 in the logical address 45 of the data of the DAT 30. Later, when a read or write request is issued for the data whose cache flag 48 is on (1), processing is performed in the sub-cache 32.

In the same manner as in Example 1, D
When the update of the AT 30 is completed, the MP 329 sets the ADC 2
A response indicating that data transfer is possible is made to the Drive IF 28 in the drive. The Drive IF 28 reports this response to the MP 120.

When MP1 20 receives this report,
If storage in the cache memory 7 is possible, Drive
Instruct the IF 28 to transfer data from the sub DKC 11. In Drive IF28, MP12
0, MP3 2 of sub-DKC11
9, a read request is issued. Upon receiving the read request, the MP3 29 instructs the sub-cache adapter circuit (SCA) 31 to read the data from the sub-cache 32, and the SCA 31 actually reads the data and transfers the data to the Drive IF. . After DriveIF 28 receives the data,
The processing described in the first and second embodiments is performed.

On the other hand, at the time of writing, as in the case of reading,
The logical group 10 is determined, and MP1 20
ive IF 28, the MP of the logical group 10
329 is instructed to issue a write request. After the MP3 29 in the logical group 10 receives the write request and stores the write data in the sub-cache 32, the MP3 29 according to the first and second embodiments according to the flowchart of FIG.
The processing is performed in the same manner as described above. In this embodiment, the effects of the first and second embodiments can be realized.

Although the system using the magnetic disk device has been described as an embodiment, the present invention can exert the same effect in a system using an optical disk device.

[0099]

According to the present invention, it is possible to delay the parity update processing at the time of data writing until a read or write request from the CPU is small. This allows the CPU to perform write processing at high speed when there are many read or write processing requests, thereby increasing the number of I / O processes per unit time. Further, a spare SCSI drive that is not normally used can be used to improve the performance of reducing the rotation waiting time, and the SCSI drive resources can be effectively used.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a first embodiment.

FIG. 2 is a configuration diagram in a cluster according to the first embodiment;

FIG. 3 is an explanatory diagram of an address conversion table.

FIG. 4 is an explanatory diagram of data movement during a writing process.

FIG. 5 is a write processing flowchart (1).

FIG. 6 is an explanatory view of a data recovery process, and an explanatory view of a position on a disk of each data constituting a parity group.

FIG. 7 is an overall configuration diagram of a third embodiment.

FIG. 8 is a configuration diagram in a cluster according to the third embodiment.

FIG. 9 is a configuration diagram in a sub-DKC of a third embodiment.

FIG. 10 is an explanatory diagram of a logical group table.

FIG. 11 is an explanatory diagram of an update process in RAID Level5.

FIG. 12 is a write processing timing chart in RAID5.

FIG. 13 is a flowchart (2) of a writing process.

FIG. 14 is a flowchart of a parity creation process.

[Explanation of symbols]

1 CPU, 2 Ray disk controller (AD
C), 3 ... array disk unit (ADU), 4 ... external interface path, 5 ... channel path director, 6 ... channel path, 7 ... cache memory, 8 ... drive path, 9 ... array disk unit path, 10 ...
Logical group, 12: SCSI drive, 13: Cluster, 14: Drive side cache adapter (C Ad
p), 15: interface adapter, 16: channel path switch, 17: control signal line, 18: data line,
19: path, 20: microprocessor 1 (MP1),
21 channel interface (CH IF) circuit,
22: Data control circuit (DCC), 23: Group address conversion circuit (GAT), 24: Channel side cache adapter (C Adp), 28: Drive interface circuit (Drive IF), 29: Microprocessor 3 (MP3), 30 ... Data address table 4
0, 31: sub-cache adapter, 34: drive adapter (Drive Adp), 35: drive path,
36: parity generation circuit, 40: address conversion table (address table), 41: CPU designated drive number, 42: SCSI drive address, 43: SCSI
Drive number, 44: Addr in SCSI, 45: Logical address, 46: CCHHR, 47: Cache address, 48: Cache flag, 49: Invalid flag, 50
... Parity drive number, 51 ... Space drive number, 52 ... Drive flag, 53 ... SD flag, 60 ...
Logical group table, 61 ... logical group address

Continuation of the front page (51) Int.Cl. ⁷ identification code FI G06F 12/10 G06F 12/10 Z (58) Investigated field (Int.Cl. ⁷ , DB name) G06F 3/06 301 G06F 3/06 540

Claims (3)

(57) [Claims] 1. A disk array system comprising: a control device having a cache memory and connectable to a CPU (Central Processing Unit); and a plurality of data storage disk devices connected to the control device. An address conversion table for converting logical address information specified by the CPU into a physical address assigned to each of the disk devices is stored in a specific one of the plurality of disk devices, and device, at power-on of the disk array system, the conversion table from the specific disk device reads in the cache memory, when the power-off of the disk array system, the conversion table the specific disk device in the cache memory Stored in the above
When a failure occurs in any of the disk units,
The data lost on the disk unit to another disk unit
A disk array system wherein the contents of the conversion table are changed with the processing . 2. The disk array system according to claim 1, wherein said logical address comprises a cylinder address, a head address, and a record address. 3. The system according to claim 1, wherein the logical address is a SCSI drive address.
2. The disk array system according to 1.