JP3542545B2 - Solid-state imaging device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging devices, and particularly the pixel region and the peripheral circuit, a solid-state imaging device taking the optimal arrangement for minimizing the uneven polishing of the planarizing layer by the CMP process.
[0002]
[Prior art]
Amplified or non-amplified solid-state imaging devices using charge-coupled devices (CCDs), phototransistors, and photodiodes are used for area sensors, facsimile machines, barcode readers, and the like used in digital still cameras and digital video cameras. It is widely used as a line sensor and has become an indispensable device as a core device of an input device in the information society. There is a strong demand for such a solid-state imaging device to have higher resolution and higher sensitivity. In order to realize high resolution without increasing the chip size, it is necessary to reduce the area per unit pixel and increase the degree of integration of pixels. However, simply reducing the area per unit pixel at the expense of the photodiode area of the pixel decreases the aperture ratio and lowers the sensitivity. In order to realize the two demands of high resolution and high sensitivity, which are contrary to each other, in recent solid-state imaging devices, a method of securing the area of the photodiode by reducing the area ratio of the wiring by miniaturizing the wiring, a method of using a microlens for the pixel, For example, a method of increasing the light condensing rate by disposing it on the top is adopted. Among them, the flatness of the interlayer insulating film between the wiring layers is required for high integration by miniaturization of wiring, especially for manufacturing a solid-state imaging device having a multilayer wiring structure with a design rule of 0.35 μm or less. Keeping is an important technology. As a technique for making the thickness of the flattening layer of the solid-state imaging device uniform, for example, as described in Japanese Patent Application Laid-Open No. 9-55488, flattening is performed by chemical mechanical polishing (CMP). There are methods.
[0003]
FIG. 10A is a circuit block diagram of a conventional configuration of a solid-state imaging device including a pixel region and peripheral circuits such as a signal transfer unit. A pixel region 1001 in which photoelectric conversion elements are arranged is arranged on a semiconductor substrate 1000, and a scanning circuit 1002 for scanning the vertical direction in one of the left and right directions and a scanning circuit for scanning the horizontal direction in one of the up and down directions. A circuit 1003 and a line memory 1004 for storing one horizontal line are arranged.
[0004]
FIG. 7A is a cross-sectional view of a photodiode section (photoelectric conversion element section) in a pixel region of a general solid-state imaging device. The photodiode 706 has a multilayer structure such as an interlayer insulating film 704 and a protective film. If the materials of these layers are not the same, multiple interference of light occurs due to the difference in refractive index. Looking at the spectral sensitivity characteristics of the multilayer structure, ripples are generated, and as a result, a slight difference in wavelength may greatly change the sensitivity of the photodiode. Therefore, if the film thickness of the multilayer film on the photoelectric conversion element varies, the spectral sensitivity characteristics shift according to the film thickness, and the sensitivity to the same wavelength becomes uneven. Further, when the interlayer film thickness of the multilayer wiring changes, the capacitance between the multilayer wirings changes, resulting in variation in circuit characteristics such as gain. These facts indicate that, in a solid-state imaging device in which a plurality of photoelectric conversion elements are arranged, sensitivity to uniform light varies from pixel to pixel, and shading or the like occurs in the output of the solid-state imaging device. Therefore, in order to obtain uniform sensitivity, it is important to flatten the interlayer insulating film on the photoelectric conversion element.
[0005]
[Problems to be solved by the invention]
FIG. 6 shows an output example of a solid-state imaging device when a conventional solid-state imaging device as shown in FIG. 10A is manufactured by incorporating an interlayer film flattening process by CMP. FIG. 6 shows that shading occurs in the output signal in the row (horizontal) direction or the column (vertical) direction even though the solid-state imaging device is irradiated with uniform parallel light. Further, as shown in FIG. 10B, when the film thickness of the interlayer insulating film after the CMP in the solid-state imaging device having the conventional configuration is viewed, the thickness is found at the center and the end of the pixel region (near the peripheral circuit). It can be seen that there is a difference in the thickness, and the interlayer film is thick in a region near the peripheral circuit in the pixel region, and thin in a position far from the peripheral circuit. This causes variations in sensitivity and causes shading.
[0006]
An object of the present invention is to improve the layout of a solid-state imaging device, reduce the difference in the amount of polishing in CMP depending on the position, and provide a solid-state imaging device having good characteristics without output unevenness.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a solid-state imaging device according to the present invention includes a pixel region in which a plurality of photoelectric conversion elements are arranged, and first and second peripheral circuits for reading signals of the pixel region, pixel region and said first, second peripheral circuit has a plurality of wiring layers, an interlayer insulating film is planarized by CMP (chemical mechanical polishing),
The first peripheral circuit is disposed on one of two sides facing each other across the pixel region, and the second peripheral circuit is disposed on the other side of two sides facing each other across the pixel region. It is characterized by being arranged on the side.
[0008]
Further, the solid-state imaging device of the present invention includes a pixel region in which a plurality of photoelectric conversion elements are arranged, a first peripheral circuit for reading a signal of the pixel region, and a signal processing device for processing a signal read from the pixel region. A second peripheral circuit, the pixel region and the first and second peripheral circuits have a plurality of wiring layers, and an interlayer insulating film is planarized by CMP (chemical mechanical polishing);
The first peripheral circuit is disposed on one of two sides facing each other across the pixel region, and the second peripheral circuit is disposed on the other side of two sides facing each other across the pixel region. It is characterized by being arranged on the side.
[0009]
Further, in the solid-state imaging device of the present invention, a pixel region in which photoelectric conversion elements are arranged two-dimensionally in a horizontal direction and a vertical direction, a vertical scanning circuit for reading a signal of the pixel region, and reading a signal of the pixel region And a signal processing circuit for processing a signal read from the pixel area, the pixel area, the vertical scanning circuit, and the first and second horizontal scanning circuits. The circuit and the signal processing circuit have a plurality of wiring layers, the interlayer insulating film is planarized by CMP (chemical mechanical polishing),
The vertical scanning circuit is disposed on one of two sides facing each other across the pixel region in the horizontal direction, and the signal processing circuit is disposed on two sides facing each other in the horizontal direction across the pixel region. The first horizontal scanning circuit is disposed on one side, the first horizontal scanning circuit is disposed on one of two sides vertically opposed to each other across the pixel region, and the second horizontal scanning circuit is disposed on the pixel region. Are arranged on the other of the two sides vertically opposed to each other.
[0010]
Further, the solid-state imaging device of the present invention includes a pixel region in which a plurality of photoelectric conversion elements are arranged, and a peripheral circuit for reading a signal of the pixel region, and the pixel region and the peripheral circuit have a plurality of wiring layers. Then, the interlayer insulating film is planarized by CMP (chemical mechanical polishing),
A region having a higher wiring density than the pixel region is provided in the pixel region.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
[Example 1]
FIG. 1 is a schematic configuration diagram of a pixel region and a peripheral circuit for reading a stored signal of the pixel region according to the present embodiment. Each of the pixel region and the peripheral circuit has a plurality of wirings, and an interlayer insulating film on the plurality of wirings. The film has been planarized by CMP. FIG. 2 is a layout diagram and a cross-sectional view of the first embodiment of the present invention, and shows a layout example in a MOS capacitor.
[0013]
In the case of a multi-layer wiring structure, a process of forming an interlayer insulating film layer for filling a step in a lower wiring layer or the like (FIG. 7A) and flattening this layer by CMP is performed. By forming a second wiring layer or the like thereon, the influence of a step in a lower wiring layer or the like is reduced, and a multilayer wiring structure is manufactured without causing a pattern defect such as cutting of an upper wiring or the like. (FIG. 7B). However, since CMP polishes a large area at a time, when a portion having a large pattern area and a portion having a small pattern area are mixed in a layer such as a lower wiring as shown in FIG. Since the polishing rate of the oxide film is high, a difference in polishing amount occurs between the interlayer insulating film layers for planarization as shown in FIG. 7D.
[0014]
FIG. 9 is an explanatory diagram of a positional relationship between regions having different wiring densities and a relationship between polishing unevenness by CMP. As shown in FIG. 9, when there is a region with a high wiring density (for example, a peripheral circuit) on both outer sides of a region with a low wiring density (for example, a pixel region), the difference in the polishing amount increases when the interval between the high-density regions is large. The smaller the distance between the high-density regions, the smaller the difference in the polishing amount. This means that placing high-density regions symmetrically on both sides rather than placing high-density regions on only one side of low-density regions reduces the difference in polishing amount in low-density regions. It means there is.
[0015]
Therefore, as shown in FIG. 1, in the present embodiment, the scanning circuit and the signal processing circuit are symmetrically arranged on the upper, lower, left, and right sides of the pixel region. In the light receiving unit 109, a plurality of pixels including a photodiode, a MOS transistor, and the like are arranged. Although FIG. 1 shows 5 × 5 pixels for convenience, the number of pixels is actually several hundreds × several hundreds or more. The output control switch of each pixel is connected to a vertical scanning circuit 101 via a vertical scanning line 107, and the output of each pixel is connected to a line memory 103 via a vertical output line 106. Further, the line memory 103 is connected to a horizontal scanning circuit 102 and a horizontal output line 111, and the horizontal output line 111 is connected to a signal processing circuit 110 via an output circuit 104. Then, the signal subjected to the signal processing is output from the output terminal 105.
[0016]
Hereinafter, the operation of the solid-state imaging device will be described. The optical signal of the pixel 108 in the row selected by the vertical scanning circuit 101 is converted into a voltage in the pixel, and is held in the capacity of the line memory 103 via the vertical output line 106. Thereafter, the bits selected by the horizontal scanning circuit 102 are sequentially amplified by the output circuit 104, and sequentially output from the output terminal 105 via the signal processing circuit 110. Such a method of holding a temporary signal in a line memory is a means for reducing fixed pattern noise such as storing an output of a photoelectric conversion element in a dark state in advance and taking a difference from the output when reading an optical signal. Used.
[0017]
As described above, in this embodiment, the horizontal scanning circuit 102 is positioned above and below the pixel area 109, and the vertical scanning circuit 101, AD conversion, AGC (auto gain control), color processing circuit, By arranging the signal processing circuits 110 such as a white balance processing circuit and a gamma processing circuit on the left and right, polishing unevenness due to a difference in polishing amount is further reduced.
[0018]
The polishing amount of the interlayer film after the CMP process also depends on the density (wiring density) of the wiring layer pattern underlying the interlayer film. FIG. 8 plots the relationship between the density of the underlayer pattern and the remaining polishing amount of the upper layer film. As shown in FIG. 8, when the pattern density of the underlying layer (wiring density) is 70% or less, the polishing residue increases sharply when the pattern density exceeds 70%. Therefore, in order to suppress the variation in the polishing amount due to the difference in the pattern density of the base, it is effective to make the pattern density of the base equal to or less than 70%. Here, a method for measuring the characteristics in FIG. 8 will be described with reference to FIG. As shown in FIG. 11A, the line width of the wiring is L, the interval between the wirings is S, L = 5 μm, S = 45 μm (L / S = 1/9), L = 15 μm, S = 35 μm ( L / S = 3/7), L = 25 μm, S = 25 μm (L / S = 5/5), L = 35 μm, S = 15 μm (L / S = 7/3), L = 45 μm, S = 5 μm In the case of (L / S = 9/1), the relative polishing remaining amount for the measurement area (2 mm square) in FIG. 11A was measured. As shown in FIG. 11B, the relative polishing remaining amount is assuming that the thickness of the interlayer insulating film on the substrate after CMP polishing is B1 and B2 and the thickness of the interlayer insulating film on the underlying pattern film is A. Is a value represented by A − ((B1 + B2) / 2). The initial film thickness is 16000 層 間 for the interlayer insulating film and 10000Å for the underlying pattern film.
[0019]
Therefore, in the area sensor, the wiring densities of the pixel region and the peripheral circuit are aligned as much as possible so that the difference in the amount of CMP of the interlayer film is reduced, and the regions having different wiring densities are symmetrically positioned around the pixel region. Deploy. By reducing the wiring density by forming a slit pattern in a capacitor portion occupying a large area on the peripheral circuit, it is possible to further suppress polishing unevenness due to CMP. In this embodiment, the wiring density in the pixel region and the peripheral circuit block is set to 70% or less.
[0020]
Next, the line memory 103 of FIG. 1 described above will be specifically described. The line memory is provided with a large-capacity portion for holding a voltage. The capacitance is a MOS capacitor, and the first metal layer 202 is used to reduce the resistance of the gate electrode as shown in the cross-sectional view of FIG. Similarly, the second metal layer 201 is used as a parallel resistor to keep the voltage on the substrate side constant. Since the voltage on the substrate side is the reference voltage for the entire capacitance of one row, it is desirable to reduce the resistance by increasing the area of the parallel resistance by the second metal layer 201 as much as possible and eliminate the voltage distribution for each pixel. In this embodiment, even in such a portion where a large area pattern is required, the difference in the amount of polishing by CMP from the pixel region having a low wiring density does not appear remarkably, and the wiring density is as large as possible 70%. A slit pattern or the like is provided in the second metal layer 201 to adjust the wiring density.
[0021]
Further, there is a difference in the wiring density between the pixel region designed to reduce the wiring density as much as possible to increase the aperture ratio and the peripheral circuits such as the scanning circuit even though it is 70% or less. In the present embodiment, a horizontal scanning circuit 102 having a wiring density of about 50% is located at the center of a pixel region 109 having a wiring density of 20%, and a vertical scanning circuit having a wiring density of about 50% is disposed above and below the horizontal scanning circuit 102. By arranging the signal processing circuits 110 such as the circuit 101, AD conversion, AGC (auto gain control), color processing circuit, white balance processing circuit, and gamma processing circuit on the left and right, polishing unevenness due to a difference in polishing amount is further reduced. Has been reduced.
[0022]
As described above, by arranging the pixel region at the center and arranging other circuit blocks on the four sides thereof, variations in the thickness of the interlayer insulating film can be reduced, and variations in sensitivity can be suppressed. Further, by making the wiring density of the pixel region and the circuit blocks arranged on the four sides thereof equal to or less than 70%, it is possible to further suppress the variation in sensitivity.
[0023]
[Example 2]
FIG. 3 shows an embodiment similar to the first embodiment, in which a part of a circuit 302 arranged around a pixel region 301 is replaced with a dummy circuit 303 having a wiring density of 70% or less. At this time, both when the dummy circuit 303 is formed on one side (FIG. 3A) and when the dummy circuit 303 is formed on a part of the side (FIG. 3B), the CMP of the interlayer film is performed. This is effective in reducing polishing unevenness. As described above, the effect of the present invention can be obtained even when the peripheral circuit is replaced with a dummy circuit or a pad having a wiring density of 70% or less.
[0024]
[Example 3]
FIG. 4 shows still another embodiment of the present invention, in which a pixel having a partially different structure from a normal pixel or a dummy pixel having a different wiring density is provided in a pixel region. Generally, the pixel region is designed to lower the wiring density in order to secure the aperture ratio. As the number of pixels increases, the area of the pixel region having a relatively low wiring density increases, so that the difference in the amount of polishing between the peripheral circuit having a relatively high wiring density and the vicinity of the center of the pixel region increases. In this embodiment, as shown in FIG. 4, a region 403 having a circuit structure with a different wiring density is arranged in the center of the pixel region 401 to suppress the occurrence of a difference in polishing amount. As a circuit structure having a different wiring density, for example, there is a pixel in which the wiring density of a portion other than the light receiving element in the pixel is partially different. Alternatively, the pixel region may be divided into a plurality of regions, and regions having different wiring densities, for example, regions such as optical black, a signal processing circuit, and a dummy circuit may be arranged in the pixel region to divide the pixel region. There is a similar effect. Further, as long as the position is located in the pixel area, it is effective in suppressing polishing unevenness, regardless of the position.
[0025]
[Example 4]
FIG. 5 shows a fourth embodiment in which the present invention is applied to a line sensor or the like. A scanning circuit and a peripheral circuit 502 are arranged on two sides in the longitudinal direction with respect to a rectangular pixel region 501 for one line. In this way, by arranging circuits having a substantially uniform wiring density in the longitudinal direction in the rectangular pixel region in parallel to the longitudinal direction, it is possible to suppress polishing unevenness. In the line sensor, the two peripheral circuits arranged in the longitudinal direction are constant in the longitudinal direction and the longitudinal direction of the pixel area, regardless of the wiring density, even if the wiring density is different from each other. If they are arranged in parallel, it is effective for suppressing the polishing unevenness in the longitudinal direction in the pixel region. As circuits arranged on two sides, peripheral circuits such as a scanning circuit and signal processing, a dummy circuit, and a pad can also obtain the effects of the present invention.
[0026]
【The invention's effect】
As described above, according to the present invention, by arranging peripheral circuits, dummy circuits or pads at symmetrical positions around the pixel region, the variation in the amount of CMP of the interlayer film is suppressed, and the output of the solid-state imaging device is reduced. Unevenness can be reduced. Further, by adjusting the wiring density to 70% or less, output unevenness can be further reduced.
[Brief description of the drawings]
FIG. 1 is a layout diagram of circuit blocks according to a first embodiment of the present invention.
FIG. 2 is a layout diagram and a cross-sectional view of the first embodiment of the present invention.
FIG. 3 is a plan view showing a configuration example of a circuit block according to a second embodiment of the present invention.
FIG. 4 is a plan view showing a configuration example of a circuit block according to a third embodiment of the present invention.
FIG. 5 is a plan view illustrating a configuration example of a circuit block according to a fourth embodiment of the present invention and illustrating a configuration example of a linear sensor.
FIG. 6 is a characteristic diagram illustrating an output example of a conventional solid-state imaging device.
FIG. 7 is an explanatory cross-sectional view of polishing amount unevenness by CMP polishing.
FIG. 8 is a diagram showing a relationship between a wiring density of a base and a remaining amount of CMP of an interlayer insulating film thereon.
FIG. 9 is a diagram showing the relationship between the arrangement of regions having different underlying wiring densities and the remaining amount of CMP of the interlayer insulating film thereon.
FIG. 10A is a block diagram of a conventional general solid-state imaging device, and FIG. 10B is a characteristic diagram showing a difference between positions of a polishing amount of CMP in the conventional configuration.
FIG. 11 is a diagram for explaining a method for measuring the characteristics of FIG. 8;
[Explanation of symbols]
101 vertical scanning circuit 102 horizontal scanning circuit 103 line memory 104 output circuit 105 output terminal 106 vertical output line 107 vertical direction scanning line 108 pixel 109 pixel region 110 signal processing circuit 111 horizontal output line 201 first metal wiring layer 202 second metal wiring Layer 203 Polysilicon layer 204 Substrate 205 Oxide film 301 Pixel region 302 Peripheral circuit, Pad 303 Dummy circuit 401 Pixel region 402 Peripheral circuit, Dummy circuit, Pad 403 Circuit structure 501 with different wiring densities Pixel region 502 Peripheral circuit, Dummy circuit, Pad 701 Silicon substrate 702 Insulating film 703 First wiring layer 704 Interlayer insulating film 705 Second wiring layer 706 Photodiode 1000 Substrate 1001 Pixel region 1002 Vertical scanning circuit 1003 Horizontal scanning circuit 1004 Line memory

Claims (8)

A pixel region where a photoelectric conversion element and a plurality placed, first for reading the signal of the pixel region, and a second peripheral circuit comprises, pixel region and said first, second peripheral circuit a plurality of wirings Having a layer, the interlayer insulating film is planarized by CMP (chemical mechanical polishing) ,
The first peripheral circuit is disposed on one of two sides facing each other across the pixel region, and the second peripheral circuit is disposed on the other side of two sides facing each other across the pixel region. A solid-state imaging device, which is disposed on a side . The imaging device according to claim 1, wherein each of the first and second peripheral circuits is a scanning circuit. The photoelectric conversion element is arranged two-dimensionally in a horizontal direction and a vertical direction, and the first and second peripheral circuits are arranged so as to sandwich the pixel region in a vertical direction.
The signals of the two-dimensionally arranged photoelectric conversion elements are alternately arranged in the horizontal direction on the first peripheral circuit side and the second peripheral circuit side for each row of a plurality of photoelectric conversion elements arranged in the vertical direction. The solid-state imaging device according to claim 1, wherein the image data is read out separately. A pixel region in which a plurality of photoelectric conversion elements are arranged; a first peripheral circuit for reading a signal from the pixel region; and a second peripheral circuit for processing a signal read from the pixel region. A pixel region and the first and second peripheral circuits have a plurality of wiring layers, an interlayer insulating film is planarized by CMP (chemical mechanical polishing),
  The first peripheral circuit is disposed on one of two sides facing each other across the pixel region, and the second peripheral circuit is disposed on the other side of two sides facing each other across the pixel region. A solid-state imaging device, which is disposed on the side. The first peripheral circuit is a scanning circuit, and the second peripheral circuit is an AD conversion circuit, an AGC (auto gain control) circuit, a color processing circuit, a white balance circuit, or a gamma processing circuit. The solid-state imaging device according to claim 4. A pixel region in which photoelectric conversion elements are arranged two-dimensionally in the horizontal direction and the vertical direction; a vertical scanning circuit for reading a signal of the pixel region; and first and second horizontal circuits for reading a signal of the pixel region A scanning circuit, and a signal processing circuit for processing a signal read from the pixel region, wherein a plurality of the pixel region, the vertical scanning circuit, the first and second horizontal scanning circuits, and the signal processing circuit are provided. The interlayer insulating film is planarized by CMP (chemical mechanical polishing),
  The vertical scanning circuit is disposed on one of two sides facing each other across the pixel region in the horizontal direction, and the signal processing circuit is disposed on two sides facing each other in the horizontal direction across the pixel region. The first horizontal scanning circuit is disposed on one side, the first horizontal scanning circuit is disposed on one of two sides vertically opposed to each other across the pixel region, and the second horizontal scanning circuit is disposed on the pixel region. A solid-state imaging device, which is disposed on the other of the two sides vertically opposed to each other. The solid-state imaging device according to claim 6, wherein the signal processing circuit is an AD conversion circuit, an AGC (auto gain control) circuit, a color processing circuit, a white balance circuit, or a gamma processing circuit. A pixel region in which a plurality of photoelectric conversion elements are arranged; and a peripheral circuit for reading a signal in the pixel region. The pixel region and the peripheral circuit have a plurality of wiring layers, and the interlayer insulating film is formed of a CMP (chemical Flattened by mechanical polishing)
A solid-state imaging device, wherein a region having a higher wiring density than the pixel region is provided in the pixel region .

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