JP3540586B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device having a mask ROM and a rewritable PROM, and more particularly to a semiconductor memory device in which data written in a PROM is apparently erased and rewritable.
[0002]
[Prior art]
In a conventional mask ROM, data is written during the manufacture of the mask ROM, and the user cannot rewrite the data after the manufacture.
[0003]
[Problems to be solved by the invention]
In a conventional mask ROM, after a user purchases a mask ROM, if a data error is found due to a bug in a program on the user side, the mask ROM must be discarded.
[0004]
However, the error of this data is often about several bits, and if the erroneous data of several bits can be rewritten, the mask ROM can be used without discarding.
[0005]
Therefore, as shown in Japanese Patent Application No. Hei 7-320182, a memory cell on which a user can write data is provided on a chip in addition to a mask ROM to remedy a bug of several bits in the mask ROM. Have been.
[0006]
In this case, after writing the corrected data to the memory cell, it may be necessary to rewrite the data at the same address again. Therefore, it is desirable that the rescue memory cell be an erasable cell such as an EEPROM.
[0007]
However, the manufacturing process of the erasable cell is more complicated than that of the mask ROM, so that the manufacturing cost increases.
[0008]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which data of the same address can be rewritten twice or more using a memory cell that can be manufactured in the same manufacturing process as a mask ROM It is to provide a storage device.
[0009]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor memory device according to the present invention includes a mask ROM cell array, a first PROM cell array that stores at least a part of an address corresponding to erroneous data of the mask ROM cell array, One or more addresses corresponding to a portion of the address stored in the PROM cell array. Data group And an address signal inputted from the outside is detected as to whether or not the address signal matches the address stored in the first PROM cell array. Support from cell array Data group Data reading means for reading When two or more addresses matching the first PROM cell array are stored, the data reading means selects and reads a data group having the highest priority from one or more corresponding data groups. It is characterized by the following.
[0010]
Further, a semiconductor memory device of the present invention stores a mask ROM cell array, first reading means for reading data stored in the mask ROM cell array, and a part of an address corresponding to error data of the mask ROM cell array. A first PROM cell array, a second PROM cell array for storing a part of an address corresponding to a defective cell of the mask ROM cell array, and one corresponding to a part of an address stored in the first PROM cell array A third PROM cell array for storing the above data group, a fourth PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the second PROM cell array, Whether the set address matches the address stored in the first PROM cell array. First address detecting means for detecting whether the address inputted from the outside is the same as the address stored in the second PROM cell array; and When the address detecting means detects the coincidence of the addresses, the first signal generating means for outputting a signal for selecting the fourth PROM cell array, and the first address detecting means detects the coincidence of the addresses. If the third PROM cell array is detected, Data group with the highest priority from among And a second signal generating unit that deactivates the first signal generating unit and a corresponding signal from the third PROM cell array. Rude Data reading means for reading the data group.
[0012]
Further, the semiconductor memory device of the present invention stores a mask ROM cell array, first reading means for reading data stored in the mask ROM cell array, and a part of an address of error data included in the mask ROM cell array. A first PROM cell array, a second PROM cell array for storing a part of a row address of a defective cell included in the mask ROM cell array, and a column address of a defective cell included in the mask ROM cell array. A third PROM cell array for storing a section, a fourth PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the first PROM cell array, and the second and third PROM cell arrays. One or more data groups corresponding to some of the addresses stored in the PROM cell array A first PROM cell array, an address input from the outside, first address detection means for detecting whether an address input from the outside matches an address stored in the first PROM cell array, and an address input from the outside. A second address detecting means for detecting whether or not an address stored in the second PROM cell array is coincident with the address stored in the third PROM cell array. A third address detecting means for detecting whether the addresses match, and a second address detecting means detecting an address match, and the third address detecting means detecting an address match. And selecting an output signal of the second address detecting means, and generating an instruction signal indicating that the third address detecting means has detected an address match. First selecting means for selecting a row of the fifth PROM cell array in accordance with an output signal of the first selecting means, and first address detecting means for selecting a row of the fifth PROM cell array. If a match is detected, the first row selection means is deactivated and the fourth PROM cell array is deactivated. Highest priority from medium A second row selecting unit for selecting a row, a column selecting unit for selecting a column of the fourth and fifth PROM cell arrays, and a column selecting unit when the instruction signal is not output from the first selecting unit. A second selection unit that supplies a column address to the selection unit and supplies a row address to the column selection unit when the instruction signal is output from the first selection unit; Selected one of PROM cell array Ride Data reading means for reading the data group.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 2 shows a floor plan according to the first embodiment of the present invention. Hereinafter, the same components are denoted by the same reference numerals, and description thereof will be omitted.
[0015]
As shown in FIG. 2, main body memory cell arrays 1A and 1B each composed of a mask ROM are provided on a semiconductor chip 12. The row decoder 2 is arranged between the main body memory cell arrays 1A and 1B, and is shared by the two main body memory cell arrays. The column decoders 3A and 3B are arranged adjacent to the main body memory cell arrays 1A and 1B, respectively. The main body sense amplifiers 4A and 4B are arranged adjacent to the column decoders 3A and 3B, respectively.
[0016]
Further, on the semiconductor chip 12, there are provided PROM cell arrays 5A and 5B for data storage constituted by PROMs which can electrically rewrite data. The column decoders 7A and 7B are arranged adjacent to the PROM cell arrays 5A and 5B, respectively. The sense amplifiers 8A and 8B are connected to these column decoders 7A and 7B. Data is written in the PROM cell arrays 5A and 5B by a user.
[0017]
Further, a PROM cell array 9 for storing addresses is arranged between the PROM cell arrays 5A and 5B. Logic circuit 10 is arranged adjacent to PROM cell array 9.
[0018]
Further, pad regions 11A and 11B in which a plurality of pads (not shown) are arranged are arranged at two opposing edges of the semiconductor chip 12, respectively.
[0019]
FIG. 3 is a plan view showing a PROM having one polysilicon layer (hereinafter, referred to as a single layer PROM) used in the first embodiment shown in FIG. FIG. 4 is a sectional view taken along the line IV-IV of FIG. 3, and FIG. 5 is a sectional view taken along the line VV of FIG. FIG. 6 shows an equivalent circuit diagram of the PROM.
[0020]
In FIG. 3, the hatched portions are generally called SDG (source, drain, gate) regions, in which source / drain regions and gate electrodes are formed.
[0021]
On the semiconductor substrate 20, a field oxide film 21 is formed. A word line (control gate) 22 is formed in the semiconductor substrate 20. The word line is constituted by a diffusion layer.
[0022]
On the word line 22, a plurality of floating gates 23 are arranged. The floating gate 23 is made of, for example, WSi.
[0023]
A channel of a transistor is formed in the semiconductor substrate 20 directly below a part of the floating gate 23. Source / drain regions 24A and 24B are formed in the semiconductor substrate 20 at both ends of the channel. The source / drain regions 24A and 24B are constituted by diffusion layers.
[0024]
The source / drain regions 24A and 24B are connected to the bit line 25.
[0025]
The adjacent PROMs M1 and M2 share the source / drain regions 24A and 24B.
[0026]
When this one-layer PROM is provided in addition to the mask ROM, the word lines and source / drain regions of the one-layer PROM and the source / drain regions of the mask ROM can be formed at the same time. It can be formed simultaneously. Therefore, the number of manufacturing steps does not increase, and the cost does not increase.
[0027]
Hereinafter, an operation when data is written to this one-layer PROM cell will be described.
[0028]
First, a high potential VPP is supplied to a control gate of a cell to which data is to be written. Since a high potential is supplied to the control gate, the potential of the floating gate also increases.
[0029]
Next, the source of the cell is grounded, and the high potential VPP is supplied to the drain. As a result, hot electrons are generated between the source and the drain of the cell, and electrons are injected into the floating gate. Therefore, the threshold voltage of the transistor increases.
[0030]
Unless a high potential VPP is applied to the drain, no hot electrons are generated. Therefore, in this case, no electrons are injected into the floating gate, and the threshold voltage of the transistor does not change.
[0031]
Next, an operation for reading data from the PROM cell will be described.
[0032]
First, the normal power supply potential VDD is supplied to the control gate of the cell from which data is to be read, and 1 V is applied to the source, for example. When electrons are injected into the floating gate of the cell, no current flows between the source and the drain because the threshold voltage is high. On the other hand, when electrons are not injected into the floating gate of the cell, a current flows between the source and the drain because the threshold voltage is low. Thus, by detecting whether or not a current flows, data stored in the cell can be known.
[0033]
FIG. 1 is a block diagram showing a first embodiment of the present invention. This block diagram shows the data storage PROM cell array 5, the address storage PROM cell array 9, the column decoder 7, the sense amplifier 8, and the logic circuit 10 in the floor plan of the semiconductor memory device shown in FIG. 2 in more detail. is there. The address detection circuit 31, the priority order circuit 32, and the predecoder 33 shown in FIG. 1 are provided in the logic circuit 10 in the floor plan shown in FIG.
[0034]
The address signal supplied from the outside via the pad is supplied to the column decoder 7, the predecoder 33, the row decoder 2 for the main body memory cell array, and the column decoders 3A and 3B shown in FIG.
[0035]
The predecoder 33 generates signals φ1 to φ4 and R1 to R4 according to the input address signal, and supplies the signals to the address storage PROM cell array 9.
[0036]
The address storage PROM cell array 9 stores at least a part of the address of the error data in the main body memory cell array.
[0037]
The address detection circuit 31 detects whether the address stored in the address storage PROM cell array 9 matches the input address signal, and outputs signals OHIT1 to OHIT4 and a signal OTPMODE (OTP: One Time Program). I do. For example, an output circuit (not shown) of the semiconductor memory device outputs data stored in the main body memory cell array or data stored in the data storage PROM cell array 5 to the outside in response to a signal OTPMODE.
[0038]
The priority order circuit 32 selects one of the priority signals from the signals OHIT1 to OHIT4 and supplies the signals OTP1 to OTP4 to the PROM cell array 5 for data storage.
[0039]
The data storage PROM cell array 5 stores data obtained by correcting error data in the main body memory cell array.
[0040]
The column decoder 7 selects a column line of the data storage PROM cell array according to the address signal, reads out the data, and outputs the data to the sense amplifier 8.
[0041]
The sense amplifier 8 outputs read data to the outside via an output circuit (not shown).
[0042]
FIG. 7 shows a circuit example of the data storage PROM cell array 5 and the column decoder 7 used in the embodiment shown in FIG.
[0043]
In this embodiment, two bits A0 and A1 of the address signal are defined as one unit, and the data of the main body memory cell array is replaced for each unit.
[0044]
The input terminals of the column decoder 7 are supplied with address signals A0 and A1, and control signals C1 and C2. The four output terminals of the column decoder are connected to the column lines COL1 to COL4 of the data storage PROM cell array 5, respectively. The column decoder has a terminal to which the high potential VPP is supplied and a terminal connected to an input terminal of the sense amplifier.
[0045]
The column decoder 7 selects one of the column lines COL1 to COL4 according to the address signals A0 and A1, and connects the selected column line to the high potential VPP when writing data according to the control signals C1 and C2. When reading data, the selected column line is connected to the input terminal of the sense amplifier.
[0046]
The data storage PROM cell array 5 has, for example, four banks DBK1 to DBK4 each composed of four single-layer PROM cells. In each bank, the drains of the first to fourth layer PROM cells are connected to column lines COL1 to COL4, respectively, and the sources are all grounded. For example, the bank DBK1 is further composed of PROM cells MD11 to MD14, and the drains of the PROM cells MD11 to MD14 are connected to column lines COL1 to COL4, respectively. The control gates of the single-layer PROM in the same bank are connected to the same word line. Signals OTP1 to OTP4 are supplied to common word lines of the banks DBK1 to DBK4, respectively.
[0047]
FIG. 8 is a diagram for explaining the operation of the predecoder 33 used in the embodiment shown in FIG.
[0048]
For example, A2, A3, A4, and A5 of the address signal are supplied to the input terminal of the predecoder 33. The predecoder 33 outputs 8-bit signals φ1 to φ4 and R1 to R4 according to the address signals A2 to A5.
[0049]
8A and 8B show the relationship between signals φ1 to φ4, R1 to R4 and signals A2 to A5. The signal Z is the logical sum of the signal X and the signal Y. For example, the signal φ1 is a logical sum of / A2 and / A3. Hereinafter, / represents an inverted signal.
[0050]
As can be seen from FIG. 8, only one of the output signals φ1 to φ4 of the predecoder 33 is always at the high level and the other signal is at the low level, and only one of the output signals R1 to R4 is always at the high level and the other Becomes low level. For example, when the signals A2 to A5 are all at a low level, the signals φ1 and R1 are at a high level, and the signals φ2 to φ4 and R2 to R4 are at a low level.
[0051]
The operation logic of the predecoder is not limited to the logic shown in FIG.
[0052]
FIG. 9 shows a circuit example of an address storage PROM cell array used in the embodiment shown in FIG.
[0053]
The address storage PROM cell array 9 is composed of the same number of banks as the data storage PROM cell array 5. Each bank is composed of the same number of PROM cells as the number of output signals of the predecoder 33. According to the above example, the PROM cell array 9 for address storage has four banks ABK1 to ABK4 each composed of eight single-layer PROMs.
[0054]
In each bank, signals φ1 to φ4 and R1 to R4 are supplied to the control gates of the eight single-layer PROMs, respectively, and the sources are all grounded.
[0055]
For example, the bank ABK1 is composed of eight single-layer PROM cells MA11 to MA18, and signals φ1 to φ4 and R1 to R4 are supplied to control gates of the PROM cells MA11 to MA18, respectively. The drains of the eight single-layer PROM cells in each bank are connected to a common drain line. These commonly connected drain lines of the banks ABK1 to ABK4 are called MOHIT1 to MOHIT4, respectively.
[0056]
The common drain lines MOHIT1 to MOHIT4 are connected to the sources of the transistors Q1 to Q4, respectively. Control signals C11 to C14 are supplied to gates of the transistors Q1 to Q4. The drains of the transistors Q1 to Q4 are connected to the source of the transistor Q5. The high potential VPP is supplied to the drain of the transistor Q5 at the time of address writing, and the control signal C15 is supplied to the gate of the transistor Q5.
[0057]
Hereinafter, the bank DBKn of the data storage PROM cell array 5 and the bank ABKn of the address storage PROM cell array are collectively referred to as bank n, where n is a natural number from 1 to 4.
[0058]
FIG. 10 shows a circuit example of the address detection circuit 31 and the priority order circuit 32 used in the embodiment shown in FIG.
[0059]
In the address detection circuit 31, one ends of the current paths of the transistors Q21 to Q24 are connected to the common drain lines MOHIT1 to MOHIT4 of the address storage PROM cell array shown in FIG. The control signal C21 is supplied to gates of the transistors Q21 to Q24. The other ends of the current paths of the transistors Q21 to Q24 are connected to the sources of the transistors Q25 to Q28, respectively. The power supply potential VDD is supplied to the drains of the transistors Q25 to Q28, and the control signal C22 is supplied to all the gates. Usually, the control signals C21 and C22 are at an intermediate potential.
[0060]
The other ends of the current paths of the transistors Q21 to Q24 are respectively connected to input terminals of, for example, two-stage inverters, and output signals of the two-stage inverters are signals OHIT1 to OHIT4, respectively.
[0061]
Further, signals OHIT1 to OHIT4 are supplied to first to fourth input terminals of the NOR gate G1. An output terminal of the NOR gate G1 is connected to an input terminal of the inverter G2. A signal OTPMODE is generated from an output terminal of the inverter G2. The signal OTPMODE indicates whether or not the address signal matches the address stored in the address storage PROM cell array. Data stored in the main memory cell array or data stored in the data storage PROM cell array 5 is output from the semiconductor device according to the signal OTPMODE.
[0062]
The priority circuit 32 includes NAND gates G3 to G8 and inverters G9 to G13. Inverters G10 to G13 include, for example, level shifters, and output high potential VPP when data is written to PROM cell array 5 for data storage.
[0063]
As shown in FIG. 10, signals OHIT2 to OHIT4 are supplied to first input terminals of the NAND gates G3 to G5, respectively, and a signal TOTP inverted by an inverter is supplied to a second input terminal.
[0064]
A signal OHIT1 is supplied to a first input terminal of the NAND gate G6, and second to fourth input terminals are connected to output terminals of the NAND gates G3 to G5, respectively.
[0065]
The signal OHIT2 is supplied to a first input terminal of the NAND gate G7, and the second and third input terminals are connected to output terminals of the NAND gates G4 and G5, respectively.
[0066]
The signal OHIT3 is supplied to a first input terminal of the NAND gate G8, and the second input terminals are respectively connected to output terminals of the NAND gate G5.
[0067]
The signal OHIT4 is supplied to the input terminal of the inverter G9. The input terminals of the inverters G10 to G12 are connected to the output terminals of the NAND gates G6 to G8, respectively, and the input terminal of the inverter G13 is connected to the output terminal of the inverter G9.
[0068]
Signals OTP1 to OTP4 are output from output terminals of inverters G10 to G13, respectively. These signals OTP1 to OTP4 are supplied to the word lines of the banks DBK1 to DBK4 of the data storage PROM cell array 5 as described above.
[0069]
The priority order is assigned to the banks DBK1 to DBK4 by this priority order circuit. In the above-described priority circuit, the higher the number, the higher the priority. For example, in the banks DBK1 and DBK2, the bank DBK2 has priority.
[0070]
In order to write data in the above-described PROM cell array 9 for address storage and the PROM cell array 5 for data storage, for example, a PROM writer is used. The PROM writer supplies, for example, address signals A5 to A0, control signals C1, C2, C11 to C15, C21, C22, TOTP, high potential VPP, power supply potential VDD, and the like.
[0071]
Hereinafter, the write operation and the read operation of this embodiment will be described with reference to FIGS. 11 and 12, a part of the circuit is omitted.
[0072]
For example, a replacement operation by the user when the data of the address “010010” of the main body memory cell array is incorrect will be described. In this embodiment, since the two bits A0 and A1 of the address signal are replaced as one unit, the data from the address "010000" to the address "010011" of the mask ROM must be replaced. For example, the data from the address “010000” to the address “010011” is replaced with 1, 0, 1, and 0. It is assumed that data of another address has already been written in the bank 1 of the PROM cell array 9 for address storage and the PROM cell array 5 for data storage.
[0073]
This write operation is composed of address write, address verify, data write, and data verify processes.
[0074]
First, address writing will be described. The bits A5 to A2 of the address where the error data is stored are written into, for example, the bank ABK2 of the address storage PROM cell array 9.
[0075]
That is, an address signal is externally input to the address pad. The address signals A5 to A2 are "0100", the bit A4 goes high, and the bits A5, A3, A2 go low.
[0076]
The predecoder 33 generates φ1 to φ4 and R1 to R4 from A5 to A2 according to the logic shown in FIG. Therefore, the signal φ1 and the signal R2 are at a high level, and the signals φ2 to φ4, R1, R3, and R4 are at a low level. This high level signal is the high potential VPP.
[0077]
The high potential VPP is supplied to the drain of one of the address storage banks ABK1 to ABK4. For example, the control signals C12 and C15 are set to the high level, the control signals C11, C13 and C14 are set to the low level, and the high potential VPP is supplied only to the drain of the bank ABK2. At this time, the transistors Q21 to Q24 of the address detection circuit 31 are off.
[0078]
As a result, as shown in FIG. 11, electrons are injected into the floating gates of the cells MA21 and MA26 among the PROM cells of the bank ABK2.
[0079]
These control signals C11 to C15 are determined by, for example, external signals supplied from a ROM writer or the like. Therefore, the user determines which data is to be written to which bank.
[0080]
Next, the address verify operation will be described. It is checked whether an address has been written to the bank ABK2.
[0081]
First, an address signal corresponding to the address written in the bank ABK2 is supplied to the address pad from outside. The predecoder 33 sets the signals φ1 and R2 to high level, and sets the signals φ2 to φ4, R1, R3, and R4 to low level and outputs the signals.
[0082]
At this time, the transistors Q1 to Q5 of the address storage PROM cell array 9 are turned off. Further, an intermediate potential is applied to the gates of the transistors Q21 to Q28 of the address detection circuit 31 to make these transistors conductive. Further, in order to prevent writing into the address storage PROM cell array, the potential supplied to the transistors Q25 to Q28 of the address detection circuit is lower than the high potential VPP.
[0083]
In the address storage bank ABK2, the threshold voltages of the memory cells MA21 and MA26 are high, and the threshold voltages of the other memory cells are low. Therefore, all the memory cells are off. Therefore, the common drain line MOHIT2 of the bank ABK2 goes high, and the signal OHIT2 goes high (H).
[0084]
On the other hand, in the address storage bank ABK1, the threshold voltages of the memory cells MA11 and MA17 are high, but the threshold voltages of the other memory cells are low. Since the high-level signal R2 is supplied to the control gate of the memory cell MA16, the memory cell MA16 is turned on. Therefore, the common drain line MOHIT1 of the bank ABK1 goes low, and the signal OHIT1 goes low (L).
[0085]
In the banks ABK3 and ABK4, the signals OHIT3 and OHIT4 are at the low level (L), similarly to the bank ABK1.
[0086]
The signal TOTP shown in FIG. 10 is set at a high level. Therefore, in the priority order circuit 32, the signal OTP2 is at a high level, and the signals OTP1, OTP3, and OTP4 are at a low level.
[0087]
Therefore, by measuring whether or not the signal OTP2 becomes high level, it is possible to confirm whether or not the address is normally written to the bank ABK2, that is, whether or not to enter the redundancy mode.
[0088]
Next, data is written to the bank DBK2 of the data storage PROM cell array 5.
[0089]
At this time, the predecoder 33, the address storage PROM cell array 9 and the address detection circuit 31 are operated in the same manner as in the address verification described above.
[0090]
First, the signal TOTP supplied to the priority order circuit 32 is set to a low level.
[0091]
From the address detection circuit 31, OHIT2 is at a high level and OHIT1, OHIT3, and OHIT4 are at a low level. Therefore, the level shifters G10 to G13 cause the signal OTP2 to be at a high level, which is the high potential VPP, and the signals OTP1, OTP3, and OTP4 to be at a low level. It becomes.
[0092]
In addition, address signals A1 and A0 are appropriately supplied from the outside via the address pad shown in FIG. 7, and when data needs to be written, one of the column lines COL1 to COL4 is selected. Next, the control signal C1 is set at a high level and C2 is set at a low level, a high potential VPP is supplied to the selected column line, and data is written.
[0093]
As a result, as shown in FIG. 11, data corresponding to the addresses "010000" to "010011" is written to the bank DBK2 of the data storage PROM cell array 5. Here, the memory cells MD21, MD22, MD23, MD24 shown in FIG. 11 correspond to the addresses “010000”, “010010”, “010001”, “010011”, respectively.
[0094]
Next, data verification will be described.
[0095]
At this time, the predecoder 33, the address storage PROM cell array 9, and the address detection circuit 31 operate in the same manner as in the above-described data writing.
[0096]
In the priority order circuit 32 shown in FIG. 10, the signal TOTP is set to a low level. In addition, an intermediate potential is output to the level shifters G10 to G13. Therefore, the signal OTP2 has an intermediate potential, and the signals OTP1, OTP3, and OTP4 have a low level.
[0097]
Further, address signals A1 and A0 shown in FIG. 7 are supplied, and one of the column lines COL1 to COL4 is connected to the sense amplifier 8.
[0098]
As a result, the data written in the bank DBK2 of the data storage PROM cell array 5 is read out by the sense amplifier.
[0099]
Next, an operation for rewriting data written in a bank will be described.
[0100]
For example, as shown in FIG. 11, data from address "100000" to address "1000011" is written in bank ABK1, and data from address "010000" to address "010011" is written in bank ABK2. It is assumed that the data stored in the bank ABK2 is rewritten again.
[0101]
First, as described above, the same data as the bank ABK2 is written to the bank ABK3 of the address storage PROM cell array 9.
[0102]
Subsequently, address verification is performed as described above. The output signals OHIT2 and OHIT3 of the address detection circuit 31 go high. Since the signal TOTP is at a high level, the output signals OTP2 and OTP3 of the priority order circuit 32 are at a high level. Therefore, it is confirmed that the banks 2 and 3 are in the OTP mode.
[0103]
Next, as described above, the corrected data is written to the bank DBK3 of the PROM cell array 5 for data storage. In this case, since the signal TOTP is at a low level, the priority order circuit 32 ranks the banks. As a result, the signal OTP3 goes high and the signal OTP2 goes low. Thus, as shown in FIG. 12, data is written to the bank DBK3 of the data storage PROM cell array.
[0104]
Subsequently, data verification is performed in the same manner as described above.
[0105]
Next, the read operation of this embodiment will be described. For example, assume that data at address "010010" is read.
[0106]
This address signal is supplied to the predecoder 33 and the column decoder 7 via the address bus.
[0107]
The predecoder 33 sets the signals φ1 and R2 to high level, and sets other output signals to low level and outputs them.
[0108]
The transistors Q1 to Q5 of the PROM cell array 9 for address storage are off. The transistors Q21 to Q28 of the address detection circuit 31 are turned on, and the power supply potential VDD is supplied to the drains of the transistors Q24 to Q28.
[0109]
Therefore, the output signals OHIT2 and OHIT3 of the address detection circuit 31 are at a high level, and the signals OHIT1 and OHIT4 are at a low level.
[0110]
Therefore, the signal OTPMODE becomes high level. As a result, the output of the data stored in the main body memory cell array is stopped, and the data stored in the data storage PROM cell array is output to the outside.
[0111]
Further, the signal TOTP is set to a high level. As a result, the output signal OTP3 of the priority order circuit 32 goes high, and the other signals OTP1, OTP2, OTP4 go low.
[0112]
Therefore, in the data storage PROM cell array 5, only the control gate of the bank DBK3 goes high. Since the control gate of the bank DBK2 is at a low level, data of the same address stored in the bank 2 is not read.
[0113]
In the column decoder 7, the address signals A1 and A0 are "1" and "0", respectively. As a result, data held in the memory cell MD32 is read out to the sense amplifier 8.
[0114]
As described above, in the present embodiment, when rewriting data at the same address in the mask ROM more than once, new data is written to a new PROM cell and data cannot be read from the PROM cell holding the previous data. To do. As a result, data can be apparently erased and rewritten, and a function similar to that of the EEPROM can be realized in a pseudo manner.
[0115]
Further, since this PROM cell is a single-layer PROM, it can be manufactured by the same manufacturing process as that of the mask ROM. Therefore, the manufacturing cost hardly increases.
[0116]
FIG. 13 shows a second embodiment of the present invention, and shows a modification of the priority order circuit.
[0117]
In the second embodiment, the priority order circuit 34 includes transistors Q31 to Q36. Otherwise, the configuration is the same as that of the first embodiment.
[0118]
In the priority order circuit 34, the output signal OHIT2 of the address detection circuit 31 is supplied to the gate of the transistor Q31. The output signal OHIT3 of the address detection circuit 31 is supplied to the gates of the transistors Q32 and Q34. The output signal OHIT4 of the address detection circuit 31 is supplied to the gates of the transistors Q33, Q35, Q36. The drains of the transistors Q31 to Q33 are connected to a common drain line MOHIT1 of the bank ABK1 of the address storage PROM cell array 9. The drains of the transistors Q34 and Q35 are connected to a common drain line MOHIT2 of the bank ABK2 of the PROM cell array 9 for address storage. The drain of the transistor Q36 is connected to the common drain line MOHIT3 of the bank ABK3 of the PROM cell array 9 for address storage. Further, the sources of the transistors Q31 to Q36 are grounded.
[0119]
The priority order circuit 34 sets the common drain line of the banks other than the bank with the highest priority among the banks determined to match the input address signal by the address detection circuit 31 to the low level. As a result, only the data of the highest priority bank is read from the data storage PROM cell array.
[0120]
In the second embodiment, the same effect as the EEPROM can be obtained by using a single-layer PROM cell that can be manufactured in the same manufacturing process as the mask ROM.
[0121]
Further, the priority order circuit of the second embodiment can be constituted by fewer elements than the priority order circuit shown in FIG. Therefore, when the number of banks is large, it is possible to reduce the area occupied by the priority circuits.
[0122]
FIG. 14 shows a third embodiment of the present invention. In the third embodiment, a disable circuit 35 is used in place of the priority circuits in the first and second embodiments. Other configurations are the same as those of the first embodiment.
[0123]
The disable circuit 35 has the same number of PROM cells M11 to M14 as the number of banks of the PROM cell arrays 5 and 9. The control gates of the PROM cells M11 to M14 are connected to a common line C31. Further, the drains of the PROM cells M11 to M14 are connected to output terminals C32 to C35 of a write circuit composed of, for example, a circuit similar to the transistors Q1 to Q5 shown in FIG.
[0124]
The drains of PROM cells MA11 to MA14 are connected to one ends of the current paths of transistors Q41 to Q44, respectively. The control signal C36 is supplied to gates of the transistors Q41 to Q44. The other ends of the current paths of the transistors Q41 to Q44 are connected to the sources of the transistors Q45 to Q48, respectively. The drains of the transistors Q45 to Q48 are all supplied with the power supply potential VDD, and the gates are all supplied with the control signal C37. Control signals C36 and C37 are normally at an intermediate potential.
[0125]
Further, the other ends of the current paths of the transistors Q41 to Q44 are respectively connected to input terminals of, for example, two-stage inverters. Output signals of the two-stage inverters are supplied to first input terminals of NOR gates G21 to G24, respectively. Inverted signals of the signals OHIT1 to OHIT4 are supplied to second input terminals of the NOR gates G21 to G24. Output signals of the NOR gates G21 to G24 become signals OTP1 to OTP4 and are supplied to the word lines of the data storage PROM cell array 5, respectively.
[0126]
Hereinafter, the operation of the third embodiment will be described.
[0127]
First, data is written to bank 1. That is, data is written to the bank ABK1 of the address storage PROM cell array 9 and the bank DBK1 of the data storage PROM cell array 5.
[0128]
Next, when the data stored in the bank DBK1 is further rewritten, the data is written to the PROM cell M11 of the disable circuit 35 to increase the threshold voltage. Subsequently, for example, an address and data to be newly written are stored in the bank 2.
[0129]
At the time of data reading, when the addresses stored in the banks 1 and 2 are input, the output signals OHIT1 and OHIT2 of the address detection circuit 31 both go high.
[0130]
At the time of data reading, the power supply potential VDD is supplied to the common control gate line C31 of the disable circuit 35. The transistors Q41 to Q48 are conducting. Therefore, the memory cells M11 and M12 are in an off state and an on state, respectively, and the first input terminals of the NOR gates G21 and G22 are at high level and low level, respectively.
[0131]
Therefore, the output signal OTP1 of the NAND gate G21 is at a low level, the output signal OTP2 of the NAND gate G22 is at a high level, and the bank 1 is not selected. As a result, only the data written in the bank 2 is selected and read.
[0132]
In the banks 3 and 4, data of the same address as in the banks 1 and 2 may be written again to replace the data, or data of another address may be written to replace the data.
[0133]
In the third embodiment, similar to the first embodiment, the same effect as the EEPROM can be obtained by using a single-layer PROM cell that can be manufactured in the same manufacturing process as the mask ROM.
[0134]
In the method of giving a priority to each bank as in the first and second embodiments described above, the user must remember the name of the bank used. In order to avoid such trouble, the order of the banks to be written is automatically specified, and the bank used for writing is bank 1 first, and the bank used for writing next is bank 2. It is necessary to provide further.
[0135]
FIG. 15 shows a circuit example of such an automatic bank designating circuit. This circuit is added to the first and second embodiments described above.
[0136]
As shown in FIG. 15, the high potential VPP is supplied to the drain of the transistor Q51, and the control signal C41 is supplied to the gate. The source of transistor Q51 is connected to the drains of transistors Q52 to Q54. Sources of the transistors Q52 to Q54 are connected to drains of the PROM cells M21 to M23, respectively.
[0137]
Each of the PROM cells M21 to M23 is constituted by the above-described single-layer PROM. The control gates of the PROM cells M21 to M23 are connected to a common line C42.
[0138]
For example, an inverted signal of the chip enable signal CE is supplied to the line C42 via a level shifter. The sources of the PROM cells M21 to M23 are grounded.
[0139]
The drains of PROM cells M21 to M23 are connected to one ends of the current paths of transistors Q55 to Q57, respectively. A control signal C43 is supplied to gates of the transistors Q55 to Q57. The other ends of the current paths of the transistors Q55 to Q57 are connected to the sources of the transistors Q58 to Q60, respectively. The drains of the transistors Q58 to Q60 are all supplied with the power supply potential VDD, and the gates are all supplied with the control signal C44. The control signals C43, C44 are normally at an intermediate potential.
[0140]
Further, the other ends of the current paths of the transistors Q55 to Q57 are connected to the input terminals of the inverters G31, G33, G35, respectively. The output terminals of the inverters G31, G33, G35 are connected to the input terminals of the inverters G32, G34, G36, respectively.
[0141]
In the NAND gate G37, the first to third input terminals are connected to the output terminals of the inverters G32, G34, G36, respectively. The output terminal of the NAND gate G37 is connected to the input terminal of the inverter G38.
[0142]
In the NAND gate G39, the first to third input terminals are connected to the output terminals of the inverters G31, G34, G36, respectively. The output terminal of the NAND gate G39 is connected to the input terminal of the inverter G40.
[0143]
In the NAND gate G41, the first to third input terminals are connected to the output terminals of the inverters G31, G33, G36, respectively. The output terminal of the NAND gate G41 is connected to the input terminal of the inverter G42.
[0144]
In the NAND gate G43, the first to third input terminals are connected to the output terminals of the inverters G31, G33, G35, respectively. The output terminal of the NAND gate G43 is connected to the input terminal of the inverter G44.
[0145]
The output terminals of the inverters G44, G42, G40 and G38 are connected to the gates of the transistors Q1 to Q4 constituting the write circuit of the address storage PROM cell array 9 shown in FIG. 9, for example.
[0146]
The output terminals of the inverters G40, G42, G44 are connected to the gates of the transistors Q52, Q53, Q54, respectively.
[0147]
Hereinafter, the operation of the automatic bank designating circuit will be described.
[0148]
When no data is written to the banks 1 to 4, the threshold voltages of the PROM cells M21 to M23 of the automatic bank designating circuit remain low. Therefore, only the signal C11 is at the high level, and the bank 1 of the PROM cell array 9 for address storage is designated. The signals C12 to C14 are at a low level.
[0149]
Thereafter, when writing data to the PROM cell array 9 for address storage and the PROM cell array 5 for data storage, the data is written to the bank 1 because the signal C11 is at a high level.
[0150]
When the data writing to the bank 1 is completed, the control signal C41 is set to the high level. Since only the signal C11 is at the high level, the high potential VPP is applied to the drain of the PROM cell M23 via the transistor Q54. At the same time, the high potential VPP is applied to the control gate of the PROM cell M23. As a result, electrons are injected into the floating gate of the PROM cell M23, and the threshold voltage increases. This writing to the PROM cell must be performed before starting writing data to the next bank.
[0151]
When the threshold voltage of the PROM cell M23 increases, the signal C12 goes high, and the signals C11, C13, and C14 go low. Therefore, the automatic bank designating circuit designates bank 2.
[0152]
After that, similarly, after writing to the bank 2, data is written to the PROM cell M22, and only the signal C13 is set to the high level. The same is true after writing to bank 3.
[0153]
As described above, by providing the automatic bank designating circuit, data can be written to a bank having a higher priority without having to remember the bank used by the user.
[0154]
Although four banks are provided in the above-described embodiment, the number of banks is not limited to four.
[0155]
Further, in the above-described embodiment, the data of the mask ROM is replaced in units of the addresses A0 and A1, but the present invention is not limited to this. All bits of the address may be stored in the address storage PROM cell array, and the data in the mask ROM may be replaced in bit units.
[0156]
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a bug in user data can be repaired by a PROM cell, and a defective cell generated during manufacturing can be replaced.
[0157]
FIG. 16 shows the overall configuration of the semiconductor memory device. In FIG. 16, row decoders 53 and 54 and column decoders 55 and 56 are connected to MROM (mask ROM) cell arrays 51 and 52, respectively. The row decoders 53 and 54 are connected to a row predecoder 57, and the column decoders 55 and 56 are connected to a column predecoder 58. The row predecoder 57 is supplied with address signals A5 to A11, and the column predecoder 58 is supplied with address signals A1 to A4. The memory cells of the MROM cell arrays 51 and 52 are selected by the row decoders 53 and 54, the column decoders 55 and 56, the row predecoder 57, and the column predecoder 58. The column decoders 55 and 56 are connected to sense amplifiers 59 and 60, respectively. The data read from the selected memory cell is output via sense amplifiers 59 and 60. These sense amplifiers 59 and 60 are supplied with an address signal A0 and a chip enable signal (not shown).
[0158]
On the other hand, this semiconductor storage device has OTPPROM cell arrays 61 and 62 as a PROM cell array for data storage which can be rewritten by a user, and R / DPROMs 63 and 64 as a redundant PROM cell array. The OTPPROM cell arrays 61 and 62 are rewritten in the user mode, and the R / DPROMs 63 and 64 are rewritten in the defective cell rewriting mode.
[0159]
In this embodiment, in order to simplify the description, the row direction of the MROM cell arrays 51 and 52 is 64 cells selected by addresses A0 to A5, and the column direction is 64 cells selected by addresses A6 to A11. The cell array has a 2 I / O configuration, and has a total of 4 I / Os.
[0160]
If there are defective cells in the MROM cell array, one word line (128 cells) in each MROM cell array is replaced by the R / DPROM. This replacement unit includes 2I / Os in the same array as all cells selected by the addresses A0 to A5. When data is rewritten by a user, the data is rewritten using one word line (256 cells) of both MROM cell arrays as one unit. This unit includes all the cells selected by the addresses A0 to A5 and 4 I / O. That is, in the case of replacement of a defective cell, a memory cell is replaced for each array (2 I / O), and for user rewriting, a memory cell is replaced for every 4 I / O. Also, in the case of replacing a defective cell, the number of word lines selected in one R / DPROM array is four, and in the case of rewriting by a user, a total of eight word lines, four in each of the TOPPROM cell arrays, are used. Selected.
[0161]
The OTPPROM cell arrays 61 and 62 and the R / DPROMs 63 and 64 are connected to R / D row decoders 65 and 66 as so-called spare row decoders and R / D column decoders 67 and 68. The R / D column decoders 67 and 68 are connected to the column predecoder 58. The memory cells of the OTPPROM cell arrays 61 and 62 are selected by the R / D row decoders 65 and 66 and the R / D column decoders 67 and 68. The high potential VPP, address signals A0 and A5, and signals TOTP and TRD are supplied to the R / D row decoders 65 and 66.
[0162]
The OTP and R / D predecoder 69 are supplied with address signals A6 to A11 and a high potential VPP. The OTP / R / D predecoder 69 is connected to a PROM cell 70 for storing an OTP address and a PROM cell 71 for storing an R / D address. The OTP / R / D predecoder 69 has a level shift circuit described later in the output section.
[0163]
The OTP address storage PROM cell 70 stores the row address of the OTPPROM cell arrays 61 and 62, and the R / D address storage PROM cell 71 stores the row address of the R / DPROM cell arrays 63 and 64. A write load circuit 72 is connected to the OTP address storage PROM cell 70 and the R / D address storage PROM cell 71. The write load circuit 72 is supplied with address signals A0 to A2, a high potential VPP, a chip enable signal CE, and signals TOTP, TRD, and WRITE described later. This write load circuit 72 supplies a high voltage to a memory cell selected at the time of writing an address.
[0164]
An output terminal of the OTP address storage PROM cell 70 is connected to an address detection circuit 73, and an output terminal of the R / D address storage PROM cell 71 is connected to an address detection circuit 74. The address detection circuit 73 detects whether an address signal is output from the OTP address storage PROM cell 70 at the time of reading data, and the address detection circuit 74 outputs an address signal from the R / D address storage PROM cell 71. Detect whether it is.
[0165]
An OTP priority circuit 75 is connected to an output terminal of the address detection circuit 73, and an R / D enable circuit 76 is connected to an output terminal of the address detection circuit 74. The OTP priority circuit 75 selects the latest updated address from the output signals of the address detection circuit 73, and supplies this to the R / D row decoders 65 and 66 as signals OTP1 to OTP4. At the same time, a signal OTPMOD indicating the user mode is generated and supplied to the R / D enable circuit 76. The R / D enable circuit 76 supplies signals RD1L to RD4L for selecting the R / DPROM cell array 63 to the R / D row decoder 65 in accordance with the output signal of the address detection circuit 74, and causes the R / DPROM cell array 64 to The selection signals RD1R to RD4R are supplied to the R / D row decoder 66. In the case of the user mode, the output of the signals RD1R to RD4R and the signals RD1L to RD4L is prohibited according to the signal OTPMOD supplied from the OTP priority circuit 75. As a result, the data written by the user at the time of reading data is read with priority.
[0166]
R / D sense amplifiers 77 and 78 having a load circuit for writing are connected to the R / D column decoders 67 and 68, respectively. The R / D column decoders 67 and 68 are supplied with a high potential VPP and a chip enable signal CE, respectively. The output terminal of the R / D sense amplifier 77 is connected to the input terminal of the switching circuit 79 together with the output terminal of the sense amplifier 59, and the output terminal of the R / D sense amplifier 78 is connected to the switching circuit 80 together with the output terminal of the sense amplifier 60. Is connected to the input terminal of These switching circuits 79 and 80 select the output signals of the sense amplifiers 59 and 60 at the time of normal reading, and in the user mode and the redundancy mode, according to the signals SPMODR and SPMODL output from the R / D enable circuit 76, The output signals of the R / D sense amplifiers 77 and 78 are selected. The output terminals of the switching circuits 79 and 80 are connected to a pad 82 via an output buffer 81. The output buffer 81 is supplied with an output enable signal / OE and a chip enable signal CE. Therefore, data read from the MROM cell arrays 51 and 52 or the OTPRPROM cell arrays 61 and 62 and the R / DPROM cell arrays 63 and 64 are output via the output buffer 81 according to the output enable signal / OE and the chip enable signal CE. Output to pad 82.
[0167]
The pad 82 is connected to the R / D sense amplifiers 77 and 78 via a data input circuit 83. The data supplied to the pad 82 is supplied to the R / D sense amplifiers 77 and 78 via a data input circuit 83.
[0168]
The data write decoder 84 is connected to the R / D row decoders 65 and 66. The data write decoder 84 is supplied with the signals WRITE, TOTP, TRD and address signals A6 and A7. The data write decoder 84 generates signals SBANK1 to SBANK4 based on the signals at the time of data writing and supplies the signals to the R / D row decoders 65 and 66. Therefore, when writing data, the OTP address storage PROM cell 70 and the R / D address storage PROM cell 71 are not used, and the data write decoder 84 and the R / D row decoders 65 and 66 use the OTPPROM cell array 61, 62, the R / DPROM cell arrays 63 and 64 are selected.
[0169]
FIG. 17 shows one I / O of the MROMs 51 and 52 shown in FIG. 16, and FIG. 18 shows a configuration of one block in FIG. As shown in FIG. 17, one I / O is constituted by 16 blocks, and as shown in FIG. 18, one block is constituted by 16 banks. As shown in FIGS. 17 and 18, banks and blocks in the row direction are selected using address signals A1 to A4, and banks and blocks in the column direction are selected using address signals A8 to A11.
[0170]
FIG. 19A shows a circuit configuration of one bank shown in FIG. 18, and FIG. 19B shows a word line selection logic. In the circuit shown in FIG. 19A, one bank includes four cells arranged in the row direction and four cells arranged in the column direction. Two column lines adjacent to one bit line are selected by the column decoder 55 (56), and the bit lines are connected to the sense amplifier 59 (60). One of the column lines is supplied with the ground potential VSS, and the other is supplied with the same intermediate potential as the potential supplied to the sense amplifier. In this embodiment, the sense amplifier 59 (60) uses the address signal A0 to select the ground potential VSS and the intermediate potential of the column line.
[0171]
Further, when one of the output signals SGU and SGD of the row decoder 53 (54) is at the high level “H” and the other is at the low level “L”, one of the four cells in the row direction in the bank in the drawing is shown. The cell is selected. In this embodiment, the address signal A5 is used for this selection. In the column direction, one word line is selected by the address signals A6 and A7. When the address signal is supplied as described above, one cell in the MROM is selected.
[0172]
FIG. 20 shows the configuration of the OTP address storage PROM cell 70 and the R / D address storage PROM cell 71. Since the MROMs 51 and 52 use the address signals A0 to A5 as one unit, the OTP, R / D predecoder 69, the OTP address storage PROM cell 70, and the R / D address storage PROM cell 71 have only the address signals A6 to A11. You only need to memorize it.
[0173]
The OTP address storage PROM cell 70 is composed of 12 rows × 4 columns of PROM cells, and the R / D address storage PROM cell 71 is composed of 12 rows × 8 columns of PROM cells. That is, since the OTPPROM cell arrays 61 and 62 replace the 4 I / Os of the MROMs 51 and 52 with the same address as described above, four columns of the same number as the number of relief lines are arranged. In the R / DPROM cell arrays 63 and 64, eight columns are arranged in order to replace 2 I / Os of each of the MROMs 51 and 52 with the same address.
[0174]
Predecode lines WWL1 to WWL4, WSG1 to WSG4, and WPR1 to WPR4 for transmitting output signals of the OTP and R / D predecoders 69 are arranged in the OTP address storage PROM cell 70 and the R / D address storage PROM cell 71. Connected to the word line. In the OTP address storage PROM cell 70, the drains of the PROM cells are commonly connected to the drain lines MOHIT1 to MOHIT4. In the R / D address storage PROM cell 71, the drains of the PROM cells are connected to the drain lines MRHIT1R to MRHIT4R. Commonly connected to MRHIT1L to MRHIT4L.
[0175]
The OTP / R / D predecoder 69 selects the predecode lines WWL1 to WWL4, WSG1 to WSG4, and WPR1 to WPR4 according to the table shown in FIG.
[0176]
FIG. 22 shows the address detection circuits 73 and 74. The drain lines MOHIT1 to MOHIT4, MRHIT1R to MRHIT4R, and MRHIT1L to MRHIT4L are connected to input terminals of inverters 73e to 73h and 74i to 74p via transistors 73a to 73d and transistors 74a to 74h. The intermediate potential is supplied to the gates of the transistors 73a to 73d and the transistors 74a to 74h when reading data, and the ground potential VSS is supplied when writing data. Transistors 73i to 73l and 74q to 74x are connected between input terminals of the inverters 73e to 73h and 74i to 74p and terminals to which the power VDD is supplied. An intermediate potential is supplied to the gates of these transistors 73i to 73l and 74q to 74x. Signals OHIT1B to OHIT4B, RHIT1BR to RHIT4BR, and RHIT1BL to RHIT4BL are output from the output terminals of the inverters 73e to 73h and 74i to 74p.
[0177]
FIG. 23 shows the operation of the address detection circuits 73 and 74, and shows the main part of FIG. Bank 1 shows a state where addresses are in an unsatisfactory state. That is, the threshold voltage of the PROM cell selected by the predecode line WWL1 is set high, and the threshold voltage of the PROM cell selected by the predecode lines WSG1 and WPR1 is set low. Therefore, the PROM cell selected by the predecode lines WSG1 and WPR1 is turned on, and the potential of the drain line MOHIT1 becomes low level. Therefore, the output signal OHIT1B of the inverter 73e becomes high level.
[0178]
On the other hand, bank 2 shows an address matching state. That is, the threshold voltages of the PROM cells selected by the predecode lines WWL1, WSG1, and WPR1 are all set high. Therefore, the PROM cells selected by the predecode lines WWL1, WSG1, and WPR1 are all turned off, and the potential of the drain line MOHIT2 becomes high level. Therefore, the output signal OHIT2B of the inverter 73f becomes low level, and the OTPPROM cell arrays 61 and 62 are in the selected state.
[0179]
FIG. 24 shows the OTP priority circuit 75. Output signals OHIT1B to OHIT4B of the address detection circuit 73 are supplied to one input terminals of NOR gates 75a to 75d. A signal WRITE is supplied to the other input terminals of the NOR gates 75a to 75d. Output terminals of these NOR gates 75b, 75c, 75d are supplied to one input terminals of NAND gates 75f to 75h constituting a priority circuit 75e. A signal TOTP is supplied to the other input terminals of the NAND gates 75f to 75h via an inverter 75q. Output terminals of the NOR gate 75a and output terminals of the NAND gates 75f to 75h are connected to a plurality of input terminals of the NAND gate 75i. Output terminals of the NOR gate 75b and output terminals of the NAND gates 75g and 75h are connected to a plurality of input terminals of the NAND gate 75j. The output terminals of the NOR gate 75c and the output terminal of the NAND gate 75h are connected to a plurality of input terminals of the NAND gate 75k. The input terminal of the inverter 75l is connected to the output terminal of the NOR gate 75d. Output terminals of the NAND gates 75i, 75j, 75k and the inverter 75l are connected to input terminals of the inverters 75m to 75p, and signals OTP1 to OTP4 are output from output terminals of the inverters 75m to 75p.
[0180]
The signals OHIT1B to OHIT4B are supplied to a NAND gate 75r. The NAND gate 75r outputs a high-level signal OTPMOD when any of the signals OHIT1B to OHIT4B is in a selected state (low level).
[0181]
These signals OTP1 to OTP4 have higher priority as the subscript is larger. That is, these relationships are OTP1 <OTP2 <OTP3 <OTP4. Therefore, in the OTPPROM cell arrays 61 and 62, data is written to a cell selected by the signal OTP1, and when this data is rewritten, data is written to a cell selected by the signal OTP2. When reading the written data, when an address corresponding to the write address is input, the output signals OTP1 and OTP2 of the address detection circuit 73 are both in a selected state (low level). However, only the signal OTP2 is preferentially selected by the OTP priority circuit 75, and the signal OTP1 is non-selected. Therefore, data is read from the cell selected by the signal OTP2.
[0182]
The same data as the data written to the cell selected by the signals OTP1 and OTP2 may be written again to the cell selected by the signals OTP3 and OTP4, or data of another address may be written.
[0183]
In this manner, the operation of the EPROM can be simulated using PROM cells that can be manufactured in the same process as the mask ROM.
[0184]
FIG. 25 shows an R / D enable circuit. The signals RHIT1BR to RHIT4BR output from the address detection circuit 74 are supplied to one input terminals of NOR gates 76a to 76d. The signal OTPMOD and the signal WRITE output from the OTP priority circuit 75 are supplied to a NOR gate 76e. The output signal of the NOR gate 76e is supplied to the other input terminals of the NOR gates 76a to 76d via the inverter 76f. Signals RD1R to RD4R are output from the output terminals of these NOR gates 76a to 76d. These signals RD1R to RD4R are supplied to the R / D row decoder 66.
[0185]
The signals RHIT1BR to RHIT4BR are supplied to a NAND gate 76g. The output signal of the NAND gate 76g is supplied to the NOR gate 76h together with the signal OTPMOD. The output terminal of the NOR gate 76h is supplied to an inverter 76i, and a signal SPMODR for controlling the switching circuit 80 is output from the output terminal of the inverter 76i.
[0186]
Further, signals RHIT1BL to RHIT4BL output from the address detection circuit 74 are supplied to one input terminals of NOR gates 76j to 76m. The signal OTPMOD and the signal WRITE output from the OTP priority circuit 75 are supplied to a NOR gate 76n. The output signal of the NOR gate 76n is supplied to the other input terminals of the NOR gates 76j to 76m via an inverter 76o. Signals RD1L to RD4L are output from the output terminals of these NOR gates 76j to 76m. These signals RD1L to RD4L are supplied to the R / D row decoder 65.
[0187]
The signals RHIT1BL to RHIT4BL are supplied to a NAND gate 76p. The output signal of the NAND gate 76p is supplied to the NOR gate 76q together with the signal OTPMOD. An output terminal of the NOR gate 76q is supplied to an inverter 76r, and a signal SPMODL for controlling the switching circuit 79 is output from an output terminal of the inverter 76r.
[0188]
The R / D enable circuit 76 having the above configuration generates the signals RD1R to RD4R and RD1L to RD4L according to the signals RD1R to RD4R, RHIT1BL to RHIT4BL in the replacement mode of the defective cell. The R / D row decoders 65 and 66 read data stored in the R / DPROM cell array according to the signals RD1R to RD4R and RD1L to RD4L. Therefore, normal data corresponding to the defective cell is read from the R / DPROM cell array.
[0189]
On the other hand, when the user mode is detected by the OTP priority circuit 75, the R / D enable circuit 76 is disabled by the signal OTPMOD output from the OTP priority circuit 75, and the signals RD1R to RD4R and RD1L to RD4L are No output. Therefore, the data of the OTPPROM cell arrays 61 and 62 rewritten by the user is output with priority.
[0190]
When any one of the signals RHIT1BR to RHIT4BR and RHIT1BL to RHIT4BL output from the address detection circuit 74 is selected, one or both of the signals SPMODR and SPMODL enter a selected state (high level). Further, when the user mode is detected, both the signals SPMODR and SPMODL are selected according to the signal OTPMOD output from the OTP priority circuit 75. Therefore, in the defective cell replacement mode, one or both of the switching circuits 79 and 80 shown in FIG. 16 are selected, and the data of the defective cell is replaced with the data read from the R / DPROM cell array. In the user mode, both the switching circuits 79 and 80 are selected, and the cell data is replaced with the data read from the OTPPROM cell array.
[0191]
FIG. 26 shows the configuration of the OTPPROM cell array 61 and the R / DPROM cell array 63. The configurations of the OTPPROM cell array 62 and the R / DPROM cell array 64 are the same as those of the OTPPROM cell array 61 and the R / DPROM cell array 63, and a description thereof will be omitted.
[0192]
In the OTPPROM cell array 61 and the R / DPROM cell array 63, a plurality of PROM cells 61a are arranged in a matrix. The control gate of each PROM cell 61a is commonly connected to control gate lines Cgi1, Cgi2,. The drain of each PROM cell 61a is connected to a bit line BL, and the source is connected to a column line. The bit line BL is connected to an R / D column decoder 67. A transistor 67a is connected between the output terminal of the R / D column decoder 67 and the power supply VDD. The gate of the transistor 67a is grounded via a resistor 76e and is connected to the output terminal of a level shift circuit (LESF) 67d. The signals CESD, WRITE, the signal BYTE inverted by the inverter 67f, and Din are supplied to the NAND gate 67b. The output signal of the NAND gate 67b is supplied to the input terminal of the level shift circuit 67d via the inverter 67c.
[0193]
FIG. 27 shows the configuration of the R / D row decoder 65. The signals OTP1 to OTP4 and the signals RD1L to RD4L are selectively supplied to the NOR gates 65a1, 65a2,..., 65b1, 65b2. Are output to the NOR gates 65c1, 65c2,... Together with the signal TRD, and the output signals of the NOR gates 65b1, 65b2,... Are supplied to the NOR gates 65d1, 65d2,. The configuration after the NOR gates 65c1, 65c2..., 65d1, 65d2.
[0194]
An output signal of the NOR gate 65c1 is supplied to an input terminal of a level shift circuit 65e that converts a signal of a VDD level to a high voltage VPP. The outputs of the level shift circuit 65e are connected to the sources of P-channel MOS transistors 65f to 65i. The drains of these transistors 65f to 65i are connected to control gate lines Cgi1 to cgi4 and grounded via transistors 65j to 65m. The gates of the transistors 65f to 65i and 65j to 65m are connected to the output terminals of the level shift circuits 65o to 65r. Output terminals of NAND gates 65s to 65v are connected to input terminals of these level shift circuits 65o to 65r. Address signals A0 and A5 and their inverted signals A0B and A5B are selectively supplied to the input terminals of the NAND gates 65s to 65v.
[0195]
In the above configuration, at the time of reading data, when the mode becomes the replacement mode of the defective cell or the user mode, one of the signal signals OTP1 to OTP4 and the signals RD1L to RD4L (signals RD1R to RD4R) is in a selected state (high level). . This signal is supplied to the R / D row decoder 65, and selects one control gate line of the OTPPROM cell array 61 or the R / DPROM cell array 63.
[0196]
On the other hand, the bit line is selected by the address signals A1 to A4. However, the number of cells in the row direction shown in FIG. 16 is 128 for the MROM cell array, while 32 cells for the OTPPROM cell array and the R / DPROM cell array. For this reason, it is divided in the column direction by the address signals A0 and A5.
[0197]
By such an operation, a cell is selected, data is read from the selected cell, and detected by the R / D sense amplifier 77. At this time, since the signal SPMODL is at the high level, the output signal of the R / D sense amplifier 77 is selected by the switching circuit 79.
[0198]
FIG. 28 shows an example of the level shift circuit shown in FIG. This level shift circuit includes P-channel transistors P1 and P2 and N-channel transistors N1 and N2, converts a VDD-level signal supplied to an input terminal IN into a VPP-level signal, and outputs the signal to an output terminal OUT.
[0199]
Next, a case where data is written to the OTPPROM cell array or the R / DPROM cell array will be described.
[0200]
FIG. 29 shows an operation when data is written to the OTPPROM cell array or the R / DPROM cell array. When rewriting data, first, the address of the cell to be rewritten is written to the OTP address storage PROM cell 70 or the R / D address storage cell 71 (ST1). Next, data is written to the OTPPROM cell array or the R / DPROM cell array according to the written address (ST2). Thereafter, the written address and data are verified (ST3). By performing writing in such an order, the number of times of generating the high voltage VPP can be reduced. Since it takes time to generate the high voltage VPP, the data writing time can be reduced by reducing the number of times the high voltage VPP is generated.
[0201]
FIG. 30 shows the relationship between each pin and each operation mode. That is, this semiconductor memory device has address pins A0 to A11, / BYTE (/ BYTE in the specification indicates an inverted signal of BYTE), data pins D0 to D3, power supply pins VPP, and TEST pins. R / D address write, R / D address verify, R / D data write, R / D data verify, OTP address write, OTP address verify, OTP data write, and OTP data verify are set using these pins.
[0202]
In the drawing, the / BYTE pin at the time of reading is set to a high or low level. When the / BYTE pin is at a high level, a 4-bit output is provided. When writing and verifying are performed, 4-bit operation is always performed. Therefore, when a signal TOTP or TRD to be described later is detected, 4-bit mode is automatically set, and the signal applied to the / BYTE pin is not used. Therefore, in this embodiment, the address write verification is performed by setting the / BYTE pin to a high level, and the data write verification is performed by setting the / BYTE pin to a low level. HH and VPP indicate high voltages.
[0203]
FIG. 31 shows a write mode detection circuit. High voltage (Vihh) detection circuits 31d to 31f are connected to the address pins A11, A5, and VPP pins, respectively. The output terminals of the high voltage detection circuits 31d and 31e are connected to a NOR gate 31g, and the output terminal of the NOR gate 31g is connected to an inverter 31h. When the user rewrites data, a high voltage is applied to the address pin A11 or A5. Then, one of the output terminals of the high voltage detection circuits 31d and 31e becomes high level, and the signal TOTP is output via the NOR gate 31g and the inverter 31h.
[0204]
The TEST pin is normally grounded via the resistor 31a. To rescue a defective cell, a high level (VDD) is applied to the TEST pin. Then, the signal TRD is output via the inverters 31b and 31c.
[0205]
A high voltage VPP is applied to the VPP pin at the time of writing. Then, a high-level signal WRITE is output from the output terminal of the high voltage detection circuit 31f.
[0206]
FIG. 32 shows the high voltage detection circuit 31d. The other high voltage detection circuits 31e and 31f have the same configuration. This circuit includes P-channel MOS transistors 32a, 32b, N-channel MOS transistors 32c, 32d, 32e, and inverters 32f, 32g, 32h, which constitute an inverter. The source and the back gate of the transistor 32a are connected to the address pin A11. Power supply VDD is applied to the gates of the transistors 32a and 32c, the source of the transistor 32b, and the gate of the transistor 32e.
[0207]
In the above configuration, when the address pin A11 is at a low level, the connection node N32 between the transistor 32a and the transistor 32c is at a low level. In this state, when VPP higher than the power supply VDD is applied to the address pad A11, the node N32 goes high, and a high-level (VDD) signal is output from the output terminal of the inverter 32h.
[0208]
FIG. 33 shows the write load circuit 72. This circuit has an OTP address write load circuit 72a and an R / D address write load circuit 72b. The address signals A0 and A1, the inverted signals A0B and A1B, the signal WRITE and the signal BYTE are selectively supplied to the NAND gates 72c to 72f. Output terminals of the NAND gates 72c to 72f are connected to input terminals of level shift circuits 72k to 72n via inverters 72g to 72j, respectively. These level shift circuits 72k to 72n convert a signal at the VDD level into a signal at the VPP level, and are similar to the circuit shown in FIG.
[0209]
The output terminals of the level shift circuits 72k to 72n are connected to the gates of the transistors 721, 722, 723, and 724 constituting the OTP address write load circuit 72a and the transistor 725 constituting the R / D address write load circuit. , 726, 727, 728, 729, 7210, 7211, and 7212, respectively. One end of the current path of each of the transistors 721 to 724 is connected to each drain line MOHIT1 to MOHIT4 of the OTP address storage PROM cell 70, and the other end of the current path is connected to the power supply VPP via the transistor 7213. The gate of this transistor 7213 is grounded via a resistor 7214.
[0210]
One end of the current path of each of the transistors 725 to 728 is connected to each drain line MRHIT1R to MRHIT4R of the R / D address storage PROM cell 71, and the other end of the current path is connected to the power supply VPP via the transistor 7215. The gate of this transistor 7215 is grounded via a resistor 7216.
[0211]
One ends of the current paths of the transistors 729 to 7212 are connected to the drain lines MRHIT1L to MRHIT4L of the R / D address storage PROM cell 71, and the other ends of the current paths are connected to the power supply VPP via the transistor 7217. The gate of this transistor 7217 is grounded via a resistor 7218.
[0212]
On the other hand, the signal CESB is supplied to the delay circuit 72y via the inverter 72x. This delay circuit 72y delays the rising of inverted signal CESB by a predetermined time and outputs signal CESD. The signal CESD, the signal WRITE, the signal BYTE, the address signal A2, the inverted signal A2B, the signal TOTP, and the signal TRD are selectively supplied to the NAND gates 72o, 72p, 72q. Output terminals of these NAND gates 72o, 72p, 72q are connected to inverters 72r, 72s, 72t, respectively. The output terminals of the inverters 72r, 72s, 72t are connected to the input terminals of the level shift circuits 72u, 72v, 72w. These level shift circuits 72u to 72w have the same configuration as the level shift circuits 72k to 72n. Output terminals of the level shift circuits 72u to 72w are connected to gates of the transistors 7213, 7215, and 7217, respectively.
[0213]
In the above configuration, an operation of writing an address to the OTP address storage PROM cell 70 and the R / D address storage PROM cell 71 will be described. FIG. 34 shows each signal at the time of address writing.
[0214]
Note that the signal CESB is activated at a low level at the time of reading, a standby is at a high level, and writing and verification are at a low level in a test mode. The signal / OE outputs data at a low level.
[0215]
Since the MROMs 51 and 52 use the address signals A0 to A5 as one unit as described above, the address storage cell and the OTP / R / D predecoder 69 need only decode the address signals A6 to A11. Therefore, as shown in FIG. 30, the unused address pins A0 to A5 cause four word lines in the user mode (OTP), four word lines in the defective cell replacement mode (R / D), and eight word lines. Is specified. The defective cell replacement mode and the user mode are distinguished by the potential of the TEST pin and the potential of the address pin A11.
[0216]
The OTP / R / D predecoder 69 has a level shifter circuit as described above. Therefore, the OTP / R / D predecoder 69 outputs a high voltage to the predecode line according to the input address signal. At the same time, the write load circuit 72 shown in FIG. 33 responds to the address signals A0 to A2 and the signals TOTP, TRD, WRITE, and CESD to store the OTP address storage PROM cell 70 or the R / D address storage PROM cell 71. Of the drain lines MOHIT1 to MOHIT4, MRHIT1R to MRHIT4R, and MRHIT1L to MRHIT4L, and a high voltage is applied to the selected drain line. Therefore, data is written only in the cell whose drain and gate are set to a high voltage, and the threshold voltage of this cell is raised.
[0219]
Address detection circuits 73 and 74 are connected to the respective drain lines. However, since the gates of the transistors 73a to 73d and 74a to 74h shown in FIG. It is not applied to the detection circuits 73 and 74.
[0218]
Next, a data write operation will be described. FIG. 35 shows signals of each unit at the time of data writing. Data writing is started by setting the signal CESB to low level. Since the addresses A0 to A5 are defined as one unit, in the case of the user mode or the case of the defective cell replacement mode, if the word line is known, decoding can be performed only by the address signal. Therefore, as shown in FIG. 30, in each mode, four word lines are designated by the unused address pins A6 to A7. In the case of the defective cell replacement mode, each of the two R / DPROM cell arrays 63 and 64 has four word lines on the left and right. However, when writing data, since the left and right are collectively written, it is sufficient that four word lines can be selected. If only one of the left and right sides is used, "0" data is written to the unused PROM cell array.
[0219]
In this embodiment, when address signals A6 and A7 are input to the data write decoder 84, the signals SBAK1 to SBAK4 are output from the data write decoder 84, and these signals are supplied to the R / D row decoders 65 and 66. You. The R / D row decoders 65 and 66 select the word lines of the OTPPROM cell arrays 61 and 62 or the R / DPROM cell arrays 63 and 64 according to this signal. Bit lines of the OTPPROM cell arrays 61 and 62 or the R / DPROM cell arrays 63 and 64 are selected by R / D column decoders 67 and 68 according to address signals A0 to A5. The data supplied from the pad 82 shown in FIG. 16 is supplied to the drain of the PROM cell selected in this manner by the data input circuit 83, the R / D sense amplifier write loads 77 and 78, the R / D column decoder 67, 68 and data is written to the selected PROM cell.
[0220]
As described above, since the word lines of the OTPPROM cell arrays 61 and 62 or the R / DPROM cell arrays 63 and 64 are directly selected by using the data write decoder 84, it is necessary to operate the address detection circuits 73 and 74. There is no. Therefore, the outputs of the OTP and R / D predecoders 69 can all be at a low level, and data can be written even when a high voltage is applied to the VPP pin.
[0221]
Next, the address verify operation will be described. FIG. 36 shows signals of respective units at the time of address verification.
[0222]
When an address is input from the outside while an address is normally written in the OTP address storage PROM cell 70 or the R / D address storage PROM cell 71, the OTP priority circuit 75 outputs signals OTP1 to OTP4. Are output, and signals SPMODR and SPMODL are output from the R / D enable circuit 76. At the time of address verification, the signals OTP1 to OTP4 and the signals SPMODR and SPMODL are taken out to verify whether the address has been written normally. Therefore, a circuit (not shown) for outputting the signals OTP1 to OTP4 to the outside is connected to the output terminal of the OTP priority circuit 75, and the signals SPMODR and SPMODL are output to the output terminal of the R / D enable circuit 76. (Not shown) for performing the operation.
[0223]
In the above configuration, at the time of address verification, the address detection circuits 73 and 74 are operated in the same manner as in a normal read operation, and only the addresses A6 to A11 are input as shown in FIG. If the address has been written normally, signals OTP1 to OTP4 and signals D corresponding to signals SPMODR and SPMODL are output according to the output enable signal / OE. The high voltage VPP at the time of verification is set to 4.3V.
[0224]
Next, data verification will be described. FIG. 37 shows signals of each unit at the time of data verification.
[0225]
The data verification may be the same as a normal data read operation. However, when the sequence shown in FIG. 29 is used, there is a possibility that an address is not correctly written. Therefore, similarly to the above-described data writing, an address signal is supplied from the outside to the data writing decoder 84, and the OTPPROM cell array 61 and the R / D row decoders 65 and 66 are supplied with the address signal. 62 or the word lines of the R / DPROM cell arrays 63 and 64 are selected. The selection of the bit line uses an R / D column decoder. The data read in this way is supplied to switching circuits 79 and 80 via R / D sense amplifiers 77 and 78. At this time, the signals SPMODR and SPMODL are forced to the high level, and the output signals of the R / D sense amplifiers 77 and 78 are selected. The output signal of this switching circuit is output via output buffer 81 and pad 82.
[0226]
According to the fourth embodiment, it is possible to repair a defective cell generated at the time of manufacturing and to rewrite data by a user, so that a bug in a user program can be repaired. Therefore, the yield of the semiconductor memory device can be improved.
[0227]
Also, when writing data to the OTPPROM cell array or the R / DPROM cell array, if an address for selecting a cell of the OTPPROM cell array or the R / DPROM cell array is used, the internal circuit uses the OTP and R / D predecoders as in the read operation. The address must be detected. OTP, R / D predecoders use high voltage to write addresses. Therefore, when the OTP and R / D predecoders are operated at the time of writing data, the high-voltage system in this part must be separated from the high-voltage system in the data section, and the circuit configuration becomes complicated. However, in the fourth embodiment, a data write decoder is provided, and the OTP and the R / D predecoder are not operated at the time of writing data, so that the OTP P A cell group of the ROM cell array or the R / DPROM cell array can be selected. Therefore, the circuit configuration can be simplified.
[0228]
Furthermore, OTP P When writing data to a ROM cell array or R / DPROM cell array, address verification is performed following address writing. Thereafter, when data is written, Vpp must be set to 6.5 V during address writing, Vpp must be reduced to 4.3 V during verification, and Vpp must be boosted again to 6.5 V during data writing. Since it takes time to boost Vpp, such a sequence requires a long time to write data. On the other hand, in the case of the fourth embodiment, data writing is performed subsequent to address writing. Thereafter, address verification and data verification are performed. For this reason, Vpp does not need to be stepped down or stepped up between the address writing and the data writing, so that the data writing time can be shortened.
[0229]
Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, means for relieving a defective cell existing in the column direction is further added to the fourth embodiment. Defective cells existing in the column direction are repaired in block units.
[0230]
FIG. 38 shows a cell replacement unit in the row R / D, the block R / D, and the OTP. The repair of defective cells in the row direction is 1 cell in the column direction, 64 cells in the row direction, and 2 I / Os, and 16 cells in the block direction in the repair column, 4 cells in the row direction, and 2 I / Os. That is, four cells in the row direction indicate the bank shown in FIG. 19, and one block has a configuration in which four banks are consecutively arranged in the column direction. For example, four cells in the row direction are selected by addresses A0 and A5, and 16 cells in the column direction are selected by addresses A6 to A9. The OTP has one cell in the column direction, 64 cells in the row direction, and 4 I / O.
[0231]
FIG. 39 shows a configuration of a fifth embodiment in which FIG. 16 is modified, and FIG. 40 shows an essential part of FIG. 39 and 40, the same parts as those in FIG. 16 are denoted by the same reference numerals, and only different parts will be described.
[0232]
In this embodiment, a row predecoder 91 is added. The row predecoder 91 decodes addresses A0 to A6, and the row predecoder 57 decodes addresses A10 to A11. The signal output from the row pre-decoder 91 is supplied to row decoders 53 and 54 and also to address conversion circuits (A / C) 92 and 93. The output signals of the column predecoder 58 are supplied to these address conversion circuits 92 and 93, and signals BLKMODL, BLKMODR and TRD, which will be described later, are also supplied thereto. The address conversion circuit 92 is connected to the R / D column decoder 67, and the address conversion circuit 93 is connected to the R / D column decoder 68. In the case of row R / D and OTP, the address conversion circuits 92 and 93 supply the same decode signal of the column predecoder 58 as the main body MROM to the R / D column decoders 67 and 68, respectively. In the case of the block R / D, the signals BLKMODL and BLKMODR go to the high level. Then, the address conversion circuits 92 and 93 supply the signals WWL1 to WWL4 and WSG1 to WSG4 output from the row predecoder 91 to the R / D column decoders 67 and 68, respectively.
[0233]
On the other hand, the OTP, R / D predecoder 69 is supplied with addresses A1 to A4. The decode signal of the OTP and R / D predecoder 69 is supplied to a block R / D address storage PROM cell 94. The block R / D address storage PROM cell 94 stores a block R / D address. The block R / D address storage PROM cell 94 is connected to the write load circuit 72 and the address detection circuit 95. The output signal of the address detection circuit 95 is supplied to a row priority circuit 96 together with the output signal of the address detection circuit 74. When both the R / D address storage PROM cell 71 (row R / D) and the block R / D address storage PROM cell 94 (block R / D) hit, the row priority circuit 96 resets the block R / D. The row R / D is selected, and the output signal is connected to the R / D enable circuit 76.
[0234]
FIG. 41 shows the configuration of the PROM cell 94 for storing the block R / D address. The block R / D address storage PROM cell 94 has the same configuration as the (row) R / D address storage PROM cell 71, for example, and the same parts as those of the PROM cell 71 are denoted by the same reference numerals. The block R / D address storage PROM cells 94 output the OTP, R / D predecoder 69 according to the signals WPR1 to WPR4 output from the OTP, R / D predecoder 69 and the addresses A1 to A4. Signals WX1 to WX4 and WCB1 to WCB4 are supplied. When the address hits, the block R / D address storage PROM cell 94 outputs signals MBHIT1R to MBHIT4R and MBHIT1L to MBHIT4L.
[0235]
FIG. 42 shows the address detection circuit 95. The configuration of the address detection circuit 95 is the same as that of the address detection circuit 74, and only the input signal and the output signal are different. That is, input signals are signals MBHIT1R to MBHIT4R and MBHIT1L to MBHIT4L output from block R / D address storage PROM cell 94, and output signals are BHIT1BR to BHIT4BR and BHIT1BL to BHIT4BL.
[0236]
FIGS. 43 and 44 show the configuration of the row priority circuit 96. FIG. In FIG. 43, the output signals RHIT1BR to RHIT4BR of the address detection circuit 74 and the output signals BHIT1BR to BHIT4BR of the address detection circuit 95 are supplied to a logic circuit 96a. When both the output signals RHIT1BR to RHIT4BR and the output signals BHIT1BR to BHIT4BR hit, the logic circuit 96a gives priority to the output signals RHIT1BR to RHIT4BR and outputs these signals as signals RBHIT1BR to RBHIT4BR. When only the signals BHIT1BR to BHIT4BR are hit, the output signals BHIT1BR to BHIT4BR are output as the signals RBHIT1BR to RBHIT4BR. Further, when the signals BHIT1BR to BHIT4BR are hit, the signal BLKMODR is set to a high level.
[0237]
In FIG. 44, output signals RHIT1BL to RHIT4BL of the address detection circuit 74 and output signals BHIT1BL to BHIT4BL of the address detection circuit 95 are supplied to a logic circuit 96b. When both the output signals RHIT1BL to RHIT4BL and the output signals BHIT1BL to BHIT4BL hit, the logic circuit 96b gives priority to the output signals RHIT1BL to RHIT4BL and outputs these signals as signals RBHIT1BL to RBHIT4BL. When only the signals BHIT1BL to BHIT4BL are hit, these output signals BHIT1BL to BHIT4BL are output as the signals RBHIT1BL to RBHIT4BL. Further, when the signals BHIT1BL to BHIT4BL hit, the signal BLKMODL is set to a high level.
[0238]
FIG. 45 shows the configuration of the R / D enable circuit 76. This R / D enable circuit 76 is the same as FIG. 25 except that only the input signal names are changed to signals RBHIT1BR to RBHIT4BR and RBHIT1BL to RBHIT4BL.
[0239]
FIG. 46 shows the configuration of the address conversion circuits 92 and 93. The address conversion circuit 92 includes a NAND circuit 92a, inverter circuits 92b and 92c, and a plurality of transfer gates 92d to 92s. The signal BLKMODL output from the row priority circuit 96 is supplied to one input terminal of a NAND circuit, and the signal TRD is supplied to the other input terminal of the NAND circuit 92a via an inverter circuit 92b. The output terminal of the NAND circuit 92a is connected to the input terminal of the inverter circuit 92c. Adjacent ones of the transfer gates 92d to 92s form a pair, and each pair of the transfer gates is a signal x1 to x4, CB1 output from the column predecoder 58 according to an input signal and an output signal of the inverter circuit 92c. CB4 and one of the signals WWL1 to WWL4 and WSG1 to WSG4 output from the row pre-decoder 91. These transfer gate pairs supply the selected signals to the R / D column decoder 67 as signals RX1L to RX4L and RCB1L to RCB4L.
[0240]
The address conversion circuit 93 has the same configuration as the address conversion circuit 92, and includes a NAND circuit 93a, inverter circuits 93b and 93c, and a plurality of transfer gates 93d to 93s. The signal BLKMODR output from the row priority circuit 96 is supplied to one input terminal of a NAND circuit, and the signal TRD is supplied to the other input terminal of a NAND circuit 93a via an inverter circuit 93b. The output terminal of the NAND circuit 93a is connected to the input terminal of the inverter circuit 93c. Adjacent ones of the transfer gates 93d to 93s form a pair. Each pair of the transfer gates is a signal x1 to x4, CB1 output from the column predecoder 58 according to an input signal and an output signal of the inverter circuit 93c. CB4 and one of the signals WWL1 to WWL4 and WSG1 to WSG4 output from the row pre-decoder 91. These transfer gate pairs supply the selected signals to the R / D column decoder 68 as signals RX1R to RX4R and RCB1R to RCB4R.
[0241]
The operation of the above configuration will be described.
[0242]
(Data read)
When an address is supplied from the outside, the decode signals shown in FIG. 47 are output from the OTP / R / D predecoder 69 in FIG. 39, and these signals are used as the OTP address storage PROM cell 70 and the R / D address storage PROM. The cell 71 is supplied to a block R / D address storage PROM cell 94. In the block R / D address storage PROM cell 94, signals WX1 to WX4 and WCB1 to WCB4 determined by addresses A1 to A4 and signals WPR1 to WPR4 separated into 16 cells out of 64 cells in the column direction are provided. Supplied. In the block R / D address storage PROM cell 94, when these signals match the address written in the PROM cell, one of the output signals MBHIT1R to MBHIT4R and MBHIT1L to MBHIT4L goes high. This signal is supplied to the address detection circuit 95. Therefore, one of the output signals BHIT1BR to BHIT4BR and BHIT1BL to BHIT4BL of the address detection circuit 95 becomes low level. This signal is supplied to the row priority circuit 96. When both the row R / D and the block R / D hit, the row priority circuit 96 deselects the block R / D and selects the row R / D. That is, the output signal of the address detection circuit 74 is output. When the block R / D hits, the signals BLKMODR and BLKMODL output from the low priority circuit 96 are set to the high level. The R / D enable circuit 76 generates a signal for selecting one of the R / DROM cell arrays 63 and 64 according to the signal supplied from the row priority circuit 96. The generated signal is supplied to R / D row decoders 65 and 66. At this time, since the signals BLKMODR and BLKMODL are at the high level, the address conversion circuits 92 and 93 select the signals WWL1 to WWL4 and WSG1 to WSG4 of the low predecoder 91 and supply them to the R / D column decoders 67 and 68.
[0243]
In this example, the R / DPROM cell arrays 63 and 64 can rescue four defective rows or blocks for each I / O0, I / O1 or I / O2 and I / O3 of the main body MROMs 51 and 52.
[0244]
(Address write, address verify)
Writing an address to the block R / D address storage PROM cell 94 and verifying the written address are the same as writing an address to the R / D address storage PROM cell 71 and verifying the same. However, as shown in FIG. 41, the block R / D address storage PROM cell 94 needs signals WX1 to WX4 and WCB1 to WCB4 determined by the addresses A1 to A4. Must be supplied from outside. The writing of the R / D address and the address of the block R / D, and the verification of the R / D address and the verification of the block R / D are distinguished by setting the address pin A5 to a high level or a low level.
[0245]
(Data write, data verify)
Data write and data verify may be selected based on the addresses A0, A5 to A9 that have not been written in the address write, but signals SBAK1 to SBAK4 for selecting four word lines must be newly generated. That is, the signals SBAK1 to SBAK4 are selected by the addresses A6 and A7. Therefore, in order to avoid complication of the configuration, data writing and verification are performed as in the case of the row R / D. For this reason, as shown in FIG. 48, an address is designated by addresses A0 to A5, and the address conversion circuits 92 and 93 output signals x1 to x4 and CB1 selected by the addresses A1 to A4, similarly to the row R / D. To CB4. That is, in the address conversion circuits 92 and 93 shown in FIG. 46, the signals BLKMODL and BLKMODR are both at the low level, and the signal TRD becomes the high level by supplying the high-level signal to the TEST pin shown in FIG. Therefore, each transfer gate selects the signals x1 to x4 and CB1 to CB4.
[0246]
Further, for example, when the block R / D is used for I / O0 and I / O1 of the main body MROM 51 and the low R / D is used for I / O2 and I / O3 of the main body MROM 52, one of the signals SBAK1 to SBAK4 is used. By selecting one, data can be simultaneously written to I / O0 to I / O4.
[0247]
According to the fifth embodiment, a defective cell in the column direction of the main body MROM can be relieved by the block R / D. In addition, the address conversion circuits 92 and 93 switch the column address between the case of OTP and row R / D and the case of block R / D. Therefore, defective cells in the column direction can be relieved without increasing the capacity of the R / DPROM cell arrays 63 and 64.
[0248]
The row priority circuit 96 gives priority to the row R / D when both the row R / D and the block R / D hit. Therefore, multiple selection can be prevented.
[0249]
The row priority circuit 96 gives priority to the row R / D, but may give priority to the block R / D.
[0250]
Of course, various modifications can be made without departing from the spirit of the present invention.
[0251]
【The invention's effect】
As described above in detail, according to the present invention, when rewriting data at the same address of a mask ROM more than once, new data is written to a new PROM cell and data is written from the PROM cell holding the previous data. Since the data cannot be read, the data can be apparently erased and rewritten, and the data can be pseudo-operated in the same manner as the EEPROM.
[0252]
Further, since the PROM cell is a PROM, it can be manufactured in the same manufacturing process as the mask ROM, and the manufacturing cost hardly increases.
[0253]
In addition, the automatic bank designating circuit automatically sets the priority of the bank higher as the data is written later, so that the user does not need to remember the bank used, thereby improving user convenience. Can be.
[0254]
Further, since a redundant PROM cell array is provided, defective cells generated during manufacturing can be relieved by using this cell array.
[0255]
Further, when the address of the repaired defective cell is the same as the address written by the user, the cell written by the user later has priority. Therefore, there is an advantage that user data can be prioritized.
[0256]
In addition, it is possible to repair a defective cell generated at the time of manufacturing and to rewrite data by a user, so that a bug in a user program can be repaired. Therefore, the yield of the semiconductor memory device can be improved. Further, the defective cells in the column direction of the main body MROM can be relieved by the block R / D. In addition, the address conversion circuits 92 and 93 switch the column address between the case of OTP and row R / D and the case of block R / D. Therefore, defective cells in the column direction can be relieved without increasing the capacity of the R / DPROM cell arrays 63 and 64.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a part of a first embodiment of the present invention.
FIG. 2 is a plan view showing a floor plan according to the first embodiment of the present invention.
FIG. 3 is a plan view showing a single-layer PROM of the present invention.
FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3;
FIG. 5 is a sectional view taken along the line VV in FIG. 3;
FIG. 6 is a diagram showing an equivalent circuit of the single-layer PROM in FIG. 3;
FIG. 7 is a circuit diagram showing a PROM cell array for data storage and a column decoder shown in FIG. 1;
FIG. 8 is a view showing the operation of the predecoder shown in FIG. 1;
FIG. 9 is a circuit diagram showing the address storage PROM cell array shown in FIG. 1;
FIG. 10 is a circuit diagram showing an address detection circuit and a priority order circuit shown in FIG. 1;
FIG. 11 is a diagram for explaining the operation of the first embodiment of the present invention.
FIG. 12 is a view for explaining the operation of the first embodiment of the present invention.
FIG. 13 is a circuit diagram showing a second embodiment of the present invention and showing a modification of the priority order circuit.
FIG. 14 is a circuit diagram showing a third embodiment of the present invention and showing a disable circuit.
FIG. 15 shows a third embodiment of the present invention, and is a circuit diagram showing an automatic bank designating circuit.
FIG. 16 is an overall configuration diagram showing a fourth embodiment of the present invention.
FIG. 17 is a diagram showing a configuration of an MROM shown in FIG. 16;
FIG. 18 is a diagram showing a configuration of one block in FIG. 17;
19A is a diagram showing a circuit configuration of one bank shown in FIG. 18, and FIG. 19B is a diagram showing logic of a word line shown in FIG. 19A.
FIG. 20 is a circuit diagram showing an OTP address storage PROM cell and an R / D address storage PROM cell shown in FIG. 16;
FIG. 21 is a view for explaining the operation of FIG. 20;
FIG. 22 is a circuit diagram showing the address detection circuit shown in FIG. 16;
FIG. 23 is a circuit diagram shown for explaining the operation of FIGS. 20 to 22;
FIG. 24 is a circuit diagram showing the OTP priority circuit shown in FIG. 16;
FIG. 25 is a circuit diagram showing the R / D enable circuit shown in FIG. 16;
26 is a circuit diagram showing the OTPPROM cell array and the R / DPROM cell array shown in FIG.
FIG. 27 is a circuit diagram showing the R / D row decoder shown in FIG. 16;
FIG. 28 is a circuit diagram showing the level shift circuit shown in FIG. 27;
FIG. 29 is a flowchart for explaining a write operation of the OTPPROM cell array and the R / DPROM cell array.
FIG. 30 is a diagram showing a relationship between each pin and each operation mode.
FIG. 31 is a circuit diagram showing a write mode detection circuit.
FIG. 32 is a circuit diagram showing the high voltage detection circuit shown in FIG. 31;
FIG. 33 is a circuit diagram showing the write load circuit shown in FIG. 16;
FIG. 34 is a timing chart showing an address write operation.
FIG. 35 is a timing chart showing a data write operation.
FIG. 36 is a timing chart showing an address verify operation.
FIG. 37 is a timing chart showing a data verify operation.
FIG. 38 is a view for explaining the concept of the fifth embodiment of the present invention;
FIG. 39 is a configuration diagram showing a fifth embodiment of the present invention.
FIG. 40 is a configuration diagram showing an enlarged main part of FIG. 39;
FIG. 41 is a circuit diagram showing a PROM cell for storing a block R / D address in FIG. 39;
FIG. 42 is a circuit diagram showing the address detection circuit of FIG. 39;
FIG. 43 is a circuit diagram showing a part of the row priority circuit of FIG. 39;
FIG. 44 is a circuit diagram showing the remaining part of the row priority circuit of FIG. 39;
FIG. 45 is a circuit diagram showing the R / D enable circuit of FIG. 39;
FIG. 46 is a circuit diagram showing the address conversion circuit of FIGS. 39 and 40;
FIG. 47 is a view showing the operation of the OTP and R / D predecoder of FIG. 39;
FIG. 48 is a view showing the relationship between each pin and each operation mode.
[Explanation of symbols]
1A, 1B ... main body memory cell array,
2. Row decoder,
3A, 3B ... column decoder,
4A, 4B ... sense amplifier for main body,
5, 5A, 5B ... data storage PROM cell array,
8, 8A, 8B ... sense amplifier,
9: PROM cell array for address storage,
31 ... address detection circuit
32, 34 ... priority circuit,
33 ... Predecoder,
35 ... disable circuit,
51, 52... MROM (mask ROM) cell array,
53, 54 ... row decoder,
55, 56 ... column decoder,
57, 58, 91 ... row predecoder,
59, 60 ... sense amplifier,
61, 62 ... OTPPROM cell array,
63, 64 ... R / DPROM,
65, 66... R / D row decoder,
67, 68 ... R / D column decoder,
69 ... OTP, R / D predecoder,
70 ... PROM cell for storing OTP address
71 ... PROM cell for storing R / D address
72: write load circuit
73, 74 ... address detection circuit,
75 ... OTP priority circuit,
76 ... R / D enable circuit,
77, 78 ... R / D sense amplifier,
79, 80 ... switching circuit,
84 a data writing decoder
92, 93 ... address conversion circuit,
94 PROM cells for storing block R / D addresses
95 ... address detection circuit,
96 ... Low priority circuit.

Claims (14)

A mask ROM cell array;
A first PROM cell array for storing at least a part of an address corresponding to erroneous data of the mask ROM cell array;
A second PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the first PROM cell array;
Detects whether an address signal input from the outside matches an address stored in the first PROM cell array, and reads data from the second PROM cell array if it matches. Means,
The data reading means selects and reads a data group having the highest priority from one or more corresponding data groups when two or more addresses matching the first PROM cell array are stored. A semiconductor memory device characterized by the above-mentioned. 2. The semiconductor memory device according to claim 1, wherein said first and second PROM cell arrays are each composed of a PROM. 2. The semiconductor memory device according to claim 1, wherein data is externally written to said first and second PROM cell arrays. The data reading means prioritizes the data group in advance,
When further rewriting the data stored in the data group, the second correction data is written to an unused data group having a higher priority than the data group in which the data is stored. Item 2. The semiconductor memory device according to item 1. The data reading means includes a plurality of disable circuits respectively corresponding to the data group,
When the data stored in the data group is further rewritten, the second correction data is written in the unused data group, and the data group in which the data before rewriting is further stored corresponds to the data group. 2. The semiconductor memory device according to claim 1, wherein selection is not possible thereafter by a disable circuit. 2. The semiconductor memory device according to claim 1, further comprising: an automatic bank designating circuit for selecting the unused data group when writing data. A mask ROM cell array;
First reading means for reading data stored in the mask ROM cell array;
A first PROM cell array for storing a part of an address corresponding to error data of the mask ROM cell array;
A second PROM cell array for storing a part of an address corresponding to a defective cell of the mask ROM cell array;
A third PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the first PROM cell array;
A fourth PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the second PROM cell array;
First address detection means for detecting whether or not an externally input address matches an address stored in the first PROM cell array;
Second address detection means for detecting whether or not an externally input address matches an address stored in the second PROM cell array;
First signal generating means for outputting a signal for selecting the fourth PROM cell array when the second address detecting means detects the coincidence of the addresses;
When the first address detecting means detects the coincidence of the addresses, the first address detecting means outputs a signal for selecting a data group having the highest priority from the third PROM cell array, and generates the first signal. Second signal generating means for deactivating the means;
A second read means for reading a corresponding data group from the third PROM cell array. 8. The semiconductor memory device according to claim 7, wherein said first to fourth PROM cell arrays are constituted by PROMs having one polysilicon layer. At the time of data writing, an address for designating the third and fourth PROM cell arrays is supplied, and a data write for outputting a signal for selecting the third and fourth PROM cell arrays according to this address is provided. 8. The semiconductor memory device according to claim 7, further comprising means. 8. The semiconductor memory device according to claim 7, further comprising a switching unit connected to said first and second reading units and extracting data from one of said first and second reading units. The first signal generating means includes a circuit for generating a signal for extracting data from the second reading means by the switching means when outputting a signal for selecting the fourth PROM cell array. 11. The semiconductor memory device according to claim 10, wherein: A mask ROM cell array;
First reading means for reading data stored in the mask ROM cell array;
A first PROM cell array for storing a part of an address of error data included in the mask ROM cell array;
A second PROM cell array for storing a part of a row address of a defective cell included in the mask ROM cell array;
A third PROM cell array for storing a part of an address in a column direction of a defective cell included in the mask ROM cell array;
A fourth PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the first PROM cell array;
A fifth PROM cell array for storing one or more data groups corresponding to a part of addresses stored in the second and third PROM cell arrays;
First address detection means for detecting whether or not an externally input address matches an address stored in the first PROM cell array;
Second address detection means for detecting whether or not an externally input address matches an address stored in the second PROM cell array;
Third address detection means for detecting whether or not an externally input address matches an address stored in the third PROM cell array;
When the second address detection means detects an address match and the third address detection means detects an address match, an output signal of the second address detection means is selected, and the third address detection means selects an output signal of the third address detection means. First selecting means for generating an instruction signal indicating that the address detecting means has detected the address match;
First row selecting means for selecting a row of the fifth PROM cell array in accordance with an output signal of the first selecting means;
When the first address detection means detects an address match, the first row selection means is deactivated and a second row for selecting a row having the highest priority from among the fourth PROM cell arrays. Selecting means;
A column selecting means for selecting a column of the fourth and fifth PROM cell arrays, and a column address being supplied to the column selecting means when the instruction signal is not output from the first selecting means. A second selecting unit that supplies a row address to the column selecting unit when the instruction signal is output from the selecting unit;
A second read means for reading a data group from a selected one of the fourth and fifth PROM cell arrays. 13. The semiconductor memory device according to claim 12, wherein said first to fifth PROM cell arrays are composed of a PROM having one polysilicon layer. At the time of data writing, an address for designating the fourth and fifth PROM cell arrays is supplied, and a signal for selecting one of the fourth and fifth PROM cell arrays is output according to this address. 14. The semiconductor memory device according to claim 13 , further comprising a data writing unit.

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