JP3538941B2 - Television signal recording method and television signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording or reproducing television signals, and more particularly to an apparatus for recording or reproducing various accompanying data in addition to image data and audio data. About.

[0002]

2. Description of the Related Art At present, as a recording / reproducing apparatus for efficiently recording and reproducing NTSC television signals with high quality, image signals are sampled in a 4: 1: 1 format, digitized, and then subjected to DCT conversion and conversion. An image compression recording type digital VTR that compresses and records data by processing such as variable-length coding has been proposed, and will be put into practical use soon. This digital VTR employs a configuration in which data for one frame is recorded using ten tracks.

[0003] As a digital VTR for recording and reproducing a SECAM television signal, there has been proposed a digital VTR which performs the same processing to perform recording. In the image compression recording digital VTR for the SECAM system, an image signal is sampled in a 4: 2: 0 format and A / D converted, and data for one frame is recorded using 12 tracks. Many of the formats are shared with the data format in the digital VTR for the NTSC system.

[0004] On the other hand, a digital VTR has been developed in which a 1125/60 system television signal or a 1250/50 system television signal is compressed and recorded by the same method as described above. . In these digital VTRs, one frame of data is recorded using 20 tracks (1125/60 system) or 24 tracks (1250/50 system). Also above NT
Consideration has been given to commonality in data format with a digital VTR for the SC system or the SECAM system.

[0005] In this specification, the NTS described above is used.
A digital VTR for recording and reproducing television signals of the C system or the SECAM system is SD (STANDA).
RDDENSITY) VTR, the latter 112
A digital VTR for recording / reproducing a 5/60 or 1250/50 television signal is HD (H
(IGN DENSITY) system VTR.

[0006]

By the way, when constructing these high-performance and high-quality digital VTRs, upward compatibility must be established, that is, the HD system VTR.
, It is desirable that recording and reproduction by the SD method can be performed. In that case, regarding the circuit configuration, HD
It is desirable that the recording / reproducing circuit of the system VTR include as many recording / reproducing circuits of the SD system VTR as possible. As a result, it is possible to reduce the cost of a digital VTR in which such upward compatibility is established. The present invention has been made in consideration of the above points.

[0007]

The invention according to claim 1 is a television signal recording method for recording a television signal on a recording medium, the method comprising separating image data from an input television signal, and Ancillary data relating to image data is generated, the ancillary data comprising basic data and additional data. Further, the recording medium is scanned a plurality of times for one frame of the television signal, and
A pair of recording tracks is formed for each scan, and an image data recording area for recording image data and a basic data recording area for recording basic data are additionally provided on each of the pair of recording tracks. And a supplementary data recording area composed of an additional data recording area for recording basic data, and the formation position of the basic data recording area in each of the pair of recording tracks is defined by one frame of the television signal. Are set differently for the odd-numbered scan and the even-numbered scan, and the odd-numbered scan in one frame of the television signal and the even-numbered scan subsequent to this scan have the same basic data contents. The basic data is recorded in a basic data recording area on each recording track.

[0008] In this case, 1 is formed by one scan.
Additional data having the same data content may be recorded in each additional data recording area of each associated data recording area on a pair of recording tracks, or additional data having different data contents may be recorded. May be.

According to a fourth aspect of the present invention, there is provided a television signal recording method for recording a television signal on a recording medium, the method comprising separating image data from an input television signal and recording the television signal on the recording medium. It has information for searching the contents and generates secondary data composed of basic data and additional data, and further scans the recording medium a plurality of times for one frame of the television signal. Thus, a pair of recording tracks is formed for each scan, and an image data recording area for recording image data and a secondary data recording area for recording secondary data are formed on each recording track of the recording medium. And a secondary data recording area on each recording track is provided with a basic data recording area for recording the basic data and an additional data for recording the additional data. A data recording area, and in each scan in the first half period of one frame of a television signal, secondary data having the same data content is recorded in a secondary data recording area of a recording medium; In each scan of the second half of one frame of the signal, the secondary data having the same data content is recorded in the secondary data recording area of the recording medium, and the additional data on one recording track is further recorded. Recording area
When recording additional data in the two separate recording zones having the same recording capacity and recording the additional data in the two recording zones, each recording is performed every one scanning in the first half of one frame of the television signal. The additional data recorded in the two recording zones in the track are exchanged with each other, and are further recorded in the two recording zones in each scanning in the latter half of one frame of the television signal. Each additional data is exchanged with each other.

According to a fifth aspect of the present invention, there is provided a television signal recording / reproducing apparatus for recording / reproducing a television signal using a recording medium, comprising: separating means for separating image data from an input television signal; Ancillary data generating means for generating ancillary data comprising basic data and additional data, the ancillary data relating to the image data, and a pair of recording means, and recording for one frame of a television signal Scanning means for scanning the medium a plurality of times to form a pair of recording tracks for each scan by the pair of recording means and recording the image data and associated data on the recording medium; Means for scanning a recording medium a plurality of times for one frame of a television signal, whereby the recording medium is recorded by said pair of recording means. Reproducing means for reproducing the image data and the accompanying data from a pair of recording tracks; restoring means for restoring a television signal based on the image data reproduced by the reproducing means; and accompanying data reproduced by the reproducing means And an accompanying data deriving unit that derives the determined attached data based on, and the pair of recording units record image data in an image data recording area formed on each recording track, In an auxiliary data recording area composed of a basic data recording area and an additional data recording area formed at different positions on a recording track by odd-numbered scanning and even-numbered scanning in one frame of a television signal. Attachment data is recorded, and odd-numbered scanning in one frame of the television signal, and even-numbered scanning following this scanning are performed. In scanning,
Basic data having the same data content is recorded in a basic data recording area on each recording track.

In this case, the accompanying data deriving means outputs the basic data reproduced from the pair of recording tracks by the odd-numbered scanning in one frame of the television signal by the reproducing means and the even-numbered scanning following this scanning. By integrating, the determined basic data can be derived.

The pair of recording means may record additional data having the same data content as each other.
At this time, the accompanying data deriving means is 1
By integrating the additional data reproduced from the pair of recording tracks in each scan, the determined additional data can be derived. The pair of recording means,
Additional data having different data contents can be recorded.

According to a tenth aspect of the present invention, in a television signal recording / reproducing apparatus for recording / reproducing a television signal using a recording medium, separating means for separating image data from an input television signal, and a recording medium Has information for searching the recorded content recorded in the
A secondary data generating means for generating secondary data composed of basic data and additional data; and a pair of recording means, wherein the recording medium is scanned a plurality of times for one frame of the television signal. The image data is recorded in an image data recording area of each recording track by forming a pair of recording tracks for one scan by the pair of recording means, and the secondary data is stored in the basic data. A secondary data recording area composed of a basic data recording area in which basic data is recorded and an additional data recording area in which the additional data is composed of two separated recording areas having the same recording capacity. Scanning means for recording, and a pair of reading means, and scanning the recording medium a plurality of times for one frame of the television signal, whereby the pair of reading means From the recording track of the pair formed by the recording means and reproducing means for reproducing the image data and the auxiliary data, and restoring means for restoring the television signal based on the image data reproduced by the reproducing means,
Based on the secondary data reproduced by the reproducing means,
Secondary data deriving means for deriving the determined secondary data, and wherein the scanning means has the same data content in each of a plurality of scans in the first half period of one frame of the television signal. And recording the secondary data having the same data content on the recording medium in each of a plurality of scans in the second half period of one frame of the television signal. Further, with respect to the additional data recorded in each of the two recording areas of the additional data recording area on each recording track, the recording areas are alternated with each other for each scan in the first half of one frame of the television signal. The additional data recorded in the two recording areas is also recorded every second scanning of the one frame of the television signal. And so as to record the replacement recording area of the data with each other.

In this case, the secondary data deriving means integrates the additional data in the secondary data reproduced in one of the first half and the second half of one frame of the television signal, Preferably, it is arranged to determine the additional data reproduced during the period.

[0015]

The image data and the accompanying data are simultaneously recorded on two recording tracks by using a pair of recording heads, and the same data is recorded in the main area of the recording area of the image accompanying data in units of two track pairs. The position of the main area on the recording track is switched every two tracks. In the optional area of each image accompanying data recording area of a pair of recording tracks recorded by a pair of recording heads, the same optional data is recorded or optional data different from each other is recorded.

With respect to the optional data recorded in the subcode, the optional data recorded by the same recording head has its recording position switched every scanning, and the same optional data is recorded in the first half period of one frame. Data is recorded repeatedly. In the second half period of one frame, the optional data recorded is different from the optional data recorded in the first half of one frame, but the optional data recorded by the same recording head is the same, and is repeatedly recorded. .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of an SD VTR will be described, and then an HD VTR according to an embodiment of the present invention will be described in detail.

[1] Outline of SD System VTR The outline of the SD system VTR will be sequentially described in accordance with the following items, especially focusing on the NTSC system digital VTR. 1. Recording format of SD VTR (1) ITI area (2) AUDIO area (3) VIDEO area (4) SUBCODE area (5) Structure of ID part (6) Structure and type of pack (7) Structure of accompanying information recording area (8) Application ID system 2. Recording circuit of SD VTR Reproduction circuit of SD system VTR

1. Recording Format of SD VTR FIG. 16 shows a recording format on a tape in an NTSC SD VTR. In this figure, margins are provided at both ends of the track. Then, inside the recording start end, an IT for ensuring dubbing is performed.
There are provided an I area, an AUDIO area for recording an audio signal, a VIDEO area for recording an image signal, and a SUBCODE area for recording secondary data. An inter-block gap (IBG) is provided between the areas to secure the area.

Next, the details of the signals recorded in each of the above areas will be described. (1) ITI Area As shown in the enlarged part of FIG. 16, the ITI area has a 1400-bit preamble and an 1830-bit SSA (Start-Sync Block Are).
a), 90-bit TIA (Track Information)
ation Area) and a 280-bit postamble.

Here, the preamble has a function such as a run-in of the PLL at the time of reproduction, and the postamble has a role to gain a margin. And SSA and TIA are
Each block data has a predetermined SY in the first 10 bits of the block data.
An NC pattern (ITI-SYNC) is recorded.

In the 20-bit portion following the SYNC pattern, SYNC block numbers (0 to 60) are mainly recorded in SSA, and 3-bit APT information (APT2 to APO) is mainly used in TIA. An SP / LP flag for identifying a recording mode and a PF flag indicating a reference frame of the servo system are recorded. A
PT is ID data that defines a data structure on a track, and takes a value “000” in the SD system VTR.

As can be seen from the above description, since a large number of sync blocks with a short code length are recorded at fixed positions on the magnetic tape in the ITI area, for example, the 61st SYNC pattern of SSA is obtained from the reproduced data. By using the detected position as a reference for defining the after-recording position on the track, the position to be rewritten at the time of after-recording can be defined with high accuracy, and good after-recording can be performed. The SD system VTR is designed so that it can be easily developed into various digital signal recording / reproducing devices outside as described later. Therefore, the ITI area on the track entrance side is always provided.

(2) AUDIO area The audio area has a preamble and a postamble before and after the audio area as shown in the enlarged part of FIG. 16, and the preamble is a run-up for pulling in the PLL,
And a pre-SYNC for pre-detection of an audio SYNC block. The postamble is a post S for confirming the end of the audio area.
It is composed of a YNC and a guard area for protecting an audio area during video data dubbing.

Here, the pre-SYNC and post-SYNC
17 are configured as shown in (1) and (2) of FIG. 17. The pre-SYNC is composed of two SYNC blocks, and the post SYNC is composed of one SYNC block. Then, in the sixth byte of the pre-SYNC, the SP / LP identification byte is recorded. This is FF
h indicates SP and 00h indicates LP. When the SP / LP flag recorded in the above-mentioned ITI area cannot be read, the value of the SP / LP identification byte of the pre-SYNC is adopted.

The audio data recorded in the area between the amble areas as described above is generated as follows. First, an audio signal for one track to be recorded is subjected to A / D conversion and shuffling, and thereafter, is subjected to framing and further added with parity. A format in which parity is added by performing this framing is shown in FIG.
(1). In this figure, 5-byte audio accompanying data (referred to as AAUX data) is added to the head of 72-byte audio data to form 77-byte data per block, and these are vertically stacked in 9 blocks for framing. Then, an 8-bit horizontal parity C1 and a vertical parity C2 corresponding to five blocks are added thereto.

The data to which the parity is added is read out in units of each block, and 3 bits are added at the head of each block.
A byte ID is added, and a 2-byte SYNC signal is inserted in the recording modulation circuit.
Is formed into a signal of 1 SYNC block having a data length of 90 bytes as shown in FIG. Then, this signal is recorded on the tape.

(3) VIDEO Area The video area has the same preamble and postamble as the audio area as shown in the enlarged part of FIG. However, it differs from that of the audio area in that the guard area is formed longer. Video data sandwiched between these amble areas is generated as follows.

That is, in the case of the SD system VTR for the NTSC system, the Y signal is AD-converted at a sample frequency of 13.5 MHz, and the color difference signal is AD-converted at a frequency of 1/4 thereof. The data of the effective scanning area for minutes is extracted. The extracted data for one frame is composed of 720 samples in the horizontal direction and 480 lines in the vertical direction with respect to the AD conversion output (DY) of the Y signal. The AD conversion output (DR) of the RY signal and the B-
The AD conversion output (DB) of the Y signal is composed of 180 samples in the horizontal direction and 480 lines in the vertical direction. These extracted data are divided into blocks of 8 samples in the horizontal direction and 8 lines in the vertical direction. FIG. 19A shows this blocking process for DY for one frame.

The same operation is performed on the color difference signals DR and DB to obtain one frame of blocked data as shown in FIG. However, in the case of a color difference signal, the block at the right end in this figure has only four samples in the horizontal direction, and therefore two vertically adjacent blocks are combined into one block. By the above blocking processing, a total of 8 for DY, DR, and DB per frame
100 blocks of 8 samples × 8 lines are formed. Note that a block composed of eight horizontal samples and eight vertical lines is called a DCT block.

Next, after the blocked data is shuffled according to a predetermined shuffling pattern, DCT is performed in DCT block units, followed by quantization and variable length coding. Here, the quantization step is set for every 30 DCT blocks, and the value of this quantization step is set so that the total amount of output data obtained by quantizing the 30 DCT blocks and performing variable length coding is equal to or less than a predetermined value. You. That is, the video data is transferred to the DCT block 30.
Fixed length for each piece. The data for 30 DCT blocks is called a buffering unit.

The data fixed in length as described above is subjected to framing together with video accompanying data (hereinafter referred to as VAUX data) for each data of one track, and thereafter, an error correction code is added. FIG. 20 shows a format in which the framing is performed and the error correction code is added.

In this figure, BUF0 to BUF26 each represent one buffering unit. Then, one buffering unit corresponds to (1) in FIG.
Has a structure divided into five blocks in the vertical direction, and each block has a data amount of 77 bytes.
An area Q for storing parameters related to quantization is provided in the first byte of each block.

Video data is stored in a 76-byte area following the quantized data. As shown in FIG. 20, VAUX data α and β corresponding to two blocks in the buffering unit are arranged above the 27 buffering units arranged in the vertical direction. At the bottom, VAUX data γ corresponding to one block is arranged, and a horizontal parity C1 of 8 bytes and a vertical parity C2 corresponding to 11 blocks are added to these framed data. Is done.

The signal to which parity has been added in this manner is read out in units of blocks, a 3-byte ID signal is added to the head of each block, and a 2-byte SYNC signal is inserted in the recording modulation circuit. You. This allows
For the video data block, a signal of 1 SYNC block having a data amount of 90 bytes as shown in (2) of FIG. 21 is formed, and for the VAUX data block, 1 SYNC block as shown in (3) of FIG. A block signal is formed. The signal for each 1 SYNC block is sequentially recorded on the tape.

In the framing format described above, since 27 buffering units representing video data for one track have data for 810 DCT blocks, data for one frame (for 8100 DCT blocks) is It is recorded in ten tracks separately.

(4) SUBCODE area The SUBCODE area is an area provided mainly for recording information for high-speed search.
It is shown in FIG. As shown in this figure, the SUBCODE area includes 12 SYNC blocks having a data length of 12 bytes, and a preamble and a postamble are provided before and after the SYNC block. However, a pre-SYNC and a post-SYNC are not provided unlike the audio area and the video area. And, in each of the 12 SYNC blocks,
A data section for recording 5-byte accompanying data (AUX data) is provided. Further, as the parity for protecting the 5-byte associated data, only the 2-byte horizontal parity C1 is used, and the vertical parity is not used.

The AUDIO area described above,
Each SYNC block forming the VIDEO area and the SUBCODE area is subjected to a 24/25 conversion at the time of recording modulation (by converting data of every 24 bits of a recording signal into 25 bits, a tracking control pilot frequency is converted into a recording code. Recording modulation system with component added)
Is performed, the recording data amount of each area becomes the number of bits as shown in FIG.

(5) Structure of ID section As is clear from the structure of each SYNC block shown in FIG. 17, FIG. 18, FIG. 21, and FIG.
UDIO area, VIDEO area, and SUBOCO
The SYNC block recorded in the DE area includes ID0, ID1 and IDP (IDP) after a 2-byte SYNC signal.
0, a parity that protects ID1)
It has a common structure in that a D portion is provided. In the audio area and the video area, the data structure of ID0 and ID1 in the ID section is determined as shown in FIG.

That is, in the ID1, the SYNC number in the track from the pre-SYNC of the audio area to the post-SYNC of the video area is stored in a binary number. And I
The track number in one frame is stored in the lower 4 bits of D0. Also, AAU is set in the upper 4 bits of ID0.
SYNC of X + audio data and video data
In the block, as shown in FIG.
The bit sequence number is stored.

On the other hand, the pre-SYNC block, the post-SYNC block, and the S of the parity C2 in the audio area are used.
In the YNC block, 3-bit ID data AP1 defining the data structure of the audio area is stored.
Also, a pre-SYNC block and a post S
In the YNC block and the SYNC block of the parity C2, 3-bit ID data AP2 that defines the data structure of the video area is stored (see (2) in this figure). The values of these AP1 and AP2 take "000" in the SD system VTR.

The above sequence number is "000
Twelve different numbers from "0" to "1011" are recorded for each frame. By looking at this sequence number, it can be determined whether or not the data obtained during variable speed playback is in the same frame. On the other hand, SUBCOD
The structure of the ID part of the SYNC block in the E area is defined as shown in FIG.

This figure shows the structure of each ID part of SYNC block numbers 0 to 11 for one track of the SUBCODE area, and the FR bit is provided in the most significant bit of ID0. This flag indicates whether or not it is the first five tracks of the frame, and takes a value of "0" in the first five tracks and "1" in the latter five tracks. The next three bits include S in the SYNC blocks whose SYNC block numbers are “0” and “6”.
The ID data AP3 that defines the data structure of the UBCODE area is recorded, and the SYNC block number “1” is recorded.
In the SYNC block of "1", ID data APT defining the data structure on the track is recorded, and in the other SYNC blocks, a TAG code is recorded. Note that the value of the AP3 is “0” in the SD system VTR.
00 ".

The TAG code includes three types of ID signals for search, as shown in an enlarged view in FIG.
That is, it is composed of an INDEX ID for a conventional INDEX search, a SKIP ID for cutting unnecessary scenes such as commercials, and a PP ID (Photo / Picture ID) for a still image search. The absolute number of the track (the continuous track number from the beginning of the tape) is recorded using the lower 4 bits of ID0 and the upper 4 bits of ID1. However,
As shown in this figure, one absolute track number is recorded using a total of 24 bits for three SYNC blocks. The SYNC block number of the SUBCODE area is recorded in the lower 4 bits of ID1.

In the SD system VTR, as described above, the accompanying data is recorded in each area defined on the tape. However, a memory IC is provided outside the cassette in which the tape is stored. Mounted circuit board,
The accompanying data is also recorded in this memory IC. When this cassette is mounted on the SD system VTR, the accompanying data written in the memory IC is read out to assist the operation and operation of the digital VTR. This memory IC is referred to as MIC (M
The data structure is not directly related to the problem of the present invention, and thus the description is omitted.

(7) Structure and Type of Pack As described above, in the SD system VTR, the AAUX area of the audio area on the tape, the VAUX area of the video area,
And auxiliary data are recorded in the AUX data recording area of the SUBCODE area, and each of these areas is constituted by a pack having a fixed length of 5 bytes.

Next, the structure and types of these packs will be described. The pack has a basic structure of 5 bytes shown in FIG. Of these 5 bytes, the first byte (PC0) is used as item data (also referred to as a pack header) indicating the content of the data. Then, the format of the succeeding 4 bytes (PC1 to 4) is determined corresponding to the item data, and arbitrary data is provided according to this format.

The item data is divided into upper and lower 4 bits, and the upper 4 bits are called a large item and the lower 4 bits are called a small item. The large item of the upper 4 bits is, for example, data indicating the use of the subsequent data, and the pack is packed with the control “0000” and the title “000” as shown in the table of FIG.
1 ", chapter" 0010 ", part" 0011 ",
Program "0100", audio auxiliary data (AAUX)
“0101”, image auxiliary data (VAUX) “011”
0, camera "0111", line "1000", and soft mode "1111".

Each group of packs expanded by a large item in this way is further expanded into 16 packs by smaller items (which represent, for example, the specific contents of subsequent data). Using these items, a maximum of 256 types of packs can be defined. The large items “1001” to “1110” in the table of FIG. 26 represent undefined portions left for addition. Therefore, by defining new item data (header) using an undefined item data code, new data can be arbitrarily recorded in the future. Further, since the contents of the data stored in the pack can be grasped by reading the header, the position on the tape where the pack is recorded can be set arbitrarily.

Next, a specific example of the pack will be described with reference to FIGS. (1) to (5) of FIG. 27 and FIG. 28
As can be seen from the item data, the pack shown in (1) belongs to the group of AAUX in FIG. 26, and is used to record accompanying data relating to audio. The contents of the recorded data are as follows.

That is, the AAUX shown in FIG.
The SOURCE pack includes a flag (L) indicating whether or not the audio sample frequency is locked with the video signal.
F) Number of audio samples per frame (AF
SIZE), number of audio channels (CH), mode information such as stereo / monaural for each audio channel (PA and AUDIO MODE), information on television system (50/60 and STYPE), presence / absence of emphasis (EF), emphasis Time constant (T
C), sample frequency (SMP), quantization information (QU)
Is recorded.

AAUX SOU shown in (2) of FIG.
The RCE CONTROL pack includes SCMS data (the upper bits indicate whether or not there is a copyright, and the lower bits indicate whether or not the original tape), copy source data (which indicates whether the signal is an analog signal source, etc.), copy generation data , Cipher (encryption) type data (CP), cipher data (CI), a flag (REC ST) indicating whether or not the frame is a recording start frame, a flag (REC END) indicating whether or not a recording last frame, original recording / after-recording / Recording mode data such as insert recording (REC MO
DE), a direction flag (DRF), playback speed data, and a genre category of the recorded content are recorded.

AAUX REC shown in (3) of FIG.
The DATE pack includes a flag “DS” indicating whether or not it is daylight saving time and a flag “T” indicating whether there is a time difference of 30 minutes.
M ", data" TIME ZONE "indicating a time difference, and data of day, day of the week, month, and year. (4) in the same figure
The AAUX REC TIME pack shown in
** hour ** minute ** second ** in SMPTE time code display
The data of the recording time of the frame is recorded. (4) in the figure
AAUX REC TIME BINARY shown in
In the GROUP pack, binary group data of SMPTE time code is recorded.

AAUX CL shown in FIG.
The OSED CAPTION pack contains the main audio, second
EDS (Extended) related to the language and type of voice
Data Service) is stored. The contents of these data are as follows. MAIN and 2ND AUDIO LANGUAGE: 000 = Unknown 001 = English 010 = Spanish 011 = French 100 = German 101 = Italian 110 = Others 111 = None MAIN AUDIO0N00 = 1000 Stereo 101 = Data Service 110 = Others 111 = None 2ND AUDIO TYPE: 000 = Unknown 001 = Mono 010 = Descriptive Video Ser
device 011 = Non-program Audio 100 = Special Effects 101 = Data Service 110 = Others 111 = None

Here, when a closed caption pack is recorded in an AAUX main area to be described later, the type of the main voice / second voice follows the information in the pack. Also, CLOSED is added to the AAUX main area.
If the CAPTION pack is not recorded and a pack without information (the details of this pack will be described later) is recorded instead, the type of the main audio / second audio is AUDIO in the AAUXSOURCE pack.
According to the information of MODE. (2) and (3) in FIG. 28,
Each of the packs shown in [1] to [5] in FIG.
As can be seen from the value of the item data, it belongs to the VAUX group in FIG. 26, and is used for recording accompanying data relating to an image.

The recorded contents of these packs will be described. The VAUX SOURC shown in FIG.
The E pack includes a channel number of a recording signal source, a flag (B / W) indicating whether the recording signal is a monochrome signal, a code (CFL) representing color framing, and whether the CFL is valid. A flag (EN), a code (SOURCE COD) indicating whether the recording signal source is a camera / line / cable / tuner / soft tape, etc.
E), data (50 /
60 and TYPE), and data (TUNER CATEGORY) relating to identification of UV broadcast / satellite broadcast and the like.

The VAUX SOU shown in [3] of FIG.
The RCE CONTROL pack includes SCMS data (the upper bits indicate whether or not there is a copyright, and the lower bits indicate whether or not the original tape is used), and ISR data (whether or not the immediately preceding recording signal is from an analog signal source. ), CMP data (representing the number of compressions), SS data (representing information such as whether or not the recording signal is scrambled), and a flag (REC indicating whether or not the frame is a recording start frame). ST), an HH flag indicating whether or not the signal to be recorded has a high-frequency HH signal component (if the signal is “0”, the HH signal component is present;
When “1” indicates that there is no HH signal component), recording mode data (REC MODE) such as original recording / after-recording recording / insert recording is recorded, and further, data (BCSYS and DIS) relating to the aspect ratio and the like are recorded.
P), a flag (F) regarding whether or not only the signal of one of the odd and even fields is output twice.
F), a flag (FS) regarding whether to output a field 1 signal or a field 2 signal during the field 1 period, and a flag regarding whether or not the image data of the frame is different from the image data of the previous frame ( FC),
A flag (IL) regarding whether or not the image is interlaced,
A flag (S) indicating whether or not the recorded image is a still image
T), a flag (SC) indicating whether or not the recorded image has been recorded in the still camera mode, and the genre of the recorded content are recorded.

The VAUX shown in [1] of FIG.
Data on the recording date is recorded in the REC DATE pack, and the VAUX REC shown in [2] of FIG.
Data relating to the recording time is recorded in the TIME pack, and the BINARY GROUP shown in [3] of FIG.
In the pack, data of a time code binary group is recorded. CLOSED CA shown in [4] of FIG.
The closed caption information transmitted during the vertical blanking period of the television signal is recorded in the PTION pack.

The VAUX TR pack [5] in the figure stores mainly system data transmitted during the vertical blanking period. The type of the system data to be recorded is the data type of the lower 4 bits of PC1.
Is defined as follows according to the value of 0000 = Video ID data 0001 = WSS data 0010 = EDTV-2 ID in 22 line 0011 = EDTV-2 ID in 285 lin
e 1111 = No information Other = Reserved

As a special example of a pack, a pack with an item code of all 1s is a pack with no information (No I
nformation pack). As can be seen from the above description, in the SD system VTR, the structure of the accompanying data is a pack structure common to each area as described above, so that software for recording and reproducing these data can be shared, Processing is simplified.

Further, since the timing at the time of recording / reproducing becomes constant, there is no need to provide an extra memory such as a RAM for time adjustment, and the development of the software is not required even when a new model is developed. It can be done easily. Further, by adopting the pack structure, for example, even when an error occurs during reproduction, the next pack can be easily taken out. Therefore, a large amount of data is not destroyed due to propagation of an error.

(8) Structure of Associated Information Recording Area Next, a specific structure of the data area of the AAUX area, the VAUX area, and the SUBCODE area in which various kinds of associated data are recorded using the pack will be described.

The AAUX area In the AAUX area, 1SY shown in (2) of FIG.
5 bytes AA in NC block format
One pack is constituted by the UX area. Therefore, AA
The UX area is composed of nine packs per track. In the SD system VTR, one frame of data is recorded on ten tracks, so the AAUX area for one frame is represented as shown in FIG.

In this figure, one section represents one pack. The letters A to F written in the sections are
The six packs shown in (1) to (5) of FIG. 27 and (1) of FIG. 28 are shown, and these six types of packs are called main packs. The area in which these main packs are recorded is called an AAUX main area. The other area is called an AAUX optional area, and an arbitrary pack can be selected from various packs and recorded.

VAUX Area For the VAUX area, the VAU area in one track
As shown in FIG. 20, the X area is composed of three SYNC blocks α, β, and γ.
As shown in FIG. 1, 15 pieces per SYNC block,
There are 45 tracks in one track. The 2-byte area immediately before the error code C1 in one SYNC block is used as a spare recording area.

For a VAUX area for one frame,
FIG. 32 shows the pack configuration. In this figure, packs indicated by letters A to E represent five packs indicated by (2) and (3) in FIG. 28 and [1] to [3] in FIG. 29, and are indicated by F1 to F5. As the pack to be recorded, either the pack of [4] or [5] in FIG. 29 is recorded. These packs A to E and F1 to F5
Constitutes a VAUX main area. As shown in this figure, the main area has the same track pairs 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 of the tracks. It has the feature that the main pack is recorded. The other area constitutes a VAUX optional area.

As shown in FIG. 22, the data area of the SUBCODE area is a data area of the SUBCODE area.
Five bytes are written into the C block, each of which forms one pack. That is, 12 packs are recorded on one track, and SYNC block numbers 3 to
Packs 5 and 9 to 11 constitute the main area, and the other packs constitute the optional area.

One frame of data in the SUBCODE area is repeatedly recorded in a format as shown in FIG. In this figure, uppercase alphabets represent packs in the main area, in which data necessary for high-speed search such as time code and recording date is recorded. The lower case alphabet indicates a pack in an optional area, and an arbitrary pack can be selected and arbitrary data can be recorded in this area. However, there is a feature that the packs a to m in the optional area are repeatedly recorded with regularity as shown in the figure.

This figure shows the SUBCODE pack structure of the SD system VTR for the NTSC system.
In the case of the SD system VTR for the AM system, one frame is one.
It is composed of two tracks, and its SUBCODE pack structure is as shown in FIG. That is, only the number of repetitive recordings increases. The main area in each area described above is characterized in that a pack storing auxiliary information on basic data items common to all tapes is recorded. On the other hand, a soft tape maker or a user can freely write arbitrary accompanying data in the optional area. Such additional information includes, for example, various character information, teletext signal data, various system data in a vertical blanking period, television signal data of an arbitrary line in an effective scanning period, and computer graphic. And other data.

(9) Application ID System The recording format of the SD system VTR has been described above. However, this format is not limited to the SD system VTR, and can be easily developed as various digital signal recording / reproducing devices. Basic design. The ID data APT, AP1 to AP3, and the ID data APM recorded in the MIC appearing in the description of the format described above play a role of enabling development to such various digital signal recording devices. The ID data is collectively stored in the application I
Called D.

Then, next, the application ID
A supplementary explanation of the system will be given. It should be noted that the application ID described above is an I
It is an ID that merely determines the data structure of the area of the recording medium instead of D. APT and APM have the following meanings as described above. APT: Determines the data structure on the track. APM: Determines the data structure of the MIC.

That is, first, the data structure on the track in the digital signal recording / reproducing apparatus is defined by the value of APT. That is, the track after the ITI area is divided into several areas as shown in FIG. 35 according to the value of the APT, and the positions on those tracks, the SYNC block configuration, and the ECC for protecting data from errors are provided.
The data structure such as the configuration is uniquely determined. Further, each area has an application ID that determines the data structure of that area. The meaning is as follows. Application ID of area n: Determines the data structure of area n.

Then, the application ID on the tape
Has a hierarchical structure as shown in FIG. That is, the area on the track is defined by the original application ID APT, and AP1 to AP
n is defined. The number of areas is defined by the APT. In FIG. 36, two layers are shown, but a layer may be further provided if necessary. Thus, APT, AP
By designating the values of 1 to APn, the specific signal processing configuration of the digital signal recording / reproducing apparatus and the use of the apparatus are specified.

The APM, which is the application ID in the MIC, has only one layer, and the same value as that of the APT is written by the digital signal recording / reproducing apparatus. With this application ID system,
By using the above-mentioned digital VTR with its cassette, mechanism, servo system, ITI area generation / detection circuit, etc. as it is, a completely different product group such as a data streamer or a multi-track digital audio tape recorder is made. It is possible. Even if one area is determined, its contents can be further defined by the application ID of that area.
A very wide range of merchandise development is possible, such as video data for one application ID value, video / audio data, or computer data for another value.

Next, a specific example in the case where the value of the application ID is specified will be described. First, APT = 0
The state at 00 is shown in FIG. At this time, area 1, area 2, and area 3 are defined on the track. The position on the track, the SYNC block configuration, the ECC configuration for protecting data from errors, the gap for guaranteeing each area, and the overwrite margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of that area. The meaning is as follows.

AP 1... The data structure of area 1 is determined. AP2: Determine the data structure of area 2. AP3: Determine the data structure of area 3. And the Application ID of each area
Is defined as 000 as follows.

AP1 = 000: Audio of a digital VTR for image compression recording system for consumer use, AP2 adopting AAUX data structure AP2 = 000: AP3 of audio for image compression recording system for digital VTR for consumer use, AAUX adopting data structure of AAUX = 000... Adopts the data structure of the sub-code and ID of the image compression recording system consumer digital VTR. That is, when implementing the image compression recording system consumer digital VTR, APT, AP1, AP2, AP3 = 000
It becomes. At this time, the APM naturally becomes 000.

2. Recording Circuit of SD System VTR In the SD system VTR, recording on a tape is performed in accordance with the recording format described above. Next, a specific configuration and operation of a recording circuit for performing such recording will be described. FIG. 38 shows a configuration of such a recording circuit.

In this figure, the input Y, RY,
Each of the R-Y component signals is supplied to an A / D converter 42, and the Y signal is also supplied to a synchronization separation circuit 44, where the separated synchronization signal is supplied to a clock generator 45.
Supplied to The clock generator 45 is an A / D converter 42
And a clock signal for the blocking / shuffling circuit 43.

The component signal input to the A / D converter 42 is 13.5 MHz for the Y signal and 1 for the color difference signal.
A / D conversion is performed at a sampling frequency of 3.5 / 4 MHz. Then, of these A / D conversion outputs, only the data DY, DR, and DB in the effective scanning period are supplied to the blocking / shuffling circuit 43.

This blocking / shuffling circuit 43
In the above, as described above, the valid data DY, DR, DB
Is converted into a block consisting of 8 samples in the horizontal direction and 8 lines in the vertical direction.
DR and DB blocks are shuffled to increase the compression efficiency of image data and disperse errors during reproduction in units of a total of six blocks, one for each of the DR and DB blocks. Supplied.

The compression encoding unit performs a D / D conversion on the input block data of eight samples in the horizontal direction and eight lines in the vertical direction.
A compression circuit 46 for performing CT (Discrete Cosine Transform), an estimator 48 for estimating whether the result has been compressed to a predetermined data amount, and finally a quantization step is determined based on the determination result, and the variable length coding is performed. And a quantizer 47 for performing data compression using. The output of the quantizer 47 is framed by the framing circuit 49 into the format described in FIG.

The mode processing microcomputer 67 in FIG.
Is a microcomputer having a man-machine interface with humans, and operates in synchronization with the frequency of vertical synchronization of television signals. Further, the signal processing microcomputer 55 operates on the side closer to the machine, and has a rotation speed of 9 drums.
It operates in synchronization with 000 rpm and 150 Hz.

Then, VAUX, AAUX, SUBCO
The pack data of each area of the DE is basically generated by the mode processing microcomputer, and the absolute track number stored in the “title end” pack or the like is generated by the signal processing microcomputer 55, and is later fitted to a predetermined position. Is executed. The time code data stored in the SUBCODE is also generated by the signal processing microcomputer 55.

These results can be obtained from the interface VAUX IC 5 which is provided between the microcomputer and the hardware.
6. IC57 for SUBCODE and IC58 for AAUX
Given to. The VAUX IC 56 combines the output of the framing circuit 49 with the combiner 50 at an appropriate timing. Further, the SUBCODE IC 57 includes AP3, S
SID, which is the ID of UBCODE, and SUBCODE
Is generated.

On the other hand, the input audio signal is converted by the A / D converter 51 into a digital audio signal. In addition, at the time of A / D conversion of a video signal and an audio signal, although not shown in this figure, it is necessary to provide an LPF corresponding to the sampling frequency in a preceding stage of the sampling circuit. The A / D-converted audio data undergoes data distribution processing by a shuffling circuit 52, and is then framed by a framing circuit 53 into the format described in FIG. At this time AA
The UX IC 58 generates the AAUX pack data, measures the timing, and packs them in a predetermined location in the audio SYNC block by the synthesizing circuit 54.

Next, a pack data recording circuit will be described using VAUX as an example. FIG. 39 shows the overall flow. First, the mode processing microcomputer 67 generates pack data to be stored in the VAUX. The data is converted into serial data by the P / S conversion circuit 118 and sent to the signal processing microcomputer 55 according to the communication protocol between the microcomputers. Here, the data is converted back to parallel data by the S / P conversion circuit 119 and stored in the buffer memory 123 via the switch 122.

The header part at the head of every five bytes of the transmitted pack data is used as the pack header detection circuit 120.
And check if the pack is a pack that requires an absolute track number. Switch 122 if necessary
To switch the absolute track number generation circuits 121 to 23
Stores bit absolute track number data.

Here, the circuit 119 is a serial I / O in the microcomputer, the circuits 120, 121 and 122 are constituted by microcomputer programs, and the circuit 123 is a RAM in the microcomputer. In this way, the processing of the pack structure uses a microcomputer which is advantageous in cost because the processing time of the microcomputer is sufficient even if the processing is not performed by hardware. The data stored in the buffer memory 123 in this way is VA
Write-side timing controller 12 of UX IC 56
According to the instruction from 5, the information is sequentially read. At this time, the switch 124 is switched for the first six packs for the main area and for the subsequent 390 packs for the optional area.

The FIFO 126 for the main area is 30 bytes, and the FIFO 127 for the optional area is 1950.
Has the capacity of a byte. When only one type of TR pack or Closed Caption pack is recorded in the sixth pack of each main area, it is necessary to write to the main area FIFO 126 for each track pair.

The VAUX is stored at the SYNC numbers 19, 20, and 156 in the track as shown in [1] of FIG. Also, the track numbers in the frame are 1, 3,
At 5, 7, and 9, the main area is in the first half of SYNC number 19 with + azimuth, and the track number in the frame is 0,
At 2, 4, 6, 8-azimuth with SYNC number 156
There is a main area in the second half. This is drawn together in one video frame is [2] in FIG. As described above, the time when the timing signal nMAIN = “L” is the main area. Such a signal is generated by the read-side timing controller 129, the switch 128 is switched, and the output is passed to the synthesis circuit 50.

[0092] In the sixth pack of each main area, TR
When recording only one type of pack or Closed Caption pack, when nMAIN = “L”, the data of the main area FIFO 126 is repeatedly read 10 times (525/60) or 12 times (625/50). Good. TR Pack and Closed Capti
When a plurality of on-packs are recorded, the data is written in the main area FIFO 126 for each track. Therefore, when nMAIN = “L”, the main area FIFO
The data of O126 is read twice. This is because the VAUX main area always has the same value for each track pair. When nMAIN = “H”, the optional area FIFO 127 is read. It reads only once per video frame.

[0093] Actually, the TR pack or the Close
Since a plurality of d Caption packs are often recorded, six main pack data are written into the main area FIFO 126 for each track pair. Each track pair is an actual track pair write time, and data for one track is written once during that time. This is because the time required for the processing by the signal processing microcomputer 55 and the mode processing microcomputer 67 is not enough just for the time for writing one track, so that the time for two tracks is secured by the above-described procedure.

FIG. 41 mainly shows a pack data generating section in the mode processing microcomputer. First of all, the circuit is roughly divided
It is divided into main area and optional area.
The circuit 131 is a main area data collection and generation circuit. Data as shown in the figure is received from a digital bus or tuner, and a data group as shown at 139 is generated internally. Assemble this into the bit byte structure of the main pack, add the pack header by switch 132,
The signal is input to the P / S conversion circuit 118 via the switch 136.

The optional area data collection and generation circuit 133 receives, for example, TELETEXT data and a program title from a tuner, and generates pack data storing these. The VTR set determines which optional area is to be recorded. The pack header is set by the circuit 134 and added by the switch 135, and the P / S conversion circuit 1
Input to 38. These timings are performed by the timing adjustment circuit 137. Again, as mentioned earlier, circuit 1
Reference numeral 18 denotes a serial I / O in the microcomputer, and the circuits 131 to 137 are configured by a microcomputer program.

The generator 59 in FIG.
Each ID part of V (Audio / Video) and pre-SYN
C, post-SYNC is generated. Here, AP1,
AP2 is also generated and inserted into a predetermined ID portion. The output of the generator 59, ADATA (AUDIO DATA), VDA
TA (VIDEO DATA), SID (SUBCOD
E ID), SDATA (SUBCODE DATA)
Are switched by the first switching circuit SW1 while watching the timing.

The output of the first switching circuit SW 1 is added with a predetermined parity in a parity generation circuit 60, and a random number generation circuit 61 and a 24/25 conversion circuit 62
Supplied to Here, the randomizing circuit 61 converts input data into random numbers in order to eliminate DC components of the data. Also, 2
The 4/25 conversion circuit 62 performs a process of adding one bit to every 24 bits of data to give a pilot signal component and a precoding process (partial response class IV) suitable for digital recording.

The data thus obtained is supplied to the synthesizer 63, where the A / V SYNC and SUBCODE
The audio, video and SUBCODE SYNC patterns generated by the SYNC generator 64 are synthesized.
The output of the synthesizer 63 is supplied to the second switching circuit SW2. The ITI data output from the ITI generator 65 and the amble pattern output from the amble pattern generator 66 are also supplied to the second switching circuit SW2. These randomization circuits 61 and 24/25 conversion circuits 6
2. A channel encoder is configured by the synthesizer 63 and the switch SW2.

The APT, SP / LP, and PF data are supplied from the mode processing microcomputer 67 to the ITI generator 65. The ITI generator 65 fits these data into a predetermined position of the TIA to form a second switching circuit SW2.
Supply to Therefore, by switching the switching circuit SW2 at a predetermined timing, the amble pattern and the ITI data are added to the output of the combiner 63. The output of the second switching circuit SW2 is amplified by the recording amplifiers 201 and 204, and the minus azimuth recording head 202 and the plus azimuth recording head 20 are amplified.
3 is recorded on a magnetic tape (not shown).

The mode processing microcomputer 67 has a digital VT
The mode management of the entire R is performed. A third switching circuit SW3 connected to this microcomputer is a group of switches for instructing not only a recording operation and a reproducing operation but also various other operations outside the VTR main body.
A P / LP recording mode setting switch is also included. The setting result by this switch group is stored in the mode processing microcomputer 67.
And supplied to the signal processing microcomputer 55, the MIC microcomputer 69, and the mechanical control microcomputer by communication between the microcomputers.

The above-described series of recording operations are performed mainly by the mode processing microcomputer 67 in cooperation with the mechanical control microcomputer or the signal processing microcomputer 55 and the IC in charge of each part.
The MIC microcomputer 69 is a MIC processing microcomputer. Here, pack data, APM, and the like in the MIC are generated and provided to the MIC 68 in a MIC-equipped cassette (not shown) via MIC contacts (not shown).

3. Reproduction circuit of SD system VTR Details of the reproduction circuit of the SD system VTR are shown in FIGS.
This will be described with reference to FIG. In FIG. 42, weak signals reproduced from a magnetic tape (not shown) by reproduction heads 991 and 994 are amplified by head amplifiers 992 and 993 and applied to an equalizer circuit 71. The equalizer circuit 71 performs an inverse process of an emphasis process (for example, a partial response class IV) performed for improving electromagnetic conversion characteristics between a magnetic tape and a magnetic head during recording.

The clock CK is extracted from the output of the equalizer circuit 71 by the clock extracting circuit 72. The clock CK is supplied to the A / D converter 73, and the output of the equalizer circuit 71 is converted into a digital value. The 1-bit data thus obtained is written into the FIFO 74 using the clock CK. This clock CK is a temporally unstable signal including a jitter component of the rotating head drum. However, since the data itself before A / D conversion also includes a jitter component, there is no problem in sampling itself. However, when extracting image data or the like from this point, since the data cannot be extracted unless the data is stable over time, the time axis is adjusted using the FIFO 74. That is, writing is performed with an unstable clock, while reading is performed with a stable clock SCK from a self-excited oscillator (not shown) using a crystal oscillator or the like. The depth of the FIFO 74 should be large enough to prevent the data from being read out faster than the input speed of the input data.

The output of each stage of the FIFO 74 is applied to a SYNC pattern detection circuit 75. Here, the SYNC pattern of each area is switched by the fifth switching circuit SW5 and given by the timing circuit 79. The SYNC pattern detection circuit 75 has a flywheel configuration. Once a SYNC pattern is detected, the same SYNC pattern is again set after a predetermined SYNC block length.
See if a YNC pattern comes. For example, 3
The configuration is considered to be true if it is correct more than once to prevent erroneous detection. The depth of the FIFO 74 is necessary for several minutes.

When the SYNC pattern is detected in this way, the shift amount is determined as to which part should be extracted from the output of each stage of the FIFO 74 to extract one SYNC block, and the fourth switching circuit is determined based on the shift amount. SW4 is closed, and necessary bits are taken into the SYNC block determination latch 77. As a result, the captured SY
The NC number is extracted by the SYNC number extraction circuit 78 and supplied to the timing circuit 79. This read S
Since the position on the track where the head is scanning can be known from the YNC number, the fifth switching circuit SW5 and the sixth switching circuit SW6 are switched accordingly. The above circuits 72 to 75 and 77 to 79 constitute a so-called time base collector (TBC).

The sixth switching circuit SW 6 is switched to the lower side when the head is scanning the ITI area. The sixth switching circuit SW 6 removes the ITISYNC pattern by the subtracter 80 and adds it to the ITI decoder 81. Note that a decoder constituted by the subtracter 80 and the ITI decoder is referred to as a channel decoder A. Since the ITI area is coded and recorded, the APT, SP / LP, and PF data can be extracted by decoding it. These data are given to the mode processing microcomputer 82. The mode processing microcomputer 82
Is connected to a seventh switching circuit SW7, which is a switch group for inputting various commands such as the SP / LP mode. The mode processing microcomputer 82 has a digital V
The operation mode and the like of the entire TR are determined, and system control of the entire set is performed in cooperation with the mechanical control microcomputer 85 and the signal processing microcomputer 100 in FIG.

The mode processing microcomputer 82 is connected to an MIC microcomputer 83 for managing APM and the like. MIC
The information from the MIC 84 in the cassette (not shown) is provided to this MI via an MIC contact switch (not shown).
It is given to the C microcomputer 83 and performs MIC processing while sharing the role with the mode processing microcomputer 82. In some sets, the MIC microcomputer 83 may be omitted, and the MIC processing may be performed by the mode processing microcomputer 82.

When the head is scanning the audio area, the video area, or the SUBCODE area, the sixth switching circuit SW6 is switched to the upper side. After the SYNC pattern of each area is extracted by the subtractor 86, the data is passed through a 24/25 inverse conversion circuit 87, further applied to an inverse random number generation circuit 88, and returned to the original data string (these subtractors 86 and 24/25). A decoder constituted by the inverse conversion circuit 87 and the inverse random number generation circuit 88 is referred to as a channel decoder B.) The data thus extracted is added to the error correction circuit 89.

The error correction circuit 89 detects and corrects error data by using the parity added on the recording side.
Output with flags. Each data is switched and output by the eighth switching circuit SW8. AV
The ID, pre-SYNC, and post-SYNC extraction circuits 90
A / V area, SYNC number, track number stored in pre-SYNC and post-SYNC, and pre-S
The SP / LP signals stored in the YNC are extracted. These are given to the timing circuit 79 and used to generate various timings. In the extraction circuit 90, AP1 and AP2 are also extracted and supplied to the mode processing microcomputer 82 for checking. AP
When 1, AP2 = 000, the operation is normal, but when the value is other than that, a warning operation such as a warning process is performed.

For the SP / LP, the mode processing microcomputer 82 performs a comparison study with the one obtained from the ITI.
In the ITI area, three times SP /
LP information is written, and a majority vote is taken alone to improve reliability. The pre-SYNC has 2 SYNCs each for audio and video, and SP / LP information is written at four places in total. Here, too, a majority vote is taken to improve reliability. If the two do not finally match, the one in the ITI area is preferentially adopted.

VDATA output from the eighth switching circuit SW8 is divided into video data and video accompanying data by the ninth switching circuit SW9 shown in FIG. Then, the video data is supplied to the deframing circuit 94 together with the error flag. The deframing circuit 94 performs the inverse conversion of the framing on the recording side, and grasps the nature of the data packed therein. Then, when there is an error that cannot be removed from certain data, the propagation error processing is performed here because it is understood how the error affects other data.
As a result, the ERROR flag becomes a VERROR flag including a new propagation error. Further, even if the data has an error and is not important for image reproduction, the deframing circuit 94 also performs a process for modifying the image data to remove the error flag.

The video data is returned to the data before compression through the inverse quantization circuit 95 and the inverse compression circuit 96. Next, the data is returned to the original image space arrangement by the deshuffling / deblocking circuit 97. Only after the data is returned to the real image space can the image be repaired based on the VERROR flag. That is, for example, a process is performed in which the image data of one frame before is always stored in the memory, and the image block in which the error occurred is substituted with the previous image data.

Now, after deshuffling, DY, DR,
Data is divided into three systems of DB and handled. The D / A converters 101 to 103 return the analog components to Y, RY, and BY. Clock at this time, 13.5MH _Z for Y, R-Y, the B-Y are 3.375
MH _Z.

The three signal components thus obtained are represented by Y /
C is synthesized in the C synthesizing circuit 104,
At 5, the composite video signal is synthesized with the composite synchronization signal from the synchronization signal generation circuit 93, and output from the terminal 106 as a composite video signal.

ADATA output from the eighth switching circuit SW8 is divided into audio data and audio accompanying data by the tenth switching circuit SW10 shown in FIG. The audio data is sent to the deframing circuit 107 together with the ERROR flag.
Given to.

The deframing circuit 107 performs the inverse conversion of the framing on the recording side, and grasps the nature of the data packed therein. Then, when there is an error that cannot be removed from certain data, the propagation error processing is performed here because it is understood how the error affects other data. For example, at the time of 16-bit sampling, since one data is in units of 8 bits, one ERROR flag indicates that an AER flag newly including a propagation error is included.
It becomes a ROR flag.

The audio data is returned to the original time axis by the next deshuffling circuit 108. At this time, the audio data is repaired based on the AERROR flag. In other words, processing such as a previous value hold in which the sound immediately before the error is substituted is performed. The error period is too long,
If the repair is not effective, the sound itself will be stopped by taking measures such as muting.

After performing such a treatment, the D / A converter 1
The value is returned to the analog value by 09, and is output from the analog audio output terminal 110 while taking timing such as lip sync with the image data. Now, the data of VAUX and AAUX separated by the ninth switching circuit SW9 and the tenth switching circuit SW10 are as follows:
IC for VAUX98 and IC111 for AAUX respectively
Performs pre-processing such as majority processing while also referring to the error flag.

The ID data SID and the pack data SDATA of the SUBCODE area output from the eighth switching circuit SW8 are stored in the SUBCODE IC11.
2, and also performs preprocessing such as majority processing while referring to the error flag. The data on which these pre-processes have been performed are then provided to the signal processing microcomputer 100 to perform a final reading operation. The errors that could not be removed in the pre-processing are VAUXE
The signals are given to the signal processing microcomputer 100 as R, SUBER, and AAUXER.

Here, the SUBCODE IC 112 is the AP
3, and the APT are extracted and passed to the mode processing microcomputer 82 via the signal processing microcomputer 100 for checking. The mode processing microcomputer 82 outputs A
A based on PT and APT from SUBCODE
The value of PT is determined, and when this value is not “000”, an operation such as a warning process is performed. When AP3 = 000, normal operation is performed. When the value is other than that, a warning operation such as a warning process is performed.

Here, supplementing the error processing of the pack data, each area has a main area and an optional area. Since the same data is written a plurality of times in the main area, even if some of them have an error, the ERROR flag is no longer an error because the data can be supplementarily reproduced with other data.
However, since data is written once for optional areas other than SUBCODE, the error remains
XER and AAUXER will remain.

The signal processing microcomputer 100 further performs a propagation error process, a data repair process, and the like by analogy with the context of each data pack. The result of this determination is given to the mode processing microcomputer 82, and is used as a material for determining the behavior of the entire set. Next, take VAUX as an example.
The following describes a pack data reproducing circuit in the IC for use 98 and the signal processing microcomputer 100. Here, a description will be given of a configuration example using a simple processing method in which an error is not written to a memory in the case of an error, instead of the majority processing as preprocessing. FIG. 44 shows a circuit example of the VAUX IC 98.
First, the VAUX pack data coming from the switching circuit SW9 is sent to the nM in FIG.
By switching the switch 141 at the timing of AIN = “L”, the data is distributed to the main area memory 145 and the optional area FIFO 148.

The pack data in the main area is read by the pack header detection circuit 143 and the switch 144 is switched. Then, the data is written to the main area memory only when it is not ERROR. This memory has a 9-bit configuration, and the shaded portions in the figure are bits for storing error flags. As the initial setting of the main area memory, the value of the sixth main pack data storage area is set to all 1 (= no information) every two tracks, and the first to fifth main pack data storage areas are set. Is set to all 1 (= no information) for each video frame. And if it is ERROR, do nothing, ERROR
If it is not R, the data is written and 0 is written to the error flag. Since the same data is recorded in units of two tracks in the sixth pack in the main area, a point where the error flag is set to 1 at the end of two tracks is finally recognized as an error. Regarding the first to fifth main packs, the error flag = 1 is recognized as an error at the end of one video frame.

Since the optional area is basically written once, the ERROR flag is written as it is to the optional area FIFO 148 together with the data. These are sent to the signal processing microcomputer 100 via switches 146 and 147 switched by the read-side timing controller 149. The signal processing microcomputer 100 analyzes the received pack data and the error flag.
The processing operation in the signal processing microcomputer 100 will be described with reference to FIG. In this figure, the pack header identification circuit 150 sorts the pack data (VAUXDT) sent from the VAUX IC 98 and stores it in the memory 151. This does not particularly distinguish between the main area and the optional area.

For a pack in the main area, VAU
As with the IC 98 for X, when the error flag “1” is set in VAUXER, the writing process is not performed. As a result, repair can be performed with a value at least one video frame before. Since the content of the main area is considered to have a very strong correlation with the value one video frame before, there is no particular problem even if this processing is substituted.

On the other hand, in the case of a pack in the optional area, since it is considered that there is no correlation with the value one video frame before, the error propagation processing is performed for each pack.
This method is basically performed by changing the data to a "pack without information" in which all data is FFh if there is an error in the 5-byte fixed-length pack data. . For example, in the case of a “Teletext” pack in which Teletext data is stored,
Due to the relationship that the packs continue, even if there is an error in the pack header between them, it can be easily replaced with a Telext pack header. Even if there is an error in the data portion, if there is no error in the pack header, the pack is not changed to the "pack without information".
This will restore the Teletext data,
Since it is left to the parity check of the ext decoder, the data is left as it is even if an error is found.

That is, in the SD system VTR, FIG.
Although the description is omitted in the reproduction circuit of FIG. 1, pack data having a large data amount such as text data and Teletext data and having a characteristic as a series of data sequences are respectively processed by the signal processing microcomputer 10.
0 to a dedicated data processing circuit for more efficient error correction,
2 to reduce the load.

An error flag does not already exist in the data prepared by the processing in the signal processing microcomputer 100 as described above. These are converted into serial data by the P / S conversion circuit 152 and sent to the mode processing microcomputer 82 according to the communication protocol between the microcomputers. Where S / P
The data is converted back to parallel data by the conversion circuit 153, and the packed data is analyzed and analyzed.

Here, the circuits 150 and 155 and the switch 154 are constituted by a microcomputer program, the memory 151 is a memory inside the microcomputer, and the circuits 152 and 153 are serial I / Os inside the microcomputer. In the disassembly and analysis of the pack data in the mode processing microcomputer 82, the pack data is analyzed based on the determined pack header, and various control information and display information obtained as an analysis result are respectively controlled by control circuits and display circuits. Supply to

[2] HD VTR Next, an embodiment of the HD VTR according to the present invention will be described. The HD system VTR is one unit faster than the SD system VTR.
Except that the number of recording tracks per frame is doubled, its basic format has almost the same data structure as the SD VTR format. That is, the overall data structure of one track is the same as that of FIG. 16, the configuration of pre-SYNC and post-SYNC of FIG. 17, the audio format of FIG. 18, FIGS.
The video format 1 is also common to the HD system VTR. In the SD system VTR, [1] in FIG.
As shown in FIG. 2, recording or reproduction is performed using two heads facing each other at 180 degrees, while HD system V
In the TR, as shown in [2] of the figure, recording or reproduction is performed using a total of four heads, two heads each facing 180 degrees. That is, in the HD system VTR, recording is simultaneously performed on two adjacent tracks using a minus azimuth head and a plus azimuth head, and the tape speed is set to twice that of the SD system VTR. .

Therefore, in the HD system VTR, most of the specific circuit configuration is replaced by a processing circuit in the SD system VTR.
It is possible to configure by providing the same number of channels, so that so-called upward compatibility enabling recording of a television signal by the SD system or reproduction of the tape recorded by the SD system in the HD system VTR is easily performed. Can be

In the present embodiment, an HD VTR having higher compatibility is constructed in consideration of such characteristics. The recording circuit and the reproducing circuit of the HD VTR of the present embodiment will be described below. However, a specific circuit operation will be described in detail in addition to the description of the data structure of the recording area of the accompanying data, which is one of the features of the present embodiment. First, differences in the data structure in the recording format will be described.

1. Audio data recording area This recording area has two recording tracks for one frame.
There is no fundamental change, only a doubling. Specifically, since the recording capacity is doubled, the amount of audio data to be recorded is reduced by two.
For example, in an SD system VTR, the sampling frequency is 48 KHz and the number of quantization bits is 16
When recording PCM audio in bits, audio for two channels can be recorded. However, when recording similar PCM audio in an HD VTR, audio for four channels can be recorded. Become. Note that the recording structure of the accompanying data is merely twice as large as that of the SD system VTR, and the basic data structure is not changed. For reference, FIG. 47 shows the data structure of one frame of AAUX data.

[0134] 2. Image data recording area In this recording area, image data for one frame of a 1125/60 television signal is data-compressed and stored so as to be recorded on 20 tracks, and the sample frequency of the image data and the data compression are stored. Rate is SD system VTR
However, the basic structure of the image data of one sync block does not change.

The data structure of the VAUX area is unique to this embodiment in order to enhance compatibility when performing recording / reproducing by the SD system, and is configured as shown in FIG. That is, as is apparent from this figure, the plus azimuth recording head and the minus azimuth recording head that simultaneously perform recording always record the same main area data and optional area data, and particularly, on the track. The data in the main area is the same for two track pairs. Thus, for example, if only the recording data by the minus azimuth head is viewed, it has the same data structure as the VAUX data in the SD system VTR, and the compatibility at the time of recording by the SD system is improved.

A description will be given of the process of reproducing the VAUX data recorded in the above data format.
As shown in [1] of FIG. 2, dedicated VAUX ICs 808 and 810 for processing a reproduction signal from the minus azimuth head and a reproduction signal from the plus azimuth head are provided in parallel, and output from these ICs. VAUXDT1 and VAUXDT2 are input to the signal processing microcomputer 809, and the microcomputer integrates these two input data VAUXDT1 and VAUXDT2 to derive correct definite data as shown in [2] of FIG. Transmit to the processing microcomputer. As described above, in the present embodiment, the number of times of repeated recording of the same data is doubled as compared with the case of the SD system VTR, so that the reliability of the reproduced data is increased.

3. FIG. 3 shows the data structure of one frame in the SUBCODE area SUBCODE. As is apparent from a comparison between this figure and SUBCODE in the SD system VTR shown in FIG. The SUBCODE data is equivalent to the SUBCODE data described above, and compatibility in the case of performing recording and reproduction by the SD system using the HD system VTR of the present embodiment is considered. For reference, FIG. 4 shows data reproduced by a minus azimuth head, and FIG. 5 shows data reproduced by a plus azimuth head.

In the reproduction processing of these SUBCODE data, as shown in [1] of FIG.
DE ICs 811 and 812 are provided in parallel, and SUBDT1 and SUBDT2 output from these ICs are input to a signal processing microcomputer 809. In this signal processing microcomputer, a main area shown in [2] of FIG. The fixed data of the optional area is derived, and these data are transmitted to the mode processing microcomputer.

4. Recording Circuit of HD VTR Next, a recording circuit of the HD VTR and its signal processing operation will be described with reference to FIG. 7 and FIG. In FIG. 7, an input 1125/60 television signal is YC-separated, and AD-converted by AD conversion circuits 942 to 944. Here, the sample frequency of the Y signal is 40.5 MHz, and the sample frequency of the color difference signal is 13.5 MHz. And this HD system V
In TR, sampling is performed in a 12: 4: 0 format. That is, the color difference signal is converted into a line sequential signal and recorded. These AD conversion outputs are supplied to the blocking circuit 947 at 8 samples × as shown in FIG.
It is divided into blocks of 8 lines.

As shown in this figure, 1125/60
The data for one frame of the Y signal in the system is composed of 1024 lines with 1008 samples per line.
The data for one frame of the color difference signal is one line 33.
It consists of 1024 lines with 6 samples. These blocked data are shuffled in a predetermined pattern in the next circuit 948 for shuffling and compression encoding, and further compressed. The data compressed here is divided into odd-numbered track data and even-numbered track data, input to the next framing circuits 951 and 952, and S shown in FIG.
Framing is performed in the same manner as the framing format in the D system VTR.

Here, data of 40 DCT blocks are compressed and stored in one buffering unit. The odd track data and the even track data extracted by the parallel processing are combined with the synthesizing circuit 959.
And 960 are combined with VAUX data from VAUX ICs 954 and 955, respectively, and VDAT
A1 and VDATA2 are transmitted to the next stage.

Here, the generation of the accompanying data will be described. As with the case of the SD system VTR, the accompanying data of each AUX area is generated by the mode processing microcomputer 967 in FIG. The pack data generated by the microcomputer is transmitted to the IC 9 for the accompanying data via the signal processing microcomputer 953 of FIG.
54 to 958.

The AAUX processing IC shown in FIG.
958 is, specifically, two AAUXs provided in parallel.
The AAUX IC is composed of pack data output from the audio data processing circuit 961 and is synthesized with audio data to be recorded on odd tracks and audio data to be recorded on even tracks. Data ADATA1 of the audio recording area of the track and data ADATA2 of the audio recording area of the odd track are generated. AAU
As the XIC, the one used in the SD system VTR can be used as it is. However, AA in FIG. 47 and FIG.
As can be seen from the UX format, in the case of the HD system VTR, the timing of outputting data from the AAUX IC is different from that in the case of the SD system VTR, but this may be achieved by changing the software for determining the output timing.

In the SUBCODE IC,
As shown in FIG. 7, SU recorded on an even track
BCODE ID data SID1 and pack data SDATA1 and SUBC recorded on odd tracks
ODE ID data SID2 and back data SDAT
A2 is generated and transmitted to the next processing circuit shown in FIG.

Next, generation of VAUX data will be described with reference to a specific circuit. FIG. 10 shows VAUX I.
The circuit configuration when generating pack data in C954 and 955 is shown. In this figure, the pack data generated by the mode processing microcomputer 967 is transmitted to the signal processing microcomputer 953 in the same manner as in the case of the SD system VTR, and after storing the absolute track number in the necessary pack, the buffer memory 123 VAUX I via
C 954 and 955 are input in parallel, and read out from these ICs in accordance with the in-frame track number and the in-track SYNC number.

In this case, as shown in FIG. 1, the track number in the frame is a number in which the value is incremented by 1 for every two tracks, and the timing is the same as that of the SD system VTR. The storage capacities of the main area FIFO and the optional area FIFO can be the same as those of the SD system VTR.
In this way, the VAUX IC of the SD system VTR can be used as it is as the VAUX IC shown in FIG.

In this configuration, the VAUX IC954
And 955 are the same, but the optional data is VAUX IC
The data output from the VAUX IC 955 and the data output from the VAUX IC 955 may be configured to be different from each other to double the amount of optional data recorded. FIG. 11 shows the data structure of one frame of the VAUX area when such a configuration is adopted. In this figure, the optional data recorded by the plus azimuth recording head is indicated by a pack with halftone dots,
It is shown as different data from the optional data recorded by the minus azimuth recording head. FIG. 12 shows data reproduced by each head in this case and VAUX data determined based on the reproduced data.

In [1] of this figure, the signal processing microcomputer 809 stores the data VAUX from the VAUX IC 808.
DT1 and data VAU from VAUX IC 810
Regarding XDT2, for the main area data, correct data is determined by integrating the data from both ICs, and for the optional area data, the data from each IC is used using the respective error signals VAUXER1 and VAUXER2. Corrections were made to derive the correct optional final data.

For reference, FIG. 13 shows the configuration of a recording system for generating such VAUX data. In this figure, VAUX data for recording on even-numbered tracks and VAUX data for recording on odd-numbered tracks generated by the mode processing microcomputer 967 are input to the signal processing microcomputer 953 in parallel to each VAUX data. After the absolute track number is stored in a predetermined pack in this microcomputer as necessary, the microcomputer stores the absolute track number in the buffer packs 706 and 705, and is input to the VAUX ICs 954 and 955, respectively. It should be noted that also in this figure, the VAUX IC used therein is S
VAUXIC used in the D system VTR can be used as it is.

As described above, ADATA1 and VDA constituting the even track data generated in FIG.
TA1, SID1, SDATA1 and ADATA2, VDATA2, SID constituting odd track data
2 and SDATA2 are input to the even track data processing channel 985 and the odd track data processing channel 986 in FIG. 8, respectively. In addition to these input data, AV ID,
A generation signal in the Pre-SYNC and Post-SYNC generation circuit 984, an ITI signal from the ITI signal generation circuit 968, an amble pattern from the amble pattern generation circuit 973, and A / V SYNC and SUB
SYNC from CODE-SYNC generation circuit 975
A signal is input, and a recording code is generated in the same manner as in the case of the SD system VTR.

The recording code of the even-numbered track generated as described above is stored in the switch SW 98 and the recording amplifier 9.
It is supplied to the minus azimuth recording head 976 or 979 via 77 or 978. Further, the recording code of the odd track is the switch SW99 and the recording amplifier 98.
1 or 982, plus azimuth recording head 9
80 or 983.

5. Reproduction Circuit of HD VTR Next, the reproduction circuit of the HD VTR according to the present embodiment will be described with reference to FIGS. In FIG. 14, the signal reproduced by the minus azimuth reproducing head is input to the even track data processing channel 826, and the reproduction signal reproduced by the plus azimuth reproducing head is outputted to the odd track data processing channel 843.
Is input to From the even track data processing channels, ADATA1, VDATA1, SID1,
SDATA1 and ERROR1 are taken out, and ADATA is output from the odd track data processing channel.
2, VDATA2, SID2, SDATA2 and ERR
OR2 is taken out.

Note that T in these processing channels
BC channel decoder A and channel decoder B
Are the TBC 995 and the channel decoder A (99) in the playback circuit of the SD system VTR shown in FIG.
6) and the same internal circuit as the channel decoder B (990). That is, the circuit shown in FIG.
2 corresponds to a circuit in which two channels of SD type VTR reproducing circuits are provided in parallel.

Each data derived by the above two processing channels is supplied to each input terminal shown in FIG. 15, and a video output, an audio output, and accompanying data are taken out. Also in the circuit shown in FIG.
This corresponds to a configuration in which processing circuits in a TR are provided in parallel for two channels, and is configured so that compatibility in the case of performing recording and reproduction by the SD method is enhanced.

First, the processing of video data will be described. VDATA1 and VDATA2 are input to deframing circuits 801 and 806, respectively, where the deframed data is sent to a decompression encoding and deshuffling circuit 803. The video data input and decompressed and divided as even track data and odd track data are integrated as one frame of video data and subjected to deshuffling processing.

The deshuffled data is subjected to deblocking processing in the next deblocking circuit 805. Here, the deframing circuits 801 and 806
Error signals VERROR1 and VERROR from
The correction process of the error part is also performed by using 2. The deblocked digital data DY, DR, and DB are further D / A-converted, passed through a Y signal / chroma signal synthesizing circuit, inserted with a composite synchronizing signal, and output as a video signal.

The VAUX data processing is performed as shown in FIG. 2 or FIG. In this case, in particular, if the configuration is as shown in FIG. 2, not only the main area data but also the optional data can obtain the integration effect of adopting the correct one of the data repeatedly reproduced twice. The SUBCODE data is processed as described with reference to FIG. 6, and the data is determined. The data in the audio area is separated into AAUX data and audio data by switches SW21 and SW20, and the former is input to AAUX ICs 813 and 814, and the audio data is input to deframing circuits 815 and 817.

For processing of AAUX data, AAUXDT1 and AAUXDT output from these ICs are used.
2, and the error signals AAUXER1 and AAUXER
2 is input to the signal processing microcomputer 809, and referring to these error signals in this microcomputer, FIG.
The data in the main area and the data in the optional area are determined and transmitted to the mode processing microcomputer. As for the processing of the deframed audio data, the audio data processing circuit 816 performs error correction using the propagation error signals AERROR1 and AERROR2, and then extracts the original recorded audio signal. In addition,
As described above, the finally output audio signal is composed of a large number of channels such as four channels.
The processing for extracting the audio signal of each of these channels is not directly related to the problem of the present invention, and therefore the description is omitted.

Although the embodiment of the HD system VTR according to the present invention has been described above, it is needless to say that the present invention is not limited to the configuration of this embodiment, and various changes can be made within the technical idea of the present invention. is there.

[0160]

According to the present invention, a circuit for processing accompanying data in an HD system VTR can be constituted by using an accompanying data processing circuit in an SD system VTR, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data structure of a VAUX recording area in an embodiment of the present invention.

FIG. 2 is a diagram illustrating reproduction of VAUX data in the embodiment.

FIG. 3 is a diagram showing a data structure of a SUBCODE data recording area in the embodiment.

FIG. 4 is a diagram illustrating SUBCODE data reproduced by a minus azimuth head in the embodiment.

FIG. 5 is a diagram illustrating SUBCODE data reproduced by a plus azimuth head in the embodiment.

FIG. 6 shows a SUBCODE from a reproduction output in the embodiment.
It is a figure explaining operation which determines and derives data.

FIG. 7 is a diagram showing a configuration of a part of a recording circuit in the embodiment.

FIG. 8 is a diagram showing a configuration of another portion of the recording circuit in the embodiment.

FIG. 9 is a diagram illustrating blocking of one frame of video data in the embodiment.

FIG. 10 is a diagram illustrating a circuit configuration for generating VAUX data in the embodiment.

FIG. 11 is a diagram showing another configuration example of the data structure of the VAUX recording area in the embodiment of the present invention.

FIG. 12 shows a VAU of another configuration example in the embodiment of the present invention.
FIG. 8 is a diagram illustrating a VAUX data reproduction operation when the data structure of the X recording area is adopted.

FIG. 13 is a diagram illustrating a VAUX data generation circuit when the data structure of the VAUX recording area of the other configuration example is adopted.

FIG. 14 is a diagram illustrating a configuration of a part of a reproduction circuit according to an embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of another part of the reproduction circuit in the embodiment.

FIG. 16 is a diagram showing a recording format of one track of an SD system VTR.

FIG. 17 shows a pre-SYNC block and a post-SYNC
It is a figure showing the structure of C block.

FIG. 18 is a diagram illustrating the framing format of AUDIO and the structure of one SYNC block.

FIG. 19 is a diagram illustrating blocking of image data for one frame.

FIG. 20 is a diagram showing a VIDEO framing format to which an error correction code is added.

FIG. 21 is a diagram showing the configuration of a VIDEO buffering unit and one SYNC block.

FIG. 22 is a diagram illustrating the structure of a SUBCODE area for one track.

FIG. 23 is a diagram illustrating the structure of an ID part of a SYNC block in an AUDIO area and a VIDEO area.

FIG. 24 is a diagram illustrating the structure of an ID part of a SYNC block in a SUBCODE area.

FIG. 25 is a diagram showing a basic structure of a pack.

FIG. 26 is a diagram showing a definition of a group of packs by large items.

FIG. 27: AAUX SOURCE pack, AAUX
SOURCE CONTROL PACK, AAUX RE
C DATE pack, AAUX REC TIME pack, AAUX REC TIME BINARY GR
It is a figure showing the details of an OUP pack.

FIG. 28: AAUX CLOSED CAPTION pack, VAUX SOURCE pack, and VAUX
It is a figure which shows the detail of SOURCE CONTROL pack.

FIG. 29: VAUX REC DATE pack, VAU
X REC TIME pack, VAUX REC TI
ME BINARY GROUP PACK, CLOSED
It is a figure which shows the details of a CAPTION pack and a VAUX TR pack.

FIG. 30 is a diagram illustrating the structure of an AAUX area for one frame.

FIG. 31 is a diagram illustrating the structure of a VAUX area for one track.

FIG. 32 is a diagram illustrating a pack structure of a VAUX area for one frame.

FIG. 33 is a diagram illustrating multiple writing of pack data in a SUBCODE area.

FIG. 34: S in the SD system VTR for SECAM system
It is a figure explaining multiplex writing of pack data of a UBCODE area.

FIG. 35 is a diagram for describing definition of a track format by APT.

FIG. 36 is a diagram illustrating a hierarchical structure of an application ID.

FIG. 37 is a diagram illustrating a format on a track when an application ID is “000”.

FIG. 38 is a diagram showing a recording circuit of an SD system VTR.

FIG. 39 is a diagram illustrating generation of pack data in the recording circuit of the VTR.

FIG. 40 is a diagram illustrating a main area on a recording track.

FIG. 41 is a diagram illustrating generation of pack data in a mode processing microcomputer.

FIG. 42 is a diagram showing a configuration of one part of an SD system VTR reproduction circuit.

FIG. 43 is a diagram showing the configuration of another part of the SD system VTR reproduction circuit.

FIG. 44 is a diagram for describing processing of playback pack data in the VAUX IC.

FIG. 45 is a diagram for describing processing of reproduction pack data in the signal processing microcomputer.

FIG. 46 is a diagram illustrating a recording / reproducing head in an SD system VTR and an HD system VTR.

FIG. 47 is a diagram illustrating the structure of an AAUX data recording area in the present embodiment.

[Explanation of symbols]

801, 806, 815, 817: Deframing circuit, 808, 810, 954, 955: VAUX IC, 811, 812, 957, 957: SUBCODE I
C, 813, 814: AAUX IC, 820, 822, 833, 835: reproduction head, 948: shuffling and compression coding circuit, 951, 952: framing circuit, 985: even track data processing channel, 986: odd track data Processing channels, 976, 979, 980, 983 ... recording head,

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N 9/79-9/898

Claims (11)

(57) [Claims] 1. A television signal recording method for recording a television signal on a recording medium, the method comprising: executing the following processes (1) to (4). (1) Separate image data from an input television signal. (2) Generating additional data, which is the additional data relating to the image data, including the basic data and the additional data. (3) The recording medium is scanned a plurality of times for one frame of the television signal, and a pair of recording tracks is formed for each scanning. (4) On each of the pair of recording tracks, an image data recording area for recording image data, a basic data recording area for recording basic data, and an additional data recording area for recording additional data. And the formation position of the basic data recording area in each of the pair of recording tracks is determined by odd-numbered scanning and even-numbered scanning in one frame of the television signal. In the odd-numbered scan in one frame of the television signal and in the even-numbered scan following this scan, basic data having the same data content is basically set on each recording track. Record in the data recording area. 2. An additional data having the same data content is recorded in each additional data recording area of each associated data recording area on a pair of recording tracks formed by one scan. The television signal recording method according to claim 1, wherein 3. An additional data having different data contents is recorded in each additional data recording area of each associated data recording area on a pair of recording tracks formed by one scanning. The television signal recording method according to claim 1, wherein 4. A television signal recording method for recording a television signal on a recording medium, the method comprising performing the following processes (1) to (6). (1) Separate image data from an input television signal. (2) Generates secondary data having information for searching for the recorded content recorded on the recording medium and including basic data and additional data. (3) The recording medium is scanned a plurality of times for one frame of the television signal, and a pair of recording tracks is formed for each scanning. (4) An image data recording area for recording image data and a secondary data recording area for recording secondary data are formed on each recording track of the recording medium. The basic data recording area includes a basic data recording area for recording the basic data and an additional data recording area for recording the additional data. (5) In each scan in the first half period of one frame of the television signal, the secondary data having the same data content is recorded in the secondary data recording area of the recording medium, and one frame of the television signal is recorded. In each scan in the latter half of the period, the secondary data having the same data content is recorded in the secondary data recording area of the recording medium. (6) The additional data recording area on one recording track is composed of two separated recording zones having the same recording capacity, and the additional data is recorded in the two recording zones. 1 in the first half of one frame of the John signal
The additional data recorded in the two recording zones in each recording track are exchanged with each other for each scan, and the two data are also exchanged for each scan in the latter half of one frame of the television signal. Each additional data recorded in the recording zone is exchanged with each other. 5. A television signal recording / reproducing apparatus for recording / reproducing a television signal using a recording medium,
(1) separating means for separating image data from an input television signal; and (2) auxiliary data which is auxiliary data relating to the image data and which generates auxiliary data including basic data and additional data. Generating means; (3)
By providing a pair of recording means and scanning the recording medium a plurality of times for one frame of the television signal,
Scanning means for forming a pair of recording tracks for each scan by the pair of recording means to record the image data and the accompanying data on a recording medium; and (4) a pair of reading means; Reproducing means for reproducing the image data and the accompanying data from the pair of recording tracks recorded by the pair of recording means by scanning the recording medium a plurality of times for one frame of the television signal; Restoring means for restoring a television signal based on the image data reproduced by the reproducing means; and (6) accompanying data deriving means for deriving determined accompanying data based on the accompanying data reproduced by the reproducing means. And a pair of recording means for recording image data in an image data recording area formed on each recording track, Accompanying data is recorded in an accompanying data recording area composed of a basic data recording area and an additional data recording area formed at different positions on a recording track by odd-numbered scanning and even-numbered scanning in one frame. Further, in the odd-numbered scan in one frame of the television signal and in the even-numbered scan following this scan, basic data having the same data content is recorded in a basic data recording area on each recording track. A television signal recording / reproducing apparatus. 6. The television signal recording / reproducing apparatus according to claim 5, wherein said pair of recording means records additional data having the same data content as each other. 7. The television signal recording / reproducing apparatus according to claim 5, wherein said pair of recording means records additional data having different data contents from each other. 8. The accompanying data deriving means converts the basic data reproduced from a pair of recording tracks by odd-numbered scanning in one frame of the television signal by the reproducing means and even-numbered scanning following this scanning. 6. The television signal recording / reproducing apparatus according to claim 5, wherein the determined basic data is derived by integration. 9. The additional data deriving means derives determined additional data by integrating additional data reproduced from a pair of recording tracks by one scan by the reproducing means. The television signal recording / reproducing device according to claim 6. 10. A television signal recording / reproducing apparatus for recording / reproducing a television signal using a recording medium, comprising: (1) separating means for separating image data from an inputted television signal; and (2) recording medium. And (3) a pair of secondary data generation means having information for searching for the recorded content recorded in the sub-data, and generating sub-data composed of basic data and additional data. And the recording medium is scanned a plurality of times for one frame of the television signal, and the pair of recording means forms one pair of recording tracks for one scan, thereby forming the image data. The secondary data is recorded in the image data recording area of each recording track, and the secondary data is further divided into two separate recording areas having the same recording capacity as the basic data recording area where the basic data is recorded. Scanning means for recording in a secondary data recording area composed of an additional data recording area in which the additional data composed of a recorded recording area is recorded,
(5) The apparatus comprises a pair of reading means, and scans the recording medium a plurality of times for one frame of the television signal, thereby obtaining the image data and the image data from the pair of recording tracks formed by the pair of recording means. Reproduction means for reproducing the secondary data; (6) restoration means for restoring a television signal based on the image data reproduced by the reproduction means; and (7) secondary data reproduced by the reproduction means. And secondary data deriving means for deriving the determined secondary data based on the following, and wherein the scanning means performs a plurality of scans in each of a plurality of scans in a first half period of one frame of the television signal, The secondary data having the same data content is recorded on the recording medium, and the same data is used in each of a plurality of scans in the latter half of one frame of the television signal. Secondary data consisting of data contents is recorded on a recording medium. Further, with respect to the additional data recorded in each of the two recording areas of the additional data recording area on each recording track, the recording area is converted to a television signal. Each of the additional data recorded in the two recording areas is alternately recorded every one scan in the first half of one frame of the television signal, and is also recorded every one scan in the second half of one frame of the television signal. A television signal recording / reproducing apparatus, wherein the recording areas are alternately recorded. 11. The secondary data deriving means integrates the additional data in the secondary data reproduced in one of the first half and the second half of one frame of the television signal, so as to integrate the additional data in the first period. 11. The television signal recording / reproducing apparatus according to claim 10, wherein the additional data reproduced on the television signal is determined.