JP3535551B2 - Electronically controlled failsafe device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronically controlled fail-safe device. 2. Description of the Related Art For example, an electric power steering system for a vehicle includes an electric motor for power assisting the operation force of a steering wheel, a steering angle sensor for detecting a steering angle of the steering wheel, and is constituted by a microcomputer or the like. The control unit electronically controls the drive of the electric motor based on the detection signal of the steering angle sensor.However, in case the control program of the control unit goes out of control for some reason, the system is moved to the safe side. As a fail-safe device for guiding, a device configured as shown in FIG. 5 is known. [0003] 1 electric motor for power assisting the operation force of the handle, a power on-off circuit 3 which comprises a relay R _Y to the drive circuit 2, the relay drive circuit 4 is provided comprised of the resistor R ₁ and transistor T _R1 . 5 is a CPU for controlling the motor drive circuit 2 according to the steering angle of the steering wheel.
The CPU 5 stores the fail-safe program in addition to the control program for the electric motor 1.
The watchdog timer 6 monitors the pulse of the CPU 5, and when detecting the stop of the pulse when the CPU is abnormal, C
A reset pulse is output to PU5. 7, a pulse output terminal; 8, a pulse input terminal; and 9, a relay drive terminal. The fail-safe program outputs a pulse of a predetermined period from the pulse output terminal 7 to the watchdog timer 6 when the CPU is normal,
5 over the bolts of the voltage supplies current I _B to the base of transistor T _{R 1} is, stops the pulses to the watchdog timer 6 when an abnormality occurs in the CPU relay reset pulse watchdog timer 6 Drive terminal
So that the cut off the base current I _B to the transistor T _R1 a 9 voltage dropped to 0 volts. Accordingly, when the control unit 5 in the reset pulse of the watchdog timer 6 stops the base current I _B to the transistor T _R1, the relay current IR _Y
Is turned off, the power to the motor drive circuit 2 is shut off.
Even if the control program runs away, the motor 1 does not operate and the vehicle can be safely steered by manual steering. FIG. 6 shows the relay drive voltage V _OUT and the base current I _B
FIG. 5 is an operation characteristic diagram showing a relationship between the relay current and the relay current _IRY . The circuit configuration of the watchdog timer is disclosed in Japanese Utility Model Laid-Open No. 1-100239. [0007] [SUMMARY OF THE INVENTION Incidentally, when this conventional example such as a pulse input terminal 8 and the relay drive pin 9 fails, may continue to flow the base current I _B of the transistor T _R1 However, there is a problem that the system cannot be led to the safe side because the power supply of the motor 1 cannot be cut off. Further, since many parts including the watchdog timer 6 are required, not only the cost is increased, but also the failsafe itself is liable to cause a failure of the device, and there is a problem that high reliability cannot be expected so much. . Although an example is shown in which the fail-safe device is formed into an IC, the IC itself is expensive and difficult to adopt in terms of cost. The present invention has been made in view of such problems, and has as its object to provide a low-cost and highly reliable fail-safe device. Therefore, a CPU having a fail-safe program for outputting a pulse of a predetermined period in a normal state, and a pulse voltage charging circuit for charging the pulse voltage and keeping the output substantially constant When, with a relay for on-off power to the electric actuator as a control target of the CPU, and a relay driving circuit for controlling the power supply of the relay in accordance with the output of the pulse voltage charging circuit, the relay driving
The circuit includes a transistor and a first resistor, and
The pulse voltage charging circuit includes a second resistor, first and second
A first capacitor comprising a capacitor and a plurality of diodes;
Is connected to the CPU via the second resistor.
A second terminal connected to a terminal for outputting a pulse voltage;
When the CPU is normal, the capacitor detects the pulse voltage.
It is charged periodically, and is not charged when the CPU is abnormal.
No. Normally, pulses of a predetermined period are output from the CPU, so that the output is kept substantially constant by the action of the pulse voltage charging circuit, and the relay drive circuit is continuously operated. Are kept on. Therefore, the electric actuator operates normally under the control of the CPU. When an abnormality or failure occurs in the control program or the pulse output terminal of the CPU, the CPU does not output a pulse having a predetermined cycle, and the pulse remains off or the pulse cycle becomes very long. Since the pulse voltage charging circuit is not charged even if the pulse is on for a long time and its output drops, the relay drive circuit turns off the power supply relay. Can be shut off. FIG. 1 shows an example of application to an electric power steering system of a vehicle. Reference numeral 1 denotes an electric motor for power assisting the operating force of a steering wheel, and a CPU 5 controls a driving circuit 2 of the electric motor. In addition to a control program for instructing the drive of the electric motor 1 according to the steering angle of the steering wheel, a fail-safe program for the abnormality is stored. The fail-safe program outputs a pulse of a predetermined cycle when the CPU 5 is normal, and stops the output of the pulse when an abnormality occurs in the motor control program. [0013] a power supply on-off circuit 3 which comprises a relay R _Y is the motor drive circuit 2, the relay drive circuit 4 is provided which is constituted by the transistors T _{R 1} and resistor R _1. A pulse voltage charging circuit 10 is given to on-off control Totanjisuta T _R1 of the relay driving circuit 4 is connected to the voltage of the CPU5 pulse output terminal 7 so that the input voltage of the relay drive circuit 4. The pulse voltage charging circuit 10 charges the pulse voltage of the CPU 5 and outputs the signal in the normal state (relay drive voltage V
_OUT (equivalent to _OUT ) is kept substantially constant, and is composed of capacitors C ₁ and C ₂ , diodes D ₁ and D ₂ and a resistor R ₂ . [0014] Figures 2-4 by adding a diode voltage V _D1 and the capacitor voltage V _C2 in the pulse voltage V _'OUT, at operating characteristic diagram showing the relationship between these and the base current I _B and the relay current I _RY, CPU 5 Is 0 in this case.
Changes from volts to 5 volts, current flows into the resistor R ₂ → capacitor C ₁ → the diode D ₂ → resistor R _1, the transistor T _R1 is turned by receiving the base current I _B. At that time, because the current also flows to the capacitor C _2, the capacitor C ₂ is charged, the voltage Vc ₂ is increased. After a lapse of a predetermined time, the pulse output terminal 7
When the voltage changes from volts to 0 volts, the current I _D1 flows from the diode D ₁ → the capacitor C ₁ → the resistor R ₂ , so that the capacitor C ₁ is discharged at once and prepares for the next pulse output.
At the same time, the discharge direction from the capacitor C ₂ to the resistor R ₁ is performed, since the flow continues base current I _B, the transistor T _R1 is held in the ON state. As described above, the voltage V 'of the pulse output terminal 7 is
_OUT is by repeating the change of the predetermined period, the flow continues the base current I _B to the transistor T _R1, power on-off circuit 3 of the electric motor 1 is to be maintained in the ON state by operation of the relay R _Y, the CPU5 The normal power steering function of the electric motor 1 based on the control program is exhibited. When an abnormality occurs in the control program, the CPU 5 stops the pulse output as shown in FIG. 2, and during that time, the resistor R ₂ → the capacitor C ₁ , as in the case of the failure in which the pulse output terminal is fixed to 0 volt. since → diode D ₂ → no current to the resistor R ₁ flows, not performed even charging and discharging of the capacitor C _1, since the base current I _B to the transistor T _R1 is cut off, the electric motor relay R _Y is turned off The power supply to 1 is cut off. Therefore, thereafter, the vehicle can be safely steered by manual steering. When a failure occurs in the pulse output terminal 7 of the CPU 5 and the pulse voltage is fixed at 0 volt due to disconnection as shown in FIG. 3, the relay _RY is turned off in the same manner as described above. Furthermore, there is also that the pulse voltage as represented in Figure 4 are fixed to 5 volts, the charge capacity of the capacitor C ₁ is full, the current is cut off by the capacitor C _1, diode D ₁ → capacitor in pulse voltage C ₁ → Since the current I _D1 to the resistor R ₂ is blocked, the capacitor C ₁ is not discharged, and the diode voltage V _D1 gradually decreases. Therefore, when the discharging of the capacitor C ₂ is completed, the base of the transistor T _{R 1} is turned off. The current is cut off and the relay _RY is turned off. That is,
As for the failure of the pulse output terminal 7, the power on-off circuit 3 of the electric motor 1 can be reliably shut off to the safe side as in the case of the abnormality of the control program. In terms of structure, the number of parts is reduced by omitting the watchdog timer, so that the cost can be reduced and the reliability can be improved. Further, since the pulse output terminal 7 of the CPU 5 is used in the same manner as the relay drive terminal 9 of the prior art, the reset pulse input terminal 8 and the relay drive terminal 9 of the prior art are used.
It is not necessary to prepare for the failure, and even if there is a failure or disconnection of the pulse output terminal 7, a good fail-safe function can be easily secured. In summary, according to the present invention, a CPU having a fail-safe program for outputting a pulse of a predetermined period in a normal state, and a pulse voltage for charging the pulse voltage and keeping the output substantially constant Since a charging circuit, a relay for turning on and off the power supply to the electric actuator as a control target of the CPU, and a relay drive circuit for controlling the relay of the power supply according to the output of the pulse voltage charging circuit are provided.
Even if a failure occurs in the pulse output terminal of the PU, the system can be guided to the safe side. In addition to the fact that a watchdog timer is not required, the number of components is reduced, and the pulse output terminal of the CPU is used as a relay drive terminal, so that a highly reliable fail-safe function can be easily realized at low cost. Can be

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing an embodiment of the present invention. FIG. 2 is an operation characteristic diagram of a pulse voltage charging circuit and a relay driving circuit. FIG. 3 is an operation characteristic diagram of a pulse voltage charging circuit and a relay driving circuit. FIG. 4 is an operation characteristic diagram of a pulse voltage charging circuit and a relay driving circuit. FIG. 5 is a configuration diagram illustrating a conventional example. FIG. 6 is an operation characteristic diagram of the relay drive circuit. [Description of Signs] 1 Electric motor for power steering 2 Motor drive circuit 3 Power on / off circuit 4 Relay drive circuit 5 CPU 7 Pulse output terminal 10 Pulse voltage charging circuit _RY Relay T _R1 transistor R ₁ , R ₂ resistor C ₁ , C ₂ capacitor D ₁ , D ₂ diode

Claims (1)

(57) [Claim 1] A CPU having a fail-safe program for outputting a pulse of a predetermined cycle in a normal state, and a pulse voltage charging circuit for charging the pulse voltage and keeping the output substantially constant When, with a relay for on-off power to the electric actuator as a control target of the CPU, and a relay driving circuit for controlling the power supply of the relay in accordance with the output of the pulse voltage charging circuit, the relay drive circuit, transient
And a first resistor, and the pulse voltage charging circuit
The path comprises a second resistor, first and second capacitors, and a plurality of diodes.
And the first capacitor outputs a pulse voltage of the CPU via the second resistor.
And the second capacitor is connected to the C
When the PU is normal, it is charged at the cycle of the pulse voltage,
The electronically controlled failsafe device is not charged when the CPU is abnormal .