JP3534915B2 - Parallel input / output port - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel input / output port, and more particularly to a parallel input / output port suitable for use in controlling a plurality of control devices to sequentially perform their respective jobs.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing a conventional example of a parallel input / output port set as an output port. 12, the register 101 ₁ is reset with D-type flip-flop is constituted by (hereinafter referred to as D-FF). In this register 101 ₁ ,
System clock signal C as its clock (C) input
LK is provided, and the system reset signal RST is provided as a reset (R) input.

[0003] Register 101 ₁ further a data signal DATA data (D) input from the internal data bus 102, and enable (E) input of the write enable signal ENBL. Data output Q of register 101 ₁
Is output via the output signal lines 103 ₁ buffer 104 ₁
And is output to the outside through the external port 105 ₁ . The external port 105 ₁ has a control device 106
₁ is connected. When the controller 106 ₁ finishes its work, it generates an interrupt signal int1 and the OR gate 10
7 to the CPU (not shown). A circuit having the same configuration as described above is arranged in parallel in n stages with respect to n control devices.

Next, the circuit operation of the above configuration will be described with reference to FIG.
This will be described with reference to the waveform chart of. First, the system reset signal RST is at a high level becomes a (hereinafter, "H" referred level), the register 101 _1, the system clock signal C
It is reset in synchronization with the rising edge of LK, and low-level (hereinafter referred to as “L” level) data is written (operation). Thus, the register 101 ₁ of the data output Q becomes "L" level.

Then, an "H" level data signal DATA is sent from the internal data bus 102 to the register 101 ₁ .
There is input, the write enable signal ENBL changes to "H" level, the "H" level data to the register 101 ₁ is written in synchronization with the rising edge of the system clock signal CLK, the register 101 ₁ of the data output Q
Becomes "H" level. This allows the external port 105
₁ becomes “H” level, the control device 106 ₁ connected to the external port 105 ₁ operates (ON), and starts work (operation). The control device 106 ₁ finishes the work (O
Then, the interrupt signal int1 is generated (operation).

Then, in response to the interrupt signal int1, the CPU starts a predetermined interrupt process. After the completion of the interrupt process, when the data signal DATA of “L” level is input from the internal data bus 102 and the write enable signal ENBL becomes “H” level, the register 10
" ₁ " level data is the system clock signal C 1
It is written in synchronization with the rising edge of LK, and the register 10
The data output Q of 1 ₁ becomes "L" level (operation).
As a result, the external port 105 ₁ becomes "L" level. By sequentially performing the above operations, and the circuits of the second and subsequent stages, a plurality of control devices 106 _{2 to} 106 _n connected to the external ports 105 _{2 to} 105 _n are sequentially driven to perform work. Go.

[0007]

However, in the conventional parallel input / output port having the above structure, each external port 1
A plurality of control devices 10 connected to 05 _{1 to} 105 _n
When 6 _{1 to} 106 _n are driven sequentially to perform work, when the work of the plurality of control devices 106 _{1 to} 106 _n ends and an interrupt occurs, the CPU performs a predetermined interrupt process, and after the process is completed, Since the operation to write data to the next register is performed, wait until the interrupt processing of the CPU is completed, and then
Since the next control device is operated, there is a problem that the sequential processing takes time.

[0008]

According to the present invention, in a parallel input / output port for driving and controlling a plurality of control units which are connected to a plurality of external ports and generate an interrupt signal when each work is completed, a parallel input / output port from a data bus is used. A register group consisting of a first-stage register for storing a data signal given as a data input and a plurality of registers of the second and subsequent stages arranged in parallel to the first-stage register, a system reset signal, and a data output signal of the first-stage register A first selector circuit which has two inputs, selects one of them as a reset input of the register in the first stage according to a predetermined control signal, and an OR gate which receives each interrupt signal of a plurality of control devices as input. The system clock signal and the output signal of the OR gate are two inputs, and either one is selected according to the control signal. A second selector circuit that receives the clocks of the register of the stage and a plurality of registers, and a data signal and a data output signal of the register of the previous stage in the register group are two inputs, and one of the plurality of registers outputs a plurality of signals depending on the control signal. Among the registers, a plurality of third selector circuits that receive data from corresponding registers are provided.

In the parallel input / output port having the above structure, first, the data signal supplied from the data bus is stored in the register in the first stage. Then, the data output signal of the register of the first stage drives the control device of the first stage. This causes the first-stage control device to start work.
Thereafter, a control signal is applied, and in response to this, the second selector circuit selects the output signal of the OR gate, and the third plurality of selector circuits selects the data output signal of the register in the preceding stage. When the control device at the first stage finishes its work, it generates an interrupt signal. This interrupt signal becomes a clock input to the register in the second stage via the OR gate and the second selector circuit. Then, in synchronization with this interrupt signal, the data output signal of the first-stage register is stored in the second-stage register. Then, the data output signal of the register of the second stage drives the control device of the second stage.
After that, each time an interrupt signal is generated from the control device of each stage, the data output signal is shifted from the register of the previous stage, so that the control device connected to each external port is driven sequentially to perform work. To go.

Further, according to the present invention, in a parallel input / output port for driving and controlling a plurality of control devices connected to a plurality of external ports, a first stage register and a first stage register for storing a data signal provided as a data input from a data bus. A register group consisting of a plurality of registers of the second and subsequent stages arranged in parallel with each other, a system reset signal and a data output signal of the register of the first stage as two inputs,
A first selector circuit that selects either one of them according to a predetermined control signal and uses it as a reset input of the register in the first stage;
An interrupt signal generation circuit that generates an interrupt signal at regular time intervals, a system clock signal and the above interrupt signal as two inputs, and select either one in accordance with the above control signal to select each clock of the first stage register and a plurality of registers. A second selector circuit which is an input, and a data signal and a data output signal of a register in the preceding stage of the register group are two inputs, and one of them is used as a data input of a corresponding register among a plurality of registers according to the control signal. And a plurality of third selector circuits that operate.

In the parallel input / output port having the above structure, first, the data signal supplied from the data bus is stored in the first stage register. Then, the data output signal of the register of the first stage drives the control device of the first stage. This causes the first-stage control device to start work.
After that, a control signal is given, and in response to this, the second selector circuit selects the output signal of the interrupt signal generation circuit,
The third plurality of selector circuits select the data output signal of the previous register. Also, the interrupt signal generation circuit generates an interrupt signal at regular time intervals. This interrupt signal becomes a clock input to the register in the second stage via the second selector circuit. Then, in synchronization with this interrupt signal, the data output signal of the first-stage register is stored in the second-stage register. Then, the data output signal of the register of the second stage drives the control device of the second stage. After that, each time the interrupt signal is generated from the interrupt signal generation circuit, the data output signal is shifted from the register in the previous stage, so that the control device connected to each external port is driven sequentially to perform work. Go.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In Figure 1, the register 11 ₁ in the first stage is reset with D-FF
It is composed by. In the register 11 ₁ , the output signal OUT1 of the selector circuit 12 is given as its clock (C) input, and the output signal OUT2 of the selector circuit 13 is given as its reset (R) input.
The selector circuit 12 receives the system clock signals CLK and O.
The output signal OUT3 of the R gate 14 is used as two inputs, and one of the two inputs is selected as the output signal OUT1 by the control signal CONT. The selector circuit 13 outputs the system reset signal RST and the data output Q1 of the register 11 ₁ to 2
One of the two inputs is selected as an input and is used as an output signal OUT2 by the control signal CONT.

The register 11 ₁ further receives the data signal DATA from the internal data bus 15 as data (D) input and enables the write enable signal ENBL (E).
Input it. The data output Q1 of the register 11 ₁ is supplied to the output buffer 17 ₁ via the output signal line 16 ₁ ,
Further, it is output to the outside through the external port 18 ₁ . The control device 19 ₁ is connected to the external port 18 ₁ . The system clock signal CLK and the control signal CO
Each of NT, the system reset signal RST, and the write enable signal ENBL may be given from a CPU (not shown) or may be given from an external hardware circuit.

Similarly to the register 11 ₁ of the first stage, the register 11 ₂ of the second stage is also constituted by a D-FF with reset, and the output signal OUT1 of the selector circuit 12 is given as its clock (C) input. . Further, the system reset signal RS is used as the reset (R) input.
T is given directly. The register 11 ₂ further receives the output signal OUT4 of the selector circuit 20 ₂ as a data (D) input and the output signal OUT5 of the OR gate 21 ₂ as an enable (E) input. The selector circuit 20 ₂ has the data signal DATA from the internal data bus 15 and the data output Q1 of the register 11 ₁ of the first stage as two inputs, selects one of the two inputs according to the control signal CONT, and outputs the output signal OU.
T4. The OR gate 21 ₂ has the above-mentioned control signal CON.
T and the write enable signal ENBL are two inputs.

The data output Q2 of the register 11 ₂ is supplied to the output buffer 17 ₂ via the output signal line 16 ₂ and becomes the data (D) input of the register 11 _{3 in} the third stage. The data output Q2 passing through the output buffer 17 ₂ is
It is supplied to the control device 19 ₂ via the external port 18 ₂ . Circuits having the same configuration as the register 11 ₂ and its peripheral circuit of the second stage are arranged in a plurality of stages parallel. The control devices 19 ₁ , 19 ₂ , ... Of these stages generate interrupt signals int1, int2 ,. These interrupt signals int1, int2, ...
The output signal OUT3 is supplied to the selector circuit 12 via the OR gate 14.

Next, the circuit operation according to the first embodiment having the above configuration will be described with reference to the waveform chart of FIG. The control signal CONT is the control device 19 ₁ , 19 ₂ , ...
For example, 1-bit data (“H” /
"L" level).

First, when the control signal CONT is at the "L" level, the selector circuit 12 causes the system clock signal C.
By selecting LK, the selector circuit 13 selecting the system reset signal RST, and the selector circuit 20 ₂ selecting the data signal DATA from the internal data bus 15, the same operation as the conventional parallel input / output port is performed. That is, when the system reset signal RST goes to "H" level while the control signal CONT is at "L" level, the registers 11 ₁ , 11 ₂ , ...
It is reset in synchronization with the rising edge of LK, "L" level data is written in each register 11 ₁ , 11 ₂ , ..., and each data output Q1, Q2, ... becomes "L" level (operation. ).

Subsequently, when the "H" level data signal DATA is input from the internal data bus 15 and the write enable signal ENBL becomes "H" level, the register 11
"H" level data in _one system clock signal CL
Since the data is written in synchronization with the rising edge of K, the data output Q1 of the register 11 ₁ becomes "H" level. As a result, the external port 18 ₁ becomes “H” level, and the control device 19 ₁ connected to the external port 18 ₁ operates (O
N) and start work (operation).

Next, when the control signal CONT goes to "H" level, the selector circuit 12 selects the output signal OUT3 of the OR gate 14, and the selector circuit 13 selects the register 11 _1.
Data output Q1 of the register 11 ₁ and the selector circuit 20 ₂ selects the data output Q1 of the register 11 ₁ (operation). When the work of the control device 19 ₁ is finished (OFF) and the interrupt signal int1 is generated from the control device 19 ₁ ,
The interrupt signal int1 registers 11 ₁ in synchronization with the reset, since the register 11 ₁ "L" level data is written, the register 11 ₁ of the data output Q1
Becomes "L" level. This allows the external port 18 ₁
Becomes "L" level.

Since the control signal CONT is at "H" level, the output signal OUT5 of the OR gate 21 ₂ is "H".
Enables (E) register 11 ₂ to reach level
The input also becomes "H" level. Since the data output Q1 of the register 11 ₁ is given to the data (D) input of the register 11 ₂ , the “H” level data held in the register 11 ₁ in synchronization with the interrupt signal int1 is transferred to the register 11 _1. This register 1 is written to ₂
The data output Q2 of 1 ₂ becomes "H" level. As a result, the external port 18 ₂ becomes “H” level, and the control device 19 ₂ connected to the external port 18 ₂ operates (O
N), start work (operation).

The control device 19 ₂ finishes its work (OFF).
Then, the interrupt signal int2 is generated. At this time,
Since the control signal CONT is at "H" level, the output signal OUT5 of the OR gate 21 ₂ is also at "H" level, and therefore the enable (E) input of the register 11 ₂ is also at "H" level. Since the data output Q1 of the register 11 ₁ is given to the data (D) input of the register 11 ₂ , the register 1 1 is synchronized with the interrupt signal int2.
1 ₁ data retention that had been "L" level is written into the register 11 _2, the data output Q2 of the register 11 ₂ is "L" level (operation).

The above operations are sequentially performed by the circuits of the third and subsequent stages, so that each time an interrupt signal int is generated, a plurality of control devices 19 ₁ connected to the external ports 18 ₁ , 18 ₂ ,. , 19 ₂ , ... Sequentially drive (ON) to get the work done.

As described above, in the parallel input / output port according to the first embodiment, the selector circuit 20 connected to the data (D) input of the second and subsequent registers.
_2, 20 _3, ... is by selecting the data output Q of the previous register one stage, the control device 19 _1, 19 _2, ... are generated at the end of each work interruption signal int1, i
By nt2, ..., the data held in the register of the previous stage is written in the register of the next stage, and the data of each register is shifted to the register of the next stage by an interrupt, so that each control device 19 ₁ , 19 ₂ , When driving ... in order to perform work, without interposing a CPU,
The following control devices can be driven.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In the second embodiment, the output signal OUT6 of the selector circuit 22 is given to the register 11 ₁ of the first stage as its data (D) input, and the output signal OU of the OR gate 23 as its enable (E) input.
T7 is given. The selector circuit 22 receives the data signal DATA from the internal data bus 15 and the final stage register 1
1 _n and a data output Q _n of the two inputs, the control signal CON
One of the two inputs is selected by T and used as the output signal OUT6. The OR gate 23 has a write enable signal ENB.
Two inputs are provided for L and the control signal CONT. The other configuration is the same as that of the first embodiment.

That is, in the first embodiment, only the data signal DATA from the internal data bus 15 is given as the data (D) input of the register 11 ₁ of the first stage, and the enable (E) input of the register 11 ₁ is applied. While only the write enable signal ENBL is applied as the above, the internal data bus 15 is used in the second embodiment.
From the data signal DATA or the final stage register 11 _n
The data output Q _n is used as the data (D) input, and the write enable signal ENBL or the control signal CONT is used as the enable (E) input.

Next, the circuit operation according to the second embodiment having the above configuration will be described with reference to the waveform chart of FIG.

First, when the control signal CONT is at "L" level, the selector circuit 22 selects the data signal DATA from the internal data bus 15. Further, the selector circuit 13 selects the system reset signal RST, the selector circuit 12 selects the system clock signal CLK, and the selector circuit 20 selects the data signal DATA from the internal data bus 15. Operates the same as a port. That is, when the system reset signal RST becomes "H" level while the control signal CONT is "L" level, the registers 11 ₁ , 11 ₂ , ...
, 11 _n are reset in synchronization with the rising of the system clock signal CLK, and registers 11 ₁ , 11 ₂ ,.
, 11 _n are written with "L" level data, and the respective data outputs Q1, Q2, ..., Qn are set to "L" level (operation).

Then, when the "H" level data signal DATA is input from the internal data bus 15 and the write enable signal ENBL becomes "H" level, the register 11
"H" level data in _one system clock signal CL
Written in synchronization with the rising edge of K, register 11 ₁
Data output Q becomes "H" level. As a result, the external port 18 ₁ becomes "H" level, and the control device 19 ₁ connected to the external port 18 ₁ operates (ON).
And start work (motion).

Next, when the control signal CONT becomes "H" level, the selector circuit 22 causes the final stage register 11 _n.
The data output Q _{n of} is selected. In addition, the selector circuit 12
Selects the output signal OUT3 of the OR gate 14, the selector circuit 13 selects the data output Q1 of the register 11 ₁ , and the selector circuit 20 selects the data output Q of the register 11 _1.
Select 1 (operation). When the work of the control device 19 ₁ is completed (OFF) and the interrupt signal int1 is generated from the control device 19 ₁ , the interrupt signal int1
Register 11 ₁ is reset in synchronization with
1 ₁ to the "L" level data is written, the data output Q1 becomes "L" level. This allows the external port 1
8 ₁ becomes "L" level.

Since the control signal CONT is at "H" level, the output signal OUT5 of the OR gate 21 ₂ is "H".
Enables (E) register 11 ₂ to reach level
The input also becomes "H" level. Since the data output Q1 of the register 11 ₁ is given to the data (D) input of the register 11 ₂ , the “H” level data held in the register 11 ₁ in synchronization with the interrupt signal int1 is transferred to the register 11 _1. written in the _2, the data output Q2 of the register 11 ₂ is set to the "H" level. As a result, the external port 18 ₂ becomes “H” level, and the external port 18 2
_The control device 19 ₂ connected to ₂ operates (ON),
Start work (motion).

The control device 19 ₂ finishes its work (OFF).
Then, the interrupt signal int2 is generated. At this time,
Since the control signal CONT is at "H" level, the output signal OUT5 of the OR gate 21 is also at "H" level, and the enable (E) input of the register 11 ₂ is also at "H" level. Since the data (D) input of the register 11 ₂ is given the data output Q1 of the register 11 ₁ ,
Data of the interrupt signal int2 synchronously held in the register 11 ₁ to the "L" level is written to the register 11 _2, the data output Q2 of the register 11 ₂ is "L" level (operation).

The above operations are sequentially performed by the circuits of the third and subsequent stages, so that each time an interrupt signal int is generated, a plurality of controls connected to the external ports 18 ₁ , 18 ₂ , ..., 18 _n are controlled. Device 19 ₁ , 19 ₂ , ..., 19 _n
Sequentially drive (ON) and let work. When the work of the control device 19 _n connected to the final stage external port 18 _n is completed (OFF), an interrupt signal intn is generated from this control device 19 _n . At this time, since the control signal CONT is at "H" level,
The output signal OUT7 of the OR gate 23 is also at the "H" level, so that the first-stage register 11 ₁ is enabled (E).
The input is also at "H" level.

Since the data output Qn of the register 11 _{n at} the final stage is selected and given to the data (D) input of the register 11 _{1 at} the first stage by the selector circuit 22, it is held in the register 11 _n at the final stage. Since the "H" level data that has been written is written in the register 11 ₁ in synchronization with the interrupt signal intn, the data output Q1 of the register 11 ₁ becomes "H" level. As a result, the external port 18 ₁ is set to the “H” level, so that the control device 19 ₁ connected to the external port 18 ₁ operates again (ON) and starts work (operation). Then, by performing the above operation, the control device connected to each external port is sequentially driven again to perform work.

As described above, in the parallel input / output port according to the second embodiment, when the control signal CONT is at "H" level, the data output Qn of the register 11 _{n at} the final stage is changed to the register at the first stage. By inputting the data (D) of 11 ₁ and the control signal CONT itself as the enable (E) input, in addition to the effect of the first embodiment, the work of the control device 19 _{n in} the final stage is performed. When the interrupt signal intn is generated after the end (OFF), the control device 19 ₁ of the first stage operates (ON) again to start the work. Therefore, each control device 19 ₁ , 19 ₂ , ..., 1
It is possible to obtain the effect that 9 _n can be driven again sequentially to perform work.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In the third embodiment, as an example, four control devices 19 _{1 to} 19 ₄ are driven. A control register 24 composed of a D-FF with a reset is provided for the _four control devices 19 _{1 to} 19 ₄ to switch the order in which they are sequentially driven. The control register 24 receives the system reset signal RST as a reset (R) input, the data signal DATA from the internal data bus 15 as a data (D) input, and enables the write enable signal ENBL (E).
The system clock signal CLK is used as an input and the system clock signal CLK is used as a clock (C) input, and for example, 2-bit data outputs Qa and Qb are generated according to the content of the data signal DATA.

Data output Qa, Qb of the control register 24
Are the control signals CONT1 and CONT2, the selector circuit 12, the selector circuit 13, and the selector circuits 20 ₂ to 20 2.
0 ₄ and OR gates 21 _{2 to} 21 ₄ , respectively. The control signals CONT1 and CONT2 are (0,0), (1,0), (0,1), (1,
Set the four patterns of 1). Here, logic "1"
Is at "H" level, and logic "0" is at "L" level.

The selector circuit 12 receives the system clock signal CLK and the output signal OUT3 of the OR gate 14 as two inputs, and the control signals CONT1 and CONT2 are (0, 0).
At that time, the system clock signal CLK is selected, and otherwise, the output signal OUT3 of the OR gate 14 is selected to be the output signal OUT1. The selector circuit 13 receives the system reset signal RST and the data output Q of the register 11 _1.
1 and 2 are input, the system reset signal RST is selected when the control signals CONT1 and CONT2 are (0, 0), and the data output Q1 of the register 11 ₁ is selected as the output signal OUT2 otherwise.

Second stage selector circuit 20₂Is an internal day
Data signal DATA from Tabus 15 and the first and third stages
Register 11 of the first and fourth stages₁, 11₃, 11_FourEach day of
Data output Q1, Q3, Q4 as four inputs and control signal CO
Data signal D when NT1 and CONT2 are (0,0)
When ATA is (1,0), the first-stage register 11 ₁
Of the data output Q1 of the third stage when (0, 1)
Star 11₃Data output Q3 of 4 when (1, 1)
Stage register 11_FourData output Q4 of each is selected
To do.

Third stage selector circuit 20₃Is an internal day
Data signal DATA from Tabus 15 and first and second stages
Register 11 of the first and fourth stages₁, 11₂, 11_FourEach day of
Control signals CO1, Q2, Q4 as four inputs, and control signal CO
Data signal D when NT1 and CONT2 are (0,0)
When ATA is (1,0), the second-stage register 11 ₂
Of the data output Q2 of the first register when (0, 1)
Star 11₁The data output Q1 of 2 is 2 when (1, 1)
Stage register 11₂Select each data output Q2
To do.

Fourth stage selector circuit 20_FourIs an internal day
Data signal DATA from Tabus 15 and first and second stages
1st and 3rd stage register 11₁, 11₂, 11₃Each day of
Control outputs CO1, Q2, and Q3 as four inputs.
Data signal D when NT1 and CONT2 are (0,0)
When ATA is (1,0), the third-stage register 11 ₃
Data output Q2 of the second stage when (0, 1)
Star 11₂Data output Q2 of 1 when (1, 1)
Stage register 11₁Select each data output Q1
To do.

Next, the circuit operation according to the third embodiment having the above configuration will be described. The control register 24 is
Data signal DA provided via internal data bus 15
Control signal CONT based on the content (data value) of TA
1, CONT2 sets four patterns (0,0), (1,0), (0,1), (1,1) as a control mode.

First, when the control signals CONT1 and CONT2 are (0, 0), the selector circuit 12 selects the system clock signal CLK, the selector circuit 13 selects the system reset signal RST, and the selector circuit 20.
_{2 to} 20 ₄ select the data signal DATA from the internal data bus 15 to perform the same operation as the conventional parallel input / output port. In addition, the control signals CONT1, CO
When NT2 is (1,0), the selector circuit 12 is O
The output signal OUT3 of the R gate 14 is selected, and the selector circuit 13 and the selector circuit 20 ₂ both register 11 ₁
Data output Q1 of the selector circuit ₂ and the selector circuit 20 ₃ selects the data output Q2 of the register 11 2.
When 0 ₄ selects the data output Q3 of the register 11 ₃ , the same operation as in the first embodiment is performed. That is, the control device 19 ₁ → the control device 19 ₂ → the control device 19 ₃ → the control device 19 ₄ are driven in this order.

Next, the operation when the control signals CONT1 and CONT2 are (0, 1) will be described with reference to the waveform chart of FIG. In this embodiment, when the "H" level data signal DATA is input from the internal data bus 15 and the write enable signal ENBL becomes "H" level, first, the register 11 ₁ of the first stage is set to "H" level. The data is written so that the first-stage control device 19 ₁ always operates (ON) first and starts the work.

The control signals CONT1 and CONT2 are (0,
1), the selector circuit 12 outputs the output of the OR gate 14.
Output signal OUT3, and the selector circuit 13 is a register
11 ₁Data output Q1 is selected. Also, selector times
Road 20₂Is register 11₃Select the data output Q3 of
Circuit 20₃Is register 11₁Data output Q1 of
Rector circuit 20_FourIs register 11₂Data output of Q2
Select each (action). Then, the control device 19₁
Job is completed (OFF), interrupt signal int1 is issued
When it occurs, the register is registered in synchronization with this interrupt signal int1.
Type 11₁Is reset, register 11₁"L" level
Data is written to the register 11 ₁Data output
Q1 becomes "L" level. Therefore, the external port 18₁
Becomes "L" level.

Here, the control signals CONT1 and CONT2
Since one of them is at the “H” level, the OR gate 21
_{2 to} 21 ₄ output signals OUT5 _{2 to} OUT5 ₄ are "H"
Since it is at the level, the enable (E) inputs of the registers 11 _{2 to} 11 ₄ also become the “H” level. Since the data (D) input of the register 11 ₃ is given the data output Q1 of the register 11 ₁ via the selector circuit 20 ₃ ,
The “H” level data held in the register 11 ₁ until then is synchronized with the register 1 in synchronization with the interrupt signal int1.
Written in the 1 _3, data output Q3 of register 11 ₃ becomes "H" level. Therefore, the external port 18 ₃ becomes “H” level, the control device 19 ₃ connected to the external port 18 ₃ operates (ON), and starts work (operation).

When the work is completed (OFF), the control device 19 ₃ generates the interrupt signal int3. At this time, the enable (E) inputs of the registers 11 _{2 to} 11 ₄ are “H”.
Are at level, the data (D) input of the register 11 _3, since the register 11 ₁ of the data output Q1 via the selector circuit 20 ₃ is provided, held in the register 11 ₁ at the "L" level data Is the interrupt signal in
It is written in the register 11 ₃ in synchronization with t3. Therefore, the data output Q3 of the register 11 ₃ becomes "L" level. As a result, the external port 18 ₃ becomes "L" level.

[0047] At the same time, the register 11 _{and second} data (D) input, since the register 11 ₃ data output Q3 via the selector circuit 20 ₂ is supplied, the register 11 ₃
Since the "H" level data held until then is written to the register 11 ₂ in synchronization with the interrupt signal int3, the data output Q2 of the register 11 ₂ becomes "H" level. Therefore, the external port 18 ₂ becomes “H” level and the control device 1 connected to the external port 18 ₂
9 ₂ operates (ON) and starts work (operation).

Further, the work of the control device 19 ₂ is completed (O
FF), and the interrupt signal int2 is generated, the register 11 _{and second} data (D) input, the selector circuit 20 ₂
Since the data output Q3 of register 11 ₃ is supplied through the, held in the register 11 ₃ "L" level data is written in synchronism with the register 11 ₂ to the interrupt signal int2, the register 11 ₂ The data output Q2 becomes "L" level. This allows the external port 1
8 ₂ becomes “L” level.

[0049] At the same time, the data (D) input of the register 11 _4, since the register 11 ₂ data output Q2 via the selector circuit 20 ₄ is supplied, the register 11 ₂
Then, the "H" level data that has been held until then is written to the register 11 ₄ in synchronization with the interrupt signal int2, and the data output Q4 of the register 11 ₄ becomes the "H" level. As a result, the external port 18 ₄ becomes “H” level, the control device 19 ₄ connected to the external port 18 ₄ operates (ON), and starts work (operation).

Then, the work of the control device 19 ₄ is completed (O
FF), and the interrupt signal int4 is generated, the data (D) input of the register 11 _4, a selector circuit 20 ₄
Since the register 11 ₂ data output Q2 is provided via, held in the register 11 ₂ "L" level data is written in synchronism with the register 11 ₄ to the interrupt signal int4, the register 11 ₄ The data output Q4 becomes "L" level. This allows the external port 1
8 ₄ becomes the "L" level (operation).

Through the above series of operations, the control signal CON
When T1 and CONT2 are (0, 1), the control device 1
9 ₁ → control device 19 ₃ → control device 19 ₂ → control device 19
It will be driven in the order of ₄ .

Next, the operation when the control signals CONT1 and CONT2 are (1,1) will be described with reference to the waveform chart of FIG. As in the case of the previous control mode, "H" level data is written in the first-stage register 11 ₁ and
In the state where the control device 19 _{1 in the} second stage operates (ON) first and is performing work, the control signals CONT1, CO
When NT2 becomes (1, 1), the selector circuit 13 selects the data output Q1 of the register 11 ₁ , and the selector circuit 1
2 selects the output signal OUT3 of the OR gate 14.

Further, the selector circuit 20₂Is register 11
_FourData output Q4 of the selector circuit 20₃Is a register
11₂Data output Q2 of the selector circuit 20_FourCash register
Star 11₁Data output Q1 of each (operation
). Then, the control device 19 ₁Work ends (OFF)
Then, when the interrupt signal int1 is generated, this interrupt
Register 11 in synchronization with signal int1₁Is reset
Register 11₁"L" level data is written to
Register 11₁Data output Q1 of "L" level
Become. This allows the external port 18₁Is "L" level
Become.

Here, the control signals CONT1 and CONT2
Is at the "H" level, the OR gates 21 ₂ to 2
Because of the 1 _fourth output signal OUT5 ₂ ~OUT5 ₄ "H" level, the register 11 ₂ to 11 ₄ enable (E) is also input becomes "H" level. The register 11 _fourth data (D) input, since the register 11 ₁ of the data output Q1 via the selector circuit 20 ₄ is applied, has been held so far in the register 11 ₁ "H" level data interrupt Register 11 in synchronization with signal int1
₄ to be written, data output Q4 of the register 11 ₄ becomes "H" level. As a result, the external port 18 ₄ becomes “H” level, the control device 19 ₄ connected to the external port 18 ₄ operates (ON), and starts work (operation).

When the work is completed (OFF), the control device 19 ₄ generates the interrupt signal int4. At this time, the enable (E) inputs of the registers 11 _{2 to} 11 ₄ are “H”.
Are at level, the register 11 ₄ data (D) input, since the register 11 ₁ of the data output Q1 via the selector circuit 20 ₄ is provided, held in the register 11 ₁ at the "L" level data Is the interrupt signal in
It is written in the register 11 ₄ in synchronization with t4. Therefore, the data output Q4 of the register 11 ₄ is "L" level. As a result, the external port 18 ₄ becomes "L" level.

[0056] At the same time, the register 11 _{and second} data (D) input, since the data output Q4 of the register 11 ₄ via the selector circuit 20 ₂ is supplied, the register 11 ₄
Then, the "H" level data that has been held until then is written to the register 11 ₂ in synchronization with the interrupt signal int4, and the data output Q2 of this register 11 ₂ becomes "H" level. As a result, the external port 18 ₂ becomes “H” level, the control device 19 ₂ connected to the external port 18 ₂ operates (ON), and starts work (operation).

Further, the work of the control device 19 ₂ is completed (O
FF), and the interrupt signal int2 is generated, the register 11 _{and second} data (D) input, the selector circuit 20 ₂
Since the data output Q4 of the register 11 ₄ is supplied via a register 11 ₄ has been held in the "L" level data is written in synchronism with the register 11 ₂ to the interrupt signal int2, the register 11 ₂ The data output Q2 becomes "L" level. This allows the external port 1
8 ₂ becomes “L” level.

[0058] At the same time, the data (D) input of the register 11 _3, since the register 11 ₂ data output Q2 via the selector circuit 20 ₃ is supplied, the register 11 ₂
Then, the "H" level data that has been held until then is written to the register 11 ₃ in synchronization with the interrupt signal int2, and the data output Q3 of the register 11 ₃ becomes the "H" level. As a result, the external port 18 ₃ becomes "H" level, the control device 19 ₃ connected to the external port 18 ₃ operates (ON), and starts work (operation).

Then, the work of the control device 19 ₃ is completed (O
FF), and the interrupt signal int3 is generated, the data (D) input of the register 11 _3, the selector circuit 20 ₃
Since the register 11 ₂ data output Q2 is provided via, held in the register 11 ₂ "L" level data is written in synchronism with the register 11 ₃ to the interrupt signal int3, the register 11 ₃ The data output Q3 becomes "L" level. This allows the external port 1
8 ₃ becomes "L" level (operation).

By the above series of operations, the control signal CON
When T1 and CONT2 are (1,1), the control device 1
9 ₁ → control device 19 ₄ → control device 19 ₂ → control device 19
It will be driven in the order of ₃ .

As described above, in the parallel input / output port according to the third embodiment, the control register that generates the control signals CONT1 and CONT2 for controlling the selector circuit 12, the selector circuit 13, and the selector circuits 20 _{2 to} 20 _4. 24 is provided, and selector circuits 20 _{2 to} 20
_Since the data output of the register of the other stage is given to 4, the data output Qa and Qb of the control register 24 is connected to each external port by being programmable in addition to the effect of the first embodiment. It is possible to obtain the effect that the order in which the control devices are driven can be arbitrarily changed.

In the third embodiment, the control device is
Setting 19₁→ Control device 19₂→ Control device 19₃→ Control device
19_FourOut of the order of the control device 19₁→ Control device 19₃
→ Control device 19₂→ Control device 19_FourAnd control device 19
₁→ Control device 19_Four→ Control device 19₂→ Control device 19₃
2 patterns are set, the selector circuit 20 ₂
~ 20_FourBy changing the configuration of the control device 19₁
→ Control device 19_Four→ Control device 19₃→ Control device 19₂Na
Any other pattern can be set.

Further, although the control register 24 having a 2-bit structure can be used to set the control pattern of 4 (= 2 ² ) patterns, the control register 24 is not limited to this, and the control register 24 may have, for example, 3 bits. By using the bit configuration, it is possible to set the control form of 8 (= 2 ³ ) patterns.

Further, in the third embodiment, the control device 19 _{1 in the} first stage is always driven first in order, but a selector circuit is also provided at the data (D) input of the register 11 _{1 in} the first stage. , In addition to the data signal DATA from the internal data bus 15, 2
To each data output Q2 of the registers 11 _{2 to} 11 ₄ of the fourth stage
By giving ~ Q4, it becomes possible to arbitrarily set the driving order including the control device 19 ₁ of the first stage.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.
It is a lock diagram, and in FIG.
It is attached. In this fourth embodiment, the register
11 ₁, 11₂, Select to give a clock to each of
Circuit circuit 25 interrupts the system clock signal CLK
The interrupt from the timer counter circuit 26, which is a signal generation circuit,
The input signal UDF and 2 inputs, and the control signal CONT
Therefore, one of the two inputs is selected and the register 11₁, 1
1₂, ... Each clock is supplied as a clock (C) input.
It has become successful.

The timer counter circuit 26 has a control signal CONT for controlling the counting operation enabled (E) input, an external clock signal ECLK input as a clock (C),
A fixed value is used as data (D) input, and an interrupt signal UDF is output when a down count underflow occurs. The interrupt signal UDF serves as one input of the selector circuit 25 as described above and also serves as one input of the OR gate 27. The OR gate 27 receives the system reset signal RST as the other input, and its output as the set (S) input of the timer counter circuit 26.

Next, the circuit operation according to the fourth embodiment having the above configuration will be described with reference to the waveform chart of FIG.

First, when the control signal CONT is at "L" level, the selector circuit 13 outputs the system reset signal R.
By selecting ST, the selector circuit 25 selects the system clock signal CLK, and the selector circuit 20 ₂ selects the data signal DATA from the internal data bus 15 to perform the same operation as the conventional parallel input / output port. That is, when the system reset signal RST goes to "H" level while the control signal CONT is at "L" level, the registers 11 ₁ , 11 ₂ , ...
It is reset in synchronization with the rising edge of LK, "L" level data is written in each register 11 ₁ , 11 ₂ , ..., and each data output Q1, Q2, ... becomes "L" level (operation. ).

Subsequently, when the "H" level data signal DATA is input from the internal data bus 15 and the write enable signal ENBL becomes "H" level, the register 11
"H" level data in _one system clock signal CL
Written in synchronization with the rising edge of K, register 11 ₁
Data output Q becomes "H" level. As a result, the external port 18 ₁ becomes "H" level, and the control device 19 ₁ connected to the external port 18 ₁ operates (ON).
And start work (motion).

Next, when the control signal CONT goes to "H" level, the timer counter circuit 26 starts down counting in synchronization with the external clock signal ECLK, and the selector circuit 25 causes the down counting of the timer counter circuit 26 to be under. Select the interrupt signal UDF when a flow occurs. Further, the selector circuit 13 selects the data output Q1 of the register 11 ₁ , and the selector circuit 20 ₂ selects the data output Q1 of the register 11 ₁ (operation).

When an underflow occurs in the timer counter circuit 26, its interrupt signal UDF
Also serves as a set (S) input to the timer counter circuit 26 via the OR gate 27. Then, a fixed value is set in the timer counter circuit 26 by this set (S) input, and the timer counter circuit 26 starts counting down again. Then, the data output Q1 of the register 11 ₁
Causes the register 11 ₁ to synchronize with the interrupt signal UDF.
Are reset, the data of "L" level is written in the register 11 ₁ , and the data output Q1 becomes "L" level. As a result, the external port 18 ₁ becomes "L" level.

Since the control signal CONT is at "H" level, the output signal OUT5 of the OR gate 21 ₂ is "H".
Enables (E) register 11 ₂ to reach level
The input also becomes "H" level. Since the data output Q1 of the register 11 ₁ is given to the data (D) input of the register 11 ₂ , the “H” level data held in the register 11 ₁ in synchronization with the interrupt signal int1 is transferred to the register 11 _1. written in the _2, the data output Q2 of the register 11 ₂ is set to the "H" level. As a result, the external port 18 ₂ becomes “H” level, and the external port 18 2
_The control device 19 ₂ connected to ₂ operates (ON),
Start work (motion).

Again, the timer counter circuit 26 is under
When a flow is generated, the control signal CONT is at "H" level
Therefore, the OR gate 21₂Output signal OUT5
Is also at the “H” level, and therefore register 11₂Noi
The enable (E) input is also at "H" level. Register 1
1₂The data (D) input of₁data from
Since output Q1 is given, underflow causes
Register 11 in synchronization with interrupt signal UDF₁Held in
The “L” level data stored in the register 11 ₂Write on
This register 11₂Data output of Q2
It becomes "L" level (operation).

The above operations are sequentially performed by the circuits of the third and subsequent stages, so that a plurality of control devices connected to the external ports 18 ₁ , 18 ₂ , ... Each time the interrupt signal int is generated. Sequentially drive (ON) 19 ₁ , 19 ₂ , ... to let them do their work.

As described above, in the parallel input / output port according to the fourth embodiment, the external clock signal EC
A timer counter circuit 26 is provided which counts down in synchronization with LK and sets a fixed value when an underflow occurs. When the control signal CONT is at the "H" level, an interrupt signal UDF when the downcount underflow occurs. Causes the control device of the next stage to operate (ON),
By starting the work, when the control devices are sequentially driven for a certain fixed time to perform the work, an interrupt generated at a certain fixed time is interrupted by C
Compared to what the PU processes and drives the next controller,
It is possible to sequentially drive each control device for each fixed value set in the timer counter circuit 26 to perform work without waiting for the interrupt processing time of the CPU.

In the fourth embodiment, a timer counter circuit 26 including a down counter is used as an interrupt signal generating circuit for generating an interrupt signal at regular time intervals.
However, a timer counter circuit including an up counter may be used, and the counter circuit is not limited to the counter circuit, and may be any circuit having a circuit configuration capable of generating an interrupt signal at regular time intervals.

FIG. 10 is a block diagram showing a fifth embodiment of the present invention. In the figure, the same parts as those in FIG. 8 are designated by the same reference numerals. In the fifth embodiment, when an underflow occurs in the timer counter circuit 26,
A timer reload data register circuit 28, which is a time setting circuit for giving an arbitrary set value to the data (D) input of the timer counter circuit 26, is provided. The timer reload data register circuit 28 resets the system reset signal RST (R). The system clock signal CLK is supplied as a clock (C) input, the write enable signal ENBL is supplied as an enable (E) input, and the data signal DATA from the internal data bus 15 is supplied as a data (D) input. ing.

That is, when an underflow occurs in the timer counter circuit 26, in the fourth embodiment,
While a preset fixed value is set in the timer counter circuit 26, in the fifth embodiment,
An arbitrary set value set in the timer reload data register circuit 28 is set by the data signal DATA from the internal data bus 15.

Next, the circuit operation according to the fifth embodiment having the above configuration will be described with reference to the waveform chart of FIG.

First, when the control signal CONT is at "L" level, the selector circuit 13 causes the system reset signal R
By selecting ST, the selector circuit 25 selects the system clock signal CLK, and the selector circuit 20 ₂ selects the data signal DATA from the internal data bus 15 to perform the same operation as the conventional parallel input / output port. That is, when the system reset signal RST goes to "H" level while the control signal CONT is at "L" level, the registers 11 ₁ , 11 ₂ , ...
It is reset in synchronization with the rising edge of LK, "L" level data is written in each register 11 ₁ , 11 ₂ , ..., and each data output Q1, Q2, ... becomes "L" level (operation. ).

Subsequently, when the data signal DATA of "H" level is input from the internal data bus 15 and the write enable signal ENBL becomes "H" level, the register 11
"H" level data in _one system clock signal CL
Written in synchronization with the rising edge of K, register 11 ₁
Data output Q becomes "H" level. As a result, the external port 18 ₁ becomes "H" level, and the control device 19 ₁ connected to the external port 18 ₁ operates (ON).
And start work (motion).

Next, when the control signal CONT becomes the "H" level, the timer counter circuit 26 starts down counting in synchronization with the external clock signal ECLK, and the selector circuit 25 causes the down counting of the timer counter circuit 26 to be under. Select the interrupt signal UDF when a flow occurs. Further, the selector circuit 13 selects the data output Q1 of the register 11 ₁ , and the selector circuit 20 ₂ selects the data output Q1 of the register 11 ₁ (operation).

When an underflow occurs in the timer counter circuit 26, the interrupt signal UDF for the underflow occurs.
Also serves as a set (S) input to the timer counter circuit 26 via the OR gate 27. Then, the timer counter circuit 26 sets an arbitrary set value of the timer reload register circuit 28 by this set (S) input, and the timer counter circuit 26 starts down counting again. An arbitrary value is set in the timer reload register circuit 28 by the data signal DATA from the internal data bus 15.

Then, the data output Q1 of the register 11 ₁
Causes the register 11 ₁ to synchronize with the interrupt signal UDF.
Are reset, the data of "L" level is written in the register 11 ₁ , and the data output Q1 becomes "L" level. As a result, the external port 18 ₁ becomes "L" level. Since the control signal CONT is at "H" level,
Since the output signal OUT5 of the OR gate 21 becomes "H" level, the enable (E) input of the register 11 ₂ also becomes "H" level.

This register 11₂Input data (D)
Is register 11₁Data output Q1 of
From the register 11 in synchronization with the interrupt signal int1₁
“H” level data held in the register 11
₂Written to this register 11₂Data output Q2
Becomes "H" level. This allows the external port 18 ₂
Goes to "H" level and the external port 18₂Connected to
Control device 19₂Works (ON) and starts work
(motion).

Again, the timer counter circuit 26 is under
When a flow is generated, the control signal CONT is at "H" level
Therefore, the OR gate 21₂Output signal OUT5
Is also at the “H” level, and therefore register 11₂Noi
The enable (E) input is also at "H" level. Register 1
1₂The data (D) input of₁data from
Since output Q1 is given, underflow causes
Register 11 in synchronization with interrupt signal UDF₁Held in
The “L” level data stored in the register 11 ₂Write on
This register 11₂Data output of Q2
It becomes "L" level (operation).

The above operations are sequentially performed by the circuits of the third and subsequent stages, so that a plurality of control devices connected to the external ports 18 ₁ , 18 ₂ , ... Each time the interrupt signal int is generated. Sequentially drive (ON) 19 ₁ , 19 ₂ , ... to let them do their work.

As described above, in the parallel input / output port according to the fifth embodiment, the timer reload data register circuit 28 in which an arbitrary value is set by the data signal DATA from the internal data bus 15 is provided and external A timer counter circuit 26 is provided which counts down in synchronization with the clock signal ECLK, and when an underflow occurs, the set value of the timer reload data register circuit 28 is set. When the control signal CONT is at "H" level, the counter counts down. The control signal of the next stage is activated (ON) by the interrupt signal UDF when the underflow occurs to start the work. In addition to the effect of the fourth embodiment, the timer reload data register circuit 28 causes the timer to reload. Counter circuit 2
There is an effect that each control device can be driven sequentially for each arbitrary set value set to 6 to perform work.

[0089]

As described above in detail, according to the present invention, the selector circuit connected to the data input of the register of the second and subsequent stages selects the data output of the register of the previous stage and each control device. By writing the data held in the register of the previous stage to the register of the next stage by the interrupt signal generated at the end of each work, the register of the previous stage is generated each time an interrupt signal is generated from each control device. Since the data output of 1 is sequentially shifted to the register of the next stage, it can be processed without intervention of the CPU. Therefore, when each control device is driven sequentially to perform work, the time required for the sequential processing can be shortened by the time required for the interrupt processing of the CPU.

Further, according to the present invention, the selector circuit connected to the data input of the register of the second and subsequent stages selects the data output of the register of the preceding stage, and the interrupt signal generated at a constant time causes the preceding stage to generate data. By writing the data held in the register of the next stage to the register of the next stage, the data output of the register of the previous stage is sequentially shifted to the register of the next stage at a constant cycle.
It can be processed without U. Therefore, when each control device is driven sequentially to perform work, the time required for the sequential processing can be shortened by the time required for the interrupt processing of the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram according to the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a waveform diagram according to the second embodiment.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a waveform diagram (part 1) according to the third embodiment.

FIG. 7 is a waveform diagram (No. 2) according to the third embodiment.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a waveform diagram according to the fourth embodiment.

FIG. 10 is a block diagram showing a fifth embodiment of the present invention.

FIG. 11 is a waveform diagram according to the fifth embodiment.

FIG. 12 is a block diagram showing a conventional example.

FIG. 13 is a waveform diagram according to a conventional example.

[Explanation of symbols]

11 ₁ , 11 ₂ , ..., 11 _n registers 12, 13, 22, 25 Selector circuits 17 ₁ , 17 ₂ , ..., 17 _n output buffers 18 ₁ , 18 ₂ , ..., 18 _n External port 19 ₁ , 19 ₂ , ..., 19 _n Control device 20 ₁ , 20 ₂ , ..., 20 _n Selector circuit 24 Control register 26 Timer counter circuit 28 Timer reload data register circuit

Claims (5)

(57) [Claims] 1. A parallel input / output port, which is connected to a plurality of external ports and drives and controls a plurality of control devices that generate an interrupt signal when each work is completed, and data supplied from a data bus as a data input. A register group including a first-stage register for storing signals and a plurality of registers of the second and subsequent stages arranged in parallel to the first-stage register, a system reset signal, and a data output signal of the first-stage register as two inputs, A first selector circuit that selects either one of them according to a predetermined control signal and uses it as a reset input of the register in the first stage, and an OR that inputs each interrupt signal of the plurality of control devices
A gate, a system clock signal, and an output signal of the OR gate as two inputs, and a second selector that selects one of them as a clock input of the register of the first stage and the plurality of registers according to the control signal. A circuit, and the data signal and the data output signal of the previous register in the register group are two inputs, and one of them corresponds to one of the plurality of registers according to the control signal .
Parallel input / output port, comprising: a plurality of third selector circuits that are used as data inputs to registers . 2. A fourth selector circuit in which the data signal and the data output signal of the final stage register in the register group are two inputs, and one of them is the data input of the first stage register in accordance with the control signal. The parallel input / output port according to claim 1, further comprising: 3. A control register for outputting a plurality of bits of data indicating a control mode for the plurality of control devices based on a data input, wherein the plurality of third selector circuits include the data signal and the register group. The data output signal of the register of another stage is input, and one of the plurality of inputs is selected based on the data output signal of the control register to be each data input of the plurality of registers. claim 1 Symbol placement of the parallel input and output ports. 4. A parallel input / output port for driving and controlling a plurality of control devices connected to a plurality of external ports, wherein a first-stage register and a first-stage register for storing a data signal supplied as a data input from a data bus are provided. On the other hand, a register group consisting of a plurality of registers of the second and subsequent stages arranged in parallel with each other, a system reset signal and a data output signal of the register of the first stage are set as two inputs, and one of them is selected according to a predetermined control signal. Then, a first selector circuit which is used as a reset input of the register of the first stage, an interrupt signal generation circuit which generates an interrupt signal at regular time intervals, a system clock signal and the interrupt signal are input as two inputs, and depending on the control signal. One of them to be used as each clock input of the register in the first stage and the plurality of registers. And second selector circuit, wherein the 2 inputs the data output signal of the previous register in the data signal and the register group corresponding to one of either one of said plurality registers in response to said control signal
Parallel input / output port, comprising: a plurality of third selector circuits that are used as data inputs to registers . 5. The parallel input / output port according to claim 4, further comprising a time setting circuit that sets a fixed time in the interrupt signal generation circuit to an arbitrary time.