JP3529585B2 - Signal control circuit, waveform generation circuit, and signal multiplexing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention has a high operation speed,
A semiconductor circuit having a large phase margin, in particular, a waveform generation circuit for converting an input clock pulse train into a desired signal train, and operating with the signal train, time-division-multiplexing a plurality of input signal trains, The present invention relates to a signal multiplexing circuit that obtains an output signal train.

[0002]

2. Description of the Related Art As an example of the prior art close to the present invention, a 2: 1 signal multiplexing circuit (source-coupled field-effect transistor logic circuit (SCFL) is used to convert two signal strings into one signal string ( References M. Ohhata et a1, “11Gbit / s MU
LTIPLEXER AND DEMULTIPLEXERUSING 0.15 μm GaAs MESF
ETs ”, Electron. Lett., 1990, 26, p467) is shown in Fig. 18. This conventional circuit has two input signal trains CH.
It has a function of time-division multiplexing 1 and CH2 and outputting from Q as one signal sequence.

The configuration of the conventional circuit will be described. This conventional circuit includes a toggle flip-flop circuit MS-TFF, two delay flip-flop circuits MS-DFF1 and 2, a tristage delay flip-flop circuit TS-DF.
F, a selector circuit SEL.

The operation of the conventional circuit will be described. The toggle flip-flop circuit has a clock signal (1/2) of the frequency of the clock signal input to the CLK terminal.
CLK), which is a so-called ½ frequency divider, and the operations of the delay flip-flop circuit, the tristage flip-flop circuit, and the selector circuit in the conventional circuit are the ½ frequency-divided clock signal (1 / 2 CLK).

The delay flip-flop circuit stores the input signal to the D terminal at the time when the voltage applied to the C terminal changes from the high potential to the low potential, and immediately stores the value as Q.
As the output of the terminal, even if the voltage applied to the C terminal changes from the low potential to the high potential, the output is not changed, and the value is maintained until the voltage applied to the C terminal changes from the high potential to the low potential again. Is a circuit that continues to output.

The tristage flip-flop circuit stores the input signal to the D terminal at the time when the voltage applied to the C terminal changes from the high potential to the low potential, and the voltage applied to the C terminal changes from the low potential to the high potential. When the potential changes, the stored value becomes the output of the Q terminal. Further, even if the voltage applied to the C terminal changes from the high potential to the low potential, only the input signal to the D terminal at that time is stored, the output of the Q terminal is not changed, and the voltage is again applied to the C terminal. It is a circuit that does not change the output of the Q terminal until the voltage changes from a low potential to a high potential.

When two signal sequences having the same phase are simultaneously input to the delay flip-flop circuit and the tristage flip-flop circuit which are controlled by the same clock signal (1/2 CLK), both circuits described above , The two signal trains have a phase of 1 / 2C of each other.
It is output in a state where it is shifted by a half cycle of the LK clock signal,
It is directly input to the selector circuit of the next stage.

The selector circuit has two input terminals (D1, D
It is a circuit which has 2) and alternately selects and outputs one of the inputs D1 and D2 according to the level of the voltage input to the S terminal. As described above, when the 1/2 CLK clock signal is input to the S terminal, the selector circuits have a mutual phase of ½.
When a signal train shifted by a half cycle of the clock signal of CLK is input, it becomes possible to alternately obtain values from the two signal trains with a phase margin of 180 °.

FIG. 19 is an example of a timing diagram showing a series of multiplexing operations in the circuit of FIG.
As shown in FIG. 19, the circuit operation is possible even if the phases of D1 and D2 deviate from the S terminal by ± 180 °.
Thus, in the selector circuit SEL, two signal strings are
It is multiplexed into one signal sequence and this is used as the output (SQ).

The delay flip-flop circuit MS-DFF2 following the selector circuit SEL is controlled in operation by a clock (CLK) given from the outside, and functions to reproduce the signal level of the signal sequence SQ multiplexed by the selector circuit. Output SQ according to the falling edge of CLK,
That is, it has a function of synchronizing the external clock with the multiplexed signal train. Due to the function of each circuit as described above, two signal trains can be multiplexed into one signal train.

[0011]

The conventional circuit as described above is characterized in that the phase margin of the circuit is expanded. As a result, the number of elements constituting the circuit is increased, for example, the tristage delay flip-flop circuit TS. -DF
In F, as shown in FIG. 20, the scale of the circuit is expanded and the configuration is complicated. Such expansion of circuit scale and complication of configuration are incompatible with reduction of power consumption and improvement of operation speed.
This is a problem of the conventional technology.

The present invention has been made to solve the problems of the prior art as described above, and realizes multiplexing a plurality of signal trains into one signal train with a simple circuit configuration. It is intended to simultaneously realize reduction of power consumption of a semiconductor circuit, improvement of operation speed, and expansion of phase margin.

[0013]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, the invention according to claim 1 relates to the configuration of the signal control circuit, and this configuration corresponds to the signal control circuit in the embodiment shown in, for example, FIGS.

[0014]

Further, the invention according to claim 2, which related to the structure of the waveform generation circuit, the arrangement 1, for example
This corresponds to the configuration for generating the three signal waveforms described in 0.

Further, claim 3 relates to a configuration of a signal multiplexing circuit using the signal control circuit according to claim 1, and this configuration corresponds to, for example, the embodiment shown in FIGS. 1 to 4. To do.

A fourth aspect of the present invention relates to the configuration of a signal multiplexing circuit using the signal control circuit of the first aspect and the waveform generating circuit of the second aspect . This configuration is, for example, This corresponds to the embodiment shown in FIGS. 11 to 13.

A fifth aspect of the present invention relates to a generalized configuration of the signal multiplexing circuit of the present invention, wherein n input signal sequences of f bits per second (bps) are multiplexed to obtain one n.
The configuration is such that a signal train of f (bps) is obtained. This configuration corresponds to, for example, the embodiment shown in FIG.

Further, claim 6 relates to a specific structure of the first partial circuit in claims 1 to 5 , and shows a structure using a negative differential resistance element and a field effect transistor. . This configuration corresponds to, for example, the first partial circuit shown in FIG.

Further, claim 7 relates to a specific structure of the second partial circuit in claims 1 to 5 , and shows a structure using a negative differential resistance element and a field effect transistor. . This configuration corresponds to, for example, the second partial circuit shown in FIG.

Further, claim 8 and claim 9
6 or 7 shows a specific example of the negative differential resistance element, claim 8 uses a resonant tunneling diode, and claim 9 uses an Esaki diode.

Further, a tenth aspect shows a structure in which a bipolar transistor is used instead of the field effect transistor in the sixth or seventh aspect .

With the above construction, in the present invention, a partial circuit for performing the operation described in claim 1, specifically, a negative differential resistance element as described in claim 7 or claim 8. By utilizing the non-linear current-voltage characteristic of the negative differential resistance element by using a partial circuit using the signal, the signal multiplexing circuit and its signal can be obtained by a simple circuit in which the number of elements is reduced to a fraction of that of the prior art. A signal for controlling the multiplexing circuit can be obtained.

[0024]

DETAILED DESCRIPTION OF THE INVENTION

(1) When Two Signal Sequences are Multiplexed An embodiment of the present invention when two signal sequences are multiplexed will be described. In the present embodiment in which two f-bit per second (bps) signal sequences are multiplexed to obtain one 2f (bps) signal sequence, in the operation of the signal multiplexing circuit, the frequency f (H
In z), two signals (which can be a clock signal of frequency f and its inverted signal) whose phases are shifted from each other by 1/2 cycle are required.

Various examples of the signal multiplexing circuit according to the present invention are shown in FIGS. All of the signal multiplexing circuits shown in FIGS. 1 to 4 include two signal control circuits each including at least one of a first partial circuit and a second partial circuit, and an OR circuit (OR circuit or NOR circuit). Consists of two signal string input terminals (D1, D2) and two power supply terminals (Vcon
1, Vcon2) and one output terminal (Q). A positive phase and a negative phase (for example, Vcon1 is a positive phase and Vcon2 is a negative phase) of the clock signal are applied to the two power supply terminals, respectively.

Here, in the first partial circuit, for example, as shown in FIG. 1, the emitter electrode of the first negative differential resistance element NR1 is grounded and the collector electrode of the second negative differential resistance element NR2 is connected to the ground. First negative differential resistance element N connected to the power supply terminal
By connecting the collector electrode of R1 and the emitter electrode of the second negative differential resistance element NR2, a field effect transistor FET
In this circuit, the drain electrode and the source electrode of No. 1 are connected to the collector electrode and the emitter electrode of the first negative differential resistance element NR1, respectively, and the gate potential of the field effect transistor is input and the drain potential is output.

In the second partial circuit, for example, as shown in FIG. 2, the emitter electrode of the first negative differential resistance element NR1 is grounded and the collector electrode of the second negative differential resistance element NR2 is a power source. Connected to the terminal, the first negative differential resistance element NR
The collector electrode of 1 and the emitter electrode of the second negative differential resistance element NR2 are connected to each other, and the field effect transistor FET2
Is a circuit in which the drain electrode and the source electrode are connected to the collector electrode and the emitter electrode of the second negative differential resistance element NR2, respectively, and the gate potential of the field effect transistor is input and the source potential is output. As the negative differential resistance elements NR1 and NR2, for example, a resonance tunnel diode or an Esaki diode can be used.

First, the first embodiment shown in FIG. 1 will be described. The signal multiplexing circuit of FIG. 1 includes a signal control circuit 1 including only one first partial circuit, a signal control circuit 2 having the same configuration as the signal control circuit 1, and signal control circuits 1 and 2. NOR circuit 3 to which outputs (Q1, Q2) are input
Consists of.

In the circuit of FIG. 1, input terminals D1 and D2
When a signal string of f (bps) to be multiplexed is input to Vcon1, the signal control circuit 1 outputs an inverted signal of the value input to the input terminal D1 as Q1 while Vcon1 is at a high potential. Is low, the low potential L is always output as Q1. On the other hand, in the signal control circuit 2, the inverted signal of the value input to the input terminal D2 is Q2 while Vcon2 is high potential.
Is output as Vcon2 is always low potential L while Vcon2 is low potential.
Is output as Q2. These outputs Q1 and Q2 are N
When input to the OR circuit 3, a 2f (bps) multiplexed signal sequence is obtained as the Q output of the NOR circuit 3.

In this embodiment, the phase margin of the circuit is 90 °.
Becomes That is, in the timing diagram shown in FIG. 5, with respect to Vcon1 and Vcon2, input terminals D1 and D
The circuit operation is possible even if the respective phases of the signals input to 2 shift within a range of ± 90 °.

Next, FIG. 2 is a circuit diagram showing a second embodiment. The signal multiplexing circuit shown in FIG. 2 has one second
Signal control circuit 4 configured only by the partial circuit of FIG. 5, a signal control circuit 5 having the same configuration as the signal control circuit 4, and an OR circuit 6 to which outputs (Q1, Q2) of the signal control circuits 4 and 5 are input.
Consists of.

In the circuit of FIG. 2, input terminals D1 and D2
When a signal sequence of f (bps) to be multiplexed is input to Vcon1, the signal control circuit 4 outputs the value input to the input terminal D1 as Q1 while Vcon1 is at a high potential.
Is low, the low potential L is always output as Q1. On the other hand, in the signal control circuit 5, while Vcon2 is high potential,
The value input to the input terminal D2 is output as Q2, and V
While con2 is at a low potential, the low potential L is always output as Q2. When these outputs Q1 and Q2 are input to the OR circuit 6, a 2f (bps) multiplexed signal sequence is obtained as the Q output of the OR circuit 6.

In this embodiment, the phase margin of the circuit is 90 °.
Becomes That is, in the timing diagram shown in FIG. 6, the input terminals D1 and D1 are connected to Vcon1 and Vcon2.
The circuit operation is possible even if the respective phases of the signals input to 2 shift within a range of ± 90 °.

Next, FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The signal multiplexing circuit shown in FIG.
Signal control circuit 1 including only the first partial circuits
And a signal control circuit 7 in which the first partial circuit and the second partial circuit are respectively used, and the output terminal of the first partial circuit is connected to the input terminal of the second partial circuit, The control circuit 1 and the OR circuit 3 to which the outputs (Q1, Q2) of the signal control circuit 7 are input.

When a signal sequence of f (bps) to be multiplexed is input to the input terminals D1 and D2, the signal control circuit 1
Then, an inverted signal of the value input to the input terminal D1 is output as Q1 while Vcon1 is at a high potential, and a low potential L is always output as Q1 while Vcon1 is at a low potential. On the other hand, in the signal control circuit 7, while Vcon1 is at a high potential, the inverted signal of the value input to the input terminal D2 is input to the second partial circuit to which Vcon2 is applied to the power supply terminal. While Vcon2 is at a high potential, its input (that is, an inverted signal of the value input to the input terminal D2) is output as Q2, and while Vcon2 is at a low potential, the low potential L is always output as Q2. . When the outputs Q1 and Q2 are input to the NOR circuit 3, N
As the output of the OR circuit 3, a 2f (bps) multiplexed signal sequence is obtained.

In this embodiment, the phase margin of the circuit is 180
It becomes °. That is, in the timing diagram shown in FIG. 7, the circuit operation is possible even if the respective phases of the signals input to the input terminals D1 and D2 deviate from Vcon1 by ± 180 °.

Next, FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. The signal multiplexing circuit shown in FIG.
Signal control circuit 4 including only the second partial circuits
And a signal control circuit 8 in which the other input terminal is connected to one output terminal by using two second partial circuits, and the output of the signal control circuit 4 and the signal control circuit 8 (Q1, Q2) Is input to the OR circuit 6.

In the circuit of FIG. 4, input terminals D1 and D2
When a signal sequence of f (bps) to be multiplexed is input to Vcon1, the signal control circuit 4 outputs the value input to the input terminal D1 as Q1 while Vcon1 is at a high potential.
Is low, the low potential L is always output as Q1. On the other hand, in the signal control circuit 8, while Vcon1 is at a high potential, the value input to the input terminal D2 is input to the second partial circuit to which Vcon2 is applied to the power supply terminal. And while Vcon2 is high potential, its input (that is, the value input to D2)
Is output as Q2, and the low potential L is always output as Q2 while Vcon2 is low potential. Their outputs Q1 and Q
When 2 is input to the OR circuit 6, a 2f (bps) multiplexed signal sequence is obtained as the output of the OR circuit 6.

In the embodiment of FIG. 4, the circuit phase margin is 1
It becomes 80 °. That is, in the timing diagram shown in FIG. 8, the circuit operation is possible even if the respective phases of the signals input to the input terminals D1 and D2 deviate from Vcon1 within a range of ± 180 °.

(2) When Four Signal Sequences are Multiplexed Next, an embodiment of the present invention when four signal sequences are multiplexed will be described. In this embodiment, four signal sequences of f (bps) are multiplexed to obtain one signal sequence of 4f (bps). In this embodiment, four signals whose frequencies are f and whose phases are shifted from each other by ¼ cycle are required. Therefore, the above four signals are generated from the clock signal of frequency 2f (Hz) by using the waveform generating circuit.

FIG. 9 is a block diagram showing an embodiment in which four signal trains are multiplexed. An example of the waveform generating circuit 50 shown in FIG. 9 is shown in FIG. 10, and an example of the signal multiplexing circuit 51 is shown in FIGS.

In FIG. 9, the waveform generating circuit 50 is composed of an even number of partial circuits and at least one inverting element circuit, and has three power supply terminals (Vck1, Vck2, Vdd),
This is a circuit capable of obtaining a plurality of outputs (Vcon1 to Vcon4). Of the power supply terminals, the positive and negative phases of the clock signal are applied to Vck1 and Vck2, respectively, and the DC voltage is applied to Vdd.

The signal multiplexing circuits 51 are all the first
Of four signal control circuits each of which is composed of the partial circuit of FIG.
Circuit or NOR circuit) and four signal string input terminals (D1 to D4) and four power supply terminals (Vcon1 to Vco).
n4) and one output terminal (Q). Outputs from the waveform generating circuit 50 are applied to the four power supply terminals, respectively.

Here, in the first partial circuit, the emitter electrode of the first negative differential resistance element is grounded, the collector electrode of the second negative differential resistance element is connected to the power supply terminal, and the first negative circuit is connected. The collector electrode of the negative differential resistance element and the emitter electrode of the second negative differential resistance element are connected, and the drain electrode and the source electrode of the field effect transistor are respectively connected to the collector electrode and the emitter electrode of the first negative differential resistance element. It is a circuit that is connected and uses the gate potential of the field effect transistor as an input and the drain potential as an output, which is the same circuit as the first partial circuit shown in FIG.

In the second partial circuit, the emitter electrode of the first negative differential resistance element is grounded, the collector electrode of the second negative differential resistance element is connected to the power supply terminal, and the first negative resistance element is connected. The collector electrode of the differential resistance element and the emitter electrode of the second negative differential resistance element are connected, and the drain electrode and the source electrode of the field effect transistor are connected to the collector electrode and the emitter electrode of the second negative differential resistance element, respectively. However, the gate potential of the field effect transistor is an input circuit and the source potential is an output circuit, which is the same circuit as the second partial circuit shown in FIG.

The waveform generating circuit 50 shown in FIG. 10 will be described below. This waveform generating circuit includes one first partial circuit 9 and three second partial circuits 10, 11, 12 and 1
Inversion element circuits (circuits that invert the input signal and output it)
13 is a circuit in which the output terminal and the input terminal are connected in the order of 9 → 10 → 11 → 12 → 13, and the output terminal of the inverting element circuit 13 and the input terminal of the first partial circuit 9 are connected. Then, Vck1 is applied to the power supply terminals of the odd-numbered partial circuits (9 and 11) and the even-numbered partial circuits (10 and 1).
Vck2 is applied to the power supply terminal of 2), and the inverting element circuit 1
A DC voltage Vdd is applied to the power supply terminal of No. 3.

The outputs of this waveform generating circuit are obtained as Q1, Q2, Q3, and Q4 from the output terminals of the first partial circuit 9 and the second partial circuits 10, 11, and 12, respectively. That is, as many outputs as the number of partial circuits can be obtained. Vdd
When a direct voltage and a positive phase and a negative phase of a 2 f (Hz) clock signal are applied to Vck1 and Vck2, respectively, a signal waveform for operating the signal multiplexing circuit (frequency is f, phase is 1/4 cycle sequentially) The signals which are shifted from each other are obtained from Q1 to Q4. The timing diagram of this waveform generator is shown in Figure 14.
Shown in.

In the circuit of FIG. 10, the frequency is f
10 is a circuit for generating four signals whose phases are sequentially shifted by 1/4 cycle. However, in the case of generating three signals whose frequency is f and whose phases are sequentially shifted by 1/3 cycle, FIG. In the same manner as above, by using the six partial circuits and connecting the odd-numbered ones to Vck1 and the odd-numbered ones to Vck2, six signals Q1 to Q6 are created, and the two adjacent signals are generated.
By giving each one to the OR circuits (three in total required) to obtain the logical sum, three signals whose phases are sequentially shifted by ⅓ cycle are obtained as the outputs of the three OR circuits. In this case, Vck1 and Vck2 are 3
The positive and negative phases of the clock signal of f (Hz) are used.

Next, FIG. 11 is a circuit diagram showing a first embodiment of the signal multiplexing circuit 51. The signal multiplexing circuit shown in FIG. 11 is composed of four signal control circuits 18, 19, 20, and 21 which are composed of only the first partial circuit, and a NOR circuit 22 to which their outputs are input.

In the circuit of FIG. 11, the signal control circuit 1
8, 19, 20, 21 are SC1, SC2, SC
3, SC4, x is a number from 1 to 4, each signal control circuit is represented by SCx, and similarly, when each power supply is represented by Vconx, the input is represented by Dx, and the output is represented by Qx, they are multiplexed to the input terminals D1 to D4. When the signal sequence of f (bps) to be attempted is input, in the control signal circuit SCx, while Vconx is at a high potential,
The inverted signal of the value input to Dx is output as Qx,
While Vconx is at a low potential, the low potential L is always output as Qx. When the outputs (Q1 to Q4: see FIG. 14) of the waveform generating circuit 50 shown in FIG. 10 are used as Vcon1 to Vcon4, the NOR circuit 2 to which Q1 to Q4 are input is input.
As the output of 2, a 4 f (bps) multiplexed signal sequence is obtained.

In this embodiment, the phase margin of the circuit is 45 °.
Becomes That is, in the timing diagram shown in FIG. 15, for Vcon1 to Vcon4, the input terminal D1
Even if the respective phases of the signals input to D4 deviate within a range of ± 45 °, the circuit operation is possible.

Next, FIG. 12 is a circuit diagram showing a second embodiment of the signal multiplexing circuit 51. The signal multiplexing circuit shown in FIG. 12 is composed of four signal control circuits 23, 24, 25, and 26, which are composed of only the second partial circuit, and an OR circuit 27 to which their outputs are input.

In the circuit of FIG. 12, the signal control circuit 2
3, 24, 25 and 26 are SC1, SC2 and SC respectively
3 and SC4, x is a number from 1 to 4, each signal control circuit is represented by SCx, and similarly, each power supply is represented by Vconx, the input is represented by Dx, and the output is represented by Qx. When a signal train of f (bps) to be input is input, SC
At x, the value input to Dx is output as Qx while Vconx is at a high potential, and the low potential L is always output as Qx while Vconx is at a low potential. Vcon1 to Vcon4
Output of the waveform generating circuit 50 shown in FIG. 10 (Q1
~ Q4: refer to FIG. 14), a multiplexed signal sequence of 4f (bps) is obtained as an output of the OR circuit 27 to which Q1 to Q4 are input.

In this embodiment, the phase margin of the circuit is 45 °.
Becomes That is, in the timing diagram shown in FIG. 16, the input terminal D1 is connected to Vcon1 to Vcon4.
Even if the respective phases of the signals input to D4 deviate within a range of ± 45 °, the circuit operation is possible.

Next, FIG. 13 is a circuit diagram showing a third embodiment of the signal multiplexing circuit 51. The signal multiplexing circuit shown in FIG. 13 is composed of a signal control circuit 28 including one second partial circuit and two second partial circuits, and one output terminal and the other input terminal are connected to each other. A signal control circuit 29 having the same configuration, a signal control circuit 30 having the same configuration as the signal control circuit 29, and an input terminal of the second partial circuit further connected to the output terminal of the circuit, and the same signal control circuit 30 as the signal control circuit 30. A signal control circuit 31 having a configuration in which the input terminal of the second partial circuit is further connected to the output terminal of the configuration circuit, and an OR circuit 2 to which the outputs (Q1 to Q4) of these four signal control circuits are input
It consists of 7.

In the circuit shown in FIG. 13, the input terminal D1
When a signal string of f (bps) to be multiplexed is input to D4, the signal control circuit 28 outputs the value input to the input terminal D1 as Q1 while Vcon1 is at a high potential, and Vcon1 Is low, the low potential L is always output as Q1.

In the signal control circuit 29, the value input to the input terminal D2 is input to the second partial circuit to which Vcon2 is applied to the power supply terminal only while Vcon1 is at the high potential. The input (that is, the value input to D2) is output as Q2 while Vcon2 is at a high potential, and the low potential L is always output as Q2 while Vcon2 is at a low potential.

In the signal control circuit 30, the value input to the input terminal D3 is input to the second partial circuit to which Vcon2 is applied to the power supply terminal only while Vcon1 is at the high potential. Then V
Only while con2 is at a high potential, its input (that is, the value input to D3) is input to the second partial circuit in which Vcon3 is applied to the power supply terminal. While Vcon3 is at a high potential, the input value (that is, the value input to D3) is Q3.
Is output as Vcon3, and low potential L is constantly maintained while Vcon3 is low potential.
Is output as Q3.

In the signal control circuit 31, the value input to the input terminal D4 is input to the second partial circuit to which Vcon2 is applied to the power supply terminal only while Vcon1 is at the high potential. Then V
Only while con2 is at a high potential, its input (that is, the value input to D4) is input to the second partial circuit in which Vcon3 is applied to the power supply terminal. Furthermore, only while Vcon3 is at high potential,
The input value (that is, the value input to D4) is
Vcon4 is input to the second partial circuit applied to the power supply terminal. The input value (that is, the value input to D4) is output as Q4 while Vcon4 is at a high potential, and the low potential L is always output as Q4 while Vcon4 is at a low potential. From Vcon1 to Vcon4, the output of the waveform generating circuit 50 shown in FIG. 10 (Q1 to Q4: see FIG. 14)
Is used, a 4 f (bps) multiplexed signal sequence is obtained as the output of the OR circuit 27 to which Q1 to Q4 are input.

In this embodiment, the phase margin of the circuit is 18
It becomes 0 °. That is, in the timing diagram shown in FIG. 17, the input terminals D1 to D4 are input to Vcon1.
The circuit operation is possible even if the respective phases of the signals input to are shifted by ± 180 °.

The contents of each of the embodiments described so far are summarized as follows. That is, n of f (bps)
A signal multiplexing circuit that multiplexes each input signal sequence to obtain one nf (bps) signal sequence sends out n output signals whose frequency is f and whose phases are sequentially shifted by 1 / n cycle. A waveform generator circuit and n input signal trains of n input signal trains, each of which inputs one input signal train to its input terminal and one of the output signals of the waveform generator circuit to its power supply terminal. Signal control circuit and an OR circuit that receives the output of each signal control circuit as an input and outputs one output. 1 to 4 are examples when n = 2, and FIGS. 11 to 13 are examples when n = 4. Further, FIG. 10 shows an example of the waveform generating circuit when n = 4.

Further, as shown in each of the above-described embodiments, the signal control circuit includes only one or a plurality of first partial circuits, only one or a plurality of second partial circuits, and one. Alternatively, it can be configured by a combination of a plurality of first and second partial circuits, and the output terminal of each partial circuit is sequentially connected to the input terminal of the next partial circuit except the first and last stages. It is what

Further, the waveform generating circuit has an even number of only the first partial circuit, only the second partial circuit, or the first and second partial circuits.
Of the partial circuit and an inverting element circuit for inverting the signal, the output terminal of each partial circuit is connected in order to the input terminal of the next partial circuit except the first stage and the final stage,
Moreover, the power supply terminal of the odd-numbered partial circuit is connected to the first power supply, the power supply terminal of the even-numbered partial circuit is connected to the second power supply, and the output of the final-stage partial circuit is output. The terminal is connected to the input terminal of the partial circuit of the first stage through the inverting element circuit, and has a waveform output terminal for each output terminal of each partial circuit. In order to output an odd number of signals, a partial circuit having twice the number of output signals is used, and two adjacent two of the outputs of each partial circuit are given to the OR circuit to obtain the logical sum. Thus, the required number of output signals can be obtained. However, the phases of the first power supply and the second power supply are ½ of each other.
The signals are out of cycle and, for example, a signal obtained by inverting the first power supply becomes the second power supply. A DC power source is connected to the inverting element circuit.

When the signal sequence of f (bps) is multiplexed, the clock signals applied to the first power source and the second power source are the frequency f and the signal sequence of 4 signals when the two signal sequences are multiplexed. Is 2f when 3 is multiplexed, and 3f when 3 signal sequences are multiplexed. Generally, when n signal sequences are multiplexed, (n / 2) f, n when n is an even number. If n is an odd number, it becomes nf.

The OR circuit is NOR when the number of the first partial circuits included in one signal control circuit is odd.
In the case of a circuit, an even number (including the case of 0, that is, only the second partial circuit), an OR circuit is used. As an example of the former,
For example, FIGS. 1 and 3 correspond, and examples of the latter correspond to FIGS. 2, 4, 12, and 13.

Further, in each of the above embodiments, the case where the field effect transistor is used has been shown, but the same effect can be obtained even if the partial circuit is configured by replacing the field effect transistor with a bipolar transistor. That is, the base electrode, the emitter electrode, and the collector electrode of the bipolar transistor may be connected instead of the gate electrode, the source electrode, and the drain electrode of the field effect transistor.

As the negative differential resistance element, for example, a resonant tunnel diode or an Esaki diode can be used.

[0068]

As described above, in the present invention, the functionality of the negative differential resistance element is utilized to obtain the output signal suitable for the control of the signal multiplexing circuit from the clock signal, and the control signal or the external signal. A signal multiplexing circuit that operates using a clock can be realized with a smaller number of elements and a simple circuit configuration as compared with the related art. Therefore, it is possible to obtain the effect that the phase margin of the circuit can be expanded, the speed can be increased, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a signal multiplexing circuit that multiplexes two signal strings.

FIG. 2 is a circuit diagram showing a second embodiment of a signal multiplexing circuit that multiplexes two signal strings.

FIG. 3 is a circuit diagram showing a third embodiment of a signal multiplexing circuit that multiplexes two signal strings.

FIG. 4 is a circuit diagram showing a fourth embodiment of a signal multiplexing circuit that multiplexes two signal strings.

5 is a timing diagram of the first embodiment shown in FIG.

FIG. 6 is a timing diagram in the second embodiment shown in FIG.

7 is a timing diagram according to the third embodiment shown in FIG.

FIG. 8 is a timing diagram according to the fourth embodiment shown in FIG.

FIG. 9 is a block diagram showing an overall configuration of a signal multiplexing circuit that multiplexes four signal strings.

10 is a circuit diagram showing an embodiment of the waveform generating circuit shown in FIG.

11 is a circuit diagram showing a first embodiment of the signal multiplexing circuit shown in FIG.

12 is a circuit diagram showing a second embodiment of the signal multiplexing circuit shown in FIG.

FIG. 13 is a circuit diagram showing a third embodiment of the signal multiplexing circuit shown in FIG.

FIG. 14 is a timing diagram in the embodiment of the waveform generating circuit shown in FIG.

FIG. 15 is a timing diagram in the first embodiment of the signal multiplexing circuit shown in FIG.

16 is a timing diagram of the second embodiment of the signal multiplexing circuit shown in FIG.

17 is a timing diagram of the third embodiment of the signal multiplexing circuit shown in FIG.

FIG. 18 is a block diagram of an example of a conventional signal multiplexing circuit.

FIG. 19 is a timing diagram of the signal multiplexing circuit shown in FIG.

20 is a circuit diagram of an example of the tri-stage flip-flop circuit shown in FIG.

[Explanation of Codes] 1, 2 ... Signal control circuit 3 composed of one first partial circuit ... NOR circuit 4, 5 ... Signal control circuit 6 composed of one second partial circuit ... OR circuit 7 ... a signal control circuit 8 including one first partial circuit and one second partial circuit ... a signal control circuit 9 including two second partial circuits ... first partial circuits 10 and 11 , 12 ... Second partial circuit 13 ... Inversion element circuits 18, 19, 20, 21 ... Signal control circuit 22 composed of one first partial circuit ... NOR circuit 23, 24, 25, 26 ... 1 OR circuit 28 ... Signal control circuit 29 composed of one second partial circuit ... Signal control circuit 30 composed of two second partial circuits ... 3 Signal control circuit 31 composed of four second partial circuits ... A signal composed of four second partial circuits No. control circuit 50 ... Waveform generation circuit 51 ... Signal multiplexing circuit NR1, NR2 ... Negative differential resistance element FET1, FET2 ... Field effect transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-132811 (JP, A) JP-A-8-79022 (JP, A) JP-A-9-162705 (JP, A) JP-A-9- 326677 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 17/00 H03K 19/00 H03K 5/00 H03K 3/00

Claims (10)

(57) [Claims] 1. A few double the includes at least one of the first partial circuit and the second partial circuit, the input of the next partial circuit output terminal of each of the partial circuits with the exception of the first stage and the last stage A signal control circuit sequentially connected to the terminals,
The partial circuit outputs a low potential regardless of the potential of the input terminal when the low potential is applied to the power supply terminal, and is applied to the input terminal when the potential of the power supply terminal changes from the low potential to the high potential. After detecting and holding a potential that is the reverse of the potential, once the potential of the power supply terminal becomes high, it is first retained regardless of the potential of the input terminal until the potential of the power supply terminal becomes low again. The second partial circuit outputs a low potential regardless of the potential of the input terminal when the low potential is applied to the power source terminal, and the potential of the power source terminal is higher than the low potential. The potential applied to the input terminal at the time of changing to the potential is detected and held, and once the potential of the power supply terminal becomes high potential, until the potential of the power supply terminal becomes low potential again,
A signal control circuit, which outputs the first held potential regardless of the potential of the input terminal. 2. A singular or plural first partial circuit.
And at least one of the second partial circuit,
Except for the final stage, the output terminals of each partial circuit are
Signal control circuit that is sequentially connected to the input terminals of the
Therefore, in the first partial circuit, a low potential is applied to the power supply terminal.
Outputs a low potential regardless of the potential of the input terminal
When the potential of the power supply terminal changes from low potential to high potential
The potential opposite to the potential applied to the input terminal at
Hold and once the potential of the power supply terminal becomes high potential,
Until the potential of the power supply terminal becomes low potential, the potential of the input terminal
It outputs the first held potential regardless of
The second partial circuit is a state in which a low potential is applied to the power supply terminal.
In the state, the low potential is output regardless of the potential of the input terminal, and
Input terminal when the potential of the child changes from low potential to high potential
The potential applied to the child is detected and held, and once the power supply terminal
After the electric potential becomes high, the electric potential of the power supply terminal becomes low again.
Hold first regardless of the potential of the input terminal until
With a waveform generation circuit that uses a signal control circuit that outputs
Therefore, an even number of at least one of the first partial circuit and the second partial circuit, an inverting element circuit that inverts a signal, and an OR circuit that is 1/2 of the number of the partial circuits are provided. Bei example, the first stage and with the exception of the last stage output terminal of each partial circuit is connected in order to the input terminal of the next partial circuits, and power supply terminals of the odd-numbered of said subcircuits first power supply Connected to the second power source, the output terminal of the partial circuit of the final stage is input to the partial circuit of the first stage through the inverting element circuit. Two adjacent output terminals of each of the partial circuits are connected to the logical sum circuit, respectively, and the output of each of the partial circuit is 1 / n of the number of the partial circuits.
A waveform generation circuit having two waveform output terminals. 3. A singular or plural first partial circuit.
And at least one of the second partial circuit,
Except for the final stage, the output terminals of each partial circuit are
Signal control circuit that is sequentially connected to the input terminals of the
Therefore, in the first partial circuit, a low potential is applied to the power supply terminal.
Outputs a low potential regardless of the potential of the input terminal
When the potential of the power supply terminal changes from low potential to high potential
The potential opposite to the potential applied to the input terminal at
Hold and once the potential of the power supply terminal becomes high potential,
Until the potential of the power supply terminal becomes low potential, the potential of the input terminal
It outputs the first held potential regardless of
The second partial circuit is a state in which a low potential is applied to the power supply terminal.
In the state, the low potential is output regardless of the potential of the input terminal, and
Input terminal when the potential of the child changes from low potential to high potential
The potential applied to the child is detected and held, and once the power supply terminal
After the electric potential becomes high, the electric potential of the power supply terminal becomes low again.
Hold first regardless of the potential of the input terminal until
Signal multiplexing circuit using signal control circuit that outputs different potential
A is, the plurality, and the signal control circuit, OR circuit or NO
E Bei and R circuits, and the respective input terminals of the respective signal control circuit, an input terminal of each signal sequence to be multiplexed, each of the output terminals of the respective signal control circuit the OR circuit or N
A signal multiplexing circuit, which is connected to an input terminal of an OR circuit, and uses the output terminal of the OR circuit or NOR circuit as an output terminal of a multiplexed signal sequence. 4. A single partial circuit or a plurality of first partial circuits.
And at least one of the second partial circuit,
Except for the final stage, the output terminals of each partial circuit are
Signal control circuit that is sequentially connected to the input terminals of the
Therefore, in the first partial circuit, a low potential is applied to the power supply terminal.
Outputs a low potential regardless of the potential of the input terminal
When the potential of the power supply terminal changes from low potential to high potential
The potential opposite to the potential applied to the input terminal at
Hold and once the potential of the power supply terminal becomes high potential,
Until the potential of the power supply terminal becomes low potential, the potential of the input terminal
It outputs the first held potential regardless of
The second partial circuit is a state in which a low potential is applied to the power supply terminal.
In the state, the low potential is output regardless of the potential of the input terminal, and
Input terminal when the potential of the child changes from low potential to high potential
The potential applied to the child is detected and held, and once the power supply terminal
After the electric potential becomes high, the electric potential of the power supply terminal becomes low again.
Hold first regardless of the potential of the input terminal until
Signal multiplexing circuit using signal control circuit that outputs different potential
A is, the plurality, and the signal control circuit, OR circuit or NO
And the R circuit, e Bei and a waveform generating circuit having the same number of waveform output terminal and the signal control circuit, an input terminal of each signal train the attempts to multiplex the input terminals of the signal control circuit, wherein each of Each output terminal of the signal control circuit is connected to the input terminal of the OR circuit or NOR circuit, and each waveform output terminal of the waveform generation circuit is connected to each power supply terminal of the signal control circuit, and the OR circuit or NOR is connected. A signal multiplexing circuit, wherein an output terminal of the circuit is used as an output terminal of a multiplexed signal. 5. A singular or plural first partial circuit.
And at least one of the second partial circuit,
Except for the final stage, the output terminals of each partial circuit are
Signal control circuit that is sequentially connected to the input terminals of the
Therefore, in the first partial circuit, a low potential is applied to the power supply terminal.
Outputs a low potential regardless of the potential of the input terminal
When the potential of the power supply terminal changes from low potential to high potential
The potential opposite to the potential applied to the input terminal at
Hold and once the potential of the power supply terminal becomes high potential,
Until the potential of the power supply terminal becomes low potential, the potential of the input terminal
It outputs the first held potential regardless of
The second partial circuit is a state in which a low potential is applied to the power supply terminal.
In the state, the low potential is output regardless of the potential of the input terminal, and
Input terminal when the potential of the child changes from low potential to high potential
The potential applied to the child is detected and held, and once the power supply terminal
After the electric potential becomes high, the electric potential of the power supply terminal becomes low again.
Hold first regardless of the potential of the input terminal until
Signal multiplexing circuit using signal control circuit that outputs different potential
A is, have a structure according to claim 2, a waveform generation circuit for transmitting the output signal of the phase sequence 1 / n cycle shifted by n frequencies f, has a configuration of the signal control circuit , N input signal trains, one input signal train is input to the input terminal, and one of the output signals of the waveform generating circuit is input to the power supply terminal. And an OR circuit that receives the output of each of the signal control circuits as an input and sends out one output, and multiplexes each of n input signal sequences of f bits per second to obtain one nf bit per second signal sequence. A signal multiplexing circuit characterized by obtaining. Signal control circuit according to any one of claims 6] claims 1 to 5, in the waveform generating circuit or the signal multiplexing circuit, the first subcircuit of the field effect transistor
An input terminal is connected to the gate electrode, an emitter electrode of the first negative differential resistance element is connected to a source electrode of the field effect transistor and a ground terminal, and a collector electrode of the first negative differential resistance element is 2 is a circuit in which the emitter electrode of the negative differential resistance element, the drain electrode of the field effect transistor, and the output terminal are connected, and the collector electrode of the second negative differential resistance element is connected to the power supply terminal. Characteristic signal control circuit, waveform generation circuit or signal multiplexing circuit. Signal control circuit according to any one of claims 7] claims 1 to 5, in the waveform generating circuit or the signal multiplexing circuit, the second partial circuit are field effect transistors
An input terminal is connected to the gate electrode, an emitter electrode of the first negative differential resistance element is connected to a ground terminal, and a collector electrode of the first negative differential resistance element is connected to the source electrode of the field effect transistor and a second electrode. A circuit in which the emitter electrode of the negative differential resistance element is connected to the output terminal, and the collector electrode of the second negative differential resistance element is connected to the drain electrode of the field effect transistor and the power supply terminal. A signal control circuit, a waveform generating circuit or a signal multiplexing circuit. 8. A signal control circuit, a waveform generating circuit or a signal multiplexing circuit according to claim 6 or 7 ,
A signal control circuit, a waveform generating circuit, or a signal multiplexing circuit, wherein a resonant tunneling diode is used as the negative differential resistance element. 9. A signal control circuit, a waveform generating circuit or a signal multiplexing circuit according to claim 6 or 7 ,
A signal control circuit, a waveform generating circuit or a signal multiplexing circuit, characterized in that an Esaki diode is used as the negative differential resistance element. 10. The signal control circuit, the waveform generating circuit or the signal multiplexing circuit according to claim 6 or 7 , wherein a bipolar transistor is used instead of the field effect transistor, and a gate electrode, a source electrode and a drain electrode are provided. , A signal control circuit, a waveform generating circuit or a signal multiplexing circuit, which are respectively a base electrode, an emitter electrode and a collector electrode.