JP3528115B2 - Motion prediction vector detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector predictor detection circuit and, more particularly, to a motion vector predictor detection circuit for predicting motion of image data with half pixel accuracy.

[0002]

2. Description of the Related Art In an image coding method, when a target image information is coded, a motion vector of the image is obtained in advance and the data amount of the image information is coded based on the motion vector. Technologies that improve the transmission efficiency and compression efficiency of image data are used.

FIG. 2 (a) is a diagram for explaining the concept of such a motion vector predictor detection method, in which one frame of image data F is divided into a plurality of blocks. Then, in the current frame, a block at an arbitrary position exists at the same position as the immediately preceding frame (the frame immediately before) or in the vicinity thereof, and therefore, with respect to a certain region (the search window SW) of the immediately preceding frame. Then, it is searched where this block (referred to as the reference block RB) was located, and the most approximate part (block RB indicated by a broken line).
It is expressed as a vector A.

As the evaluation value of the vector A, the reference block RB and the most approximate block R in the search window SW.
The sum of the differences between the corresponding pixel data with B'is also calculated,
This evaluation value is also output together with the vector A.

In such a motion vector predictor detection circuit,
Motion estimation is performed from the search window SW and the reference block RB, which are the search area of one pixel accuracy, and the minimum vector and evaluation value are obtained from the comparison result by the mean absolute value error (MAE) estimation method or the like. Therefore, even if the reference block RB moves with half-pixel accuracy with respect to the search window SW, the vector can be detected only in units of one pixel.

Therefore, an example of performing motion vector detection processing with half-pixel precision is disclosed in Japanese Patent Laid-Open No. 5-336514. In this example, half-pixel precision motion vector detection processing is executed using a single clock without increasing the number of frame memories.

That is, a vector with one pixel accuracy is obtained,
Perform interpolation processing from surrounding pixels based on this vector, search a vector with half-pixel accuracy from the half-pixel area,
A combination with a one-pixel precision vector is output as a half-pixel precision motion vector. When performing the interpolation process, the pixel data is divided in parallel to shorten the time required for the interpolation, and the circuit is configured using a single clock system.

[0008]

As described above, Japanese Patent Laid-Open No.
According to the technique of Japanese Patent No. 336514, a vector with 1-pixel precision is obtained, interpolation pixels are obtained from original pixels only in a necessary range centered on the pixel indicated by this motion vector, and a vector with 1 / 2-pixel precision is obtained from the obtained interpolation pixels. Search for 1
The motion vector combined with the pixel precision vector is defined as the 1/2 pixel precision motion vector.

For this reason, a multiport VRAM (video random access memory) for storing pixel data of a certain area for generating an interpolation pixel, a parallel circuit for outputting the pixel data to the multiport VRAM as a peripheral circuit thereof, and 1 An interpolation address generation circuit or the like for reading the area required for searching a vector with a / 2 pixel precision from the multiport VRAM is required.

An object of the present invention is to make it possible to detect a vector with half-pixel accuracy by using a search window, which is a search area for detecting a motion vector, as an area with half-pixel accuracy in advance, thereby simplifying the circuit configuration. A motion prediction vector detection circuit is provided.

[0011]

According to the present invention, image data of one frame is divided into a plurality of blocks, and a predetermined reference block of the current frame is located with respect to a search window which is a predetermined area of the immediately preceding frame. The relative positional relationship between the most approximate block and the reference block is sequentially collated for each corresponding pixel, and the sum of the difference values for each corresponding pixel together with this vector is evaluated as the evaluation value of the vector. A motion vector predictor detection circuit for outputting 1-pixel precision data in the search window, and average data of the pixel data adjacent to each 1-pixel pixel and the 1-pixel data. Half-pixel precision data generation means for calculating and generating half-pixel precision data, one-pixel precision data of the search window and the reference block 1-pixel precision vector detection means for generating a 1-pixel precision vector and its evaluation value by collating the data of the search window, the half-pixel precision data of the search window by the half-pixel precision data generation means, and the reference. The half-pixel precision vector detection means for generating a half-pixel precision vector and its evaluation value by comparing with the block data and the one-pixel precision and half-pixel precision vector detection means are compared and the comparison is made. Selecting means for selectively deriving the one-pixel precision vector and the half-pixel precision vector according to the result, and the one-pixel precision vector for the reference block.
Cuttle detection and half-pixel precision vector detection are performed in parallel at the same time.
Motion prediction vector detection circuit, characterized in that management is obtained.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The operation of the present invention will be described. 1
In addition to the pixel-precision search window data, half-pixel-precision data in which one pixel of this search window data is shifted by half a pixel in each of the horizontal, vertical, and diagonal directions is interpolated and generated. In this case, as half-pixel shifted data, average value data of adjacent data around each one pixel and the one-pixel data is obtained, and this is set as half-pixel precision data.

Then, a block matching process (determination process as to whether or not the block is the closest block) between the search window data having the half-pixel precision and the data of the input reference block, and the conventional search window data having the one-pixel precision are performed. Both the block matching process with the input reference block data is performed, and the vector having the smallest evaluation value by these block matching processes is set as the optimum vector.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, the data S1 of the reference block RB of the current frame is one input to each of the vector detection circuits 1 to 4. Data S in the search window S2 of the immediately preceding frame
2 is the other input of the vector detection circuit 1 and is also supplied to the half pixel data generation circuit 5.

It is assumed that both the reference block data S1 and the search window data S2 are data of one pixel precision as in the conventional case. Therefore, the vector detection circuit 1 performs a block matching process with one pixel accuracy and outputs the minimum vector V0 between both input data S1 and S2 and its evaluation value H0.

The half-pixel data generation circuit 5 uses the search window data S2 of 1-pixel precision to the data S of half-pixel precision.
3, S4, S5 are generated, and for example, a pixel S3 (x mark) vertically shifted by one pixel and a pixel shifted horizontally by half pixel with respect to each pixel indicated by circled numbers in FIG. S4 (marked by Δ) and pixel S5 that is shifted by half a pixel in the diagonal direction
Half-pixel interpolation data corresponding to each (□) is generated.

Each of the vector detection circuits 2 to 4 performs block matching processing between each of the half-pixel interpolation data S3 (x), S4 (Δ), S5 (□) and the reference block data S1 to obtain the minimum value. Vectors V1 to V3 and each evaluation value H1
To H3 are output respectively.

The comparator 6 compares these evaluation values H0 to H3 and generates a selector control signal C so that the selector 7 selects the minimum vector corresponding to the smallest evaluation value. As a result, the optimum motion prediction vector VOUT with half-pixel precision is derived from the output of the selector 7.

The half pixel data generation circuit 5 will be described in detail below. In this case, the size of each block during the block matching processing in the vector detection circuits 1 to 4 is generally m × n pixels (both m and n are integers of 2 or more).
However, here, for simplification, as shown in FIG. 2B, it is assumed that the block matching process is performed on a block-by-block basis with 3 × 3 pixels as one block.

Therefore, the reference block RB has 3 × 3 pixels, and the search window SW to be compared is also divided into blocks of 3 × 3 pixels, and block matching of these two blocks is performed.

In this block matching, the corresponding pixels between blocks are compared with each other. The order of comparison between the corresponding pixels is as shown in FIG. 2 (b).
There are two methods, vertical scanning and horizontal scanning.

The half-pixel data generation circuit 5 has a different structure depending on these two scanning methods. First, the case of vertical scanning in FIG. 2B will be described.

Referring to FIG. 3, the circled numbers indicate the order of 1-pixel data of each block. To generate the data of the X mark which is shifted by half a pixel in the vertical direction, for example, the pixel between and The average value of the data is calculated, and this is used as half-pixel interpolation data (marked with x). Also, regarding the pixel data at the bottom of the block, the tenth pixel immediately below the block is displayed.
The average value with the 0th pixel data needs to be the half-pixel interpolation data.

Therefore, in order to obtain the above-mentioned half-pixel interpolated data of X, it is necessary to control the timing phase of each pixel as shown in FIG. In FIG. 4, the top row shows the pixel order of the input search window data S2, and the second row stores this search window data in a FIFO memory and outputs it after performing phase matching with the top row data. The subsequent pixel order is shown, and the third row shows the pixel order after the output of this FIFO memory is delayed by one pixel.

It can be seen that if the data of two pixels indicated by the upper left black dot in each pixel is added to obtain the average value, the intended half-pixel interpolated data of X is generated.

Therefore, an example of the half-pixel data generating circuit 5 in the case of vertical scanning is obtained as shown in FIG. In FIG. 5, the search window data S2 becomes one input of the selector 52, and at the same time, the FIFO (First in FIR)
(st out) is also input to the memory 51. This FIF
The output S10 of the O memory 51 is the other input of the selector 52.

The output S10 of this FIFO memory 51 is 1
It is one input of the adder 54 via the pixel delay device 53, and the output of the selector 52 is applied to the other input of this adder 54. This adder 54 adds the two inputs and then outputs by ignoring the LSB (least significant bit) (shifts the addition data by 1 bit to the LSB side) to halve the addition result. Yes, output the average data of both inputs.

The same applies to all the other adder circuits, and the average data of two inputs is output.

The timing control circuit 59 receives the clock CLK synchronized with each pixel data of the input data as an input, and outputs FI.
The write / read (W / R) timing of the FO memory 51 is generated, and the selector control signal S of the selector 52 is generated.
Also produces twelve.

The average value S3 output from the adder 54 becomes half-pixel interpolation data in the vertical direction (marked with X), and the timing chart of FIG. 4 shows the relationship between the pixel number of each part and the selector control signal S12 of the selector 52. ing.

Horizontal half-pixel interpolation data (marked by Δ) is
The output S11 of the one-pixel delay element S3 and the data obtained by delaying the output S11 by three pixels by the three-pixel delay element (m = 3) 57 are added by the adder 58, so that, for example, a pixel The average value S4 will be calculated.

Half-pixel interpolation data (square mark) in the diagonal direction is
Here, if it is assumed that the average value of X marks adjacent to each other in the same row is calculated, the average value (×
Mark) and data delayed by 3 pixels by the 3 pixel delay element 55 are added by the adder 56 to obtain data S5.

By the half-pixel data generation circuit 5 shown in FIG. 5, the search window data S2 (vertical scan) with 1-pixel precision as shown in FIG. It will be obtained as interpolation data.

The above is an example in which the vertical scanning shown in FIG. 2B is performed during the block matching process.
In the case of the horizontal scan of FIG. 2B, the half pixel data generation circuit 5 has the circuit configuration shown in FIG.

In FIG. 6, search window data S
2 serves as one input of the selector 62 and also serves as an input of the FIFO memory 61, and the output of this memory 61 becomes the other input of the selector 62. The output of the selector 62 and the delay output of the one-pixel delay element 63 of the output of the memory 61 are added by the adder 64 to calculate the average value, and the pixel data S3 indicated by x is obtained.

This pixel data S3 becomes one input to each of the selector 67 and the adder 68, and also the FIFO memory 65.
The output of the memory 65 is the other input of the selector 67 via the one-pixel delay number 66. The output of the selector 67 becomes the other input of the adder 68, and the pixel data S5 marked with □ is obtained.

The output of the one-pixel delay element 63 becomes one input of the adder 72 and the selector 71, and the FIF
It also serves as one input of the O memory 69. This memory 69
Of the selector 71 is input to the other input of the selector 71 via the 1-pixel delay element 70. The output of the selector 71 is the adder 7
The other input becomes 2, and the pixel data S6 marked with Δ is obtained.

Assuming that the block structure is m × n pixels and the number of blocks in the horizontal direction is i, the FIFO memory has a capacity capable of storing search window data S2 for m × n × i pixels. .

[0040]

As described above, according to the present invention, half-pixel precision data is generated as search window data from one-pixel precision data, and both search window data having one-pixel precision and half-pixel precision are generated. Since the block matching with the reference block data is performed, the motion vector can be detected more accurately with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a block matching process.

FIG. 3 is a diagram illustrating a process of generating search window data with half-pixel accuracy.

FIG. 4 is a timing chart showing a phase between adjacent pixels for generating search window data with half-pixel accuracy.

5 is a diagram illustrating an example of the half-pixel data generation circuit in FIG.

FIG. 6 is a diagram showing another example of the half-pixel data generation circuit of FIG.

[Explanation of symbols]

1-4 vector generation circuit 5 Half pixel data generation circuit 6 comparator 7,52,62,67,71 Selector 51, 61, 65, 69 FIFO memory 53, 55, 57, 63, 66, 70 Delay element 54, 56, 58, 64, 68, 72 Adder 59 Timing control circuit

Claims (4)

(57) [Claims] 1. The image data of one frame is divided into a plurality of blocks, and where the predetermined reference block of the current frame is located with respect to the search window, which is the predetermined area of the immediately preceding frame, is sequentially determined for each corresponding pixel. Motion prediction vector detection in which the relative positional relationship between the block closest to the reference and the reference block is expressed as a vector, and the sum of the difference values for each corresponding pixel is output as the evaluation value of the vector together with this vector. A circuit, which calculates half-pixel precision data by calculating average data of data of pixels adjacent to each one pixel of the search window and one-pixel precision data of the search window. 1 pixel by comparing the 1-pixel precision data of the search window with the data of the reference block. 1-pixel precision vector detection means for generating a precision vector and its evaluation value, and half-pixel precision data by collating the half-pixel precision data of the search window by the half-pixel precision data generation means with the reference block data. Of the half-pixel precision vector detecting means for generating the vector and its evaluation value and the one-pixel precision and half-pixel precision vector detecting means are compared, and the one-pixel precision and half-pixel are calculated according to the comparison result. comprising selecting means for alternatively derive a vector accuracy, a, against the reference block
1-pixel precision vector detection and half-pixel precision vector detection
A motion vector predictor detection circuit characterized in that output and output are processed in parallel at the same time . 2. The interpolating means, data of one pixel accuracy of the search window, and respective average data of each pixel and at least one pixel shifted in the vertical direction and in the horizontal direction with respect to each one pixel as a reference. 2. The motion vector predictor detection circuit according to claim 1, further comprising means for calculating each of the values and outputting the data as the half-pixel precision data. 3. The half-pixel precision vector detection means collates each of the average data and the data of the reference block to generate a half-pixel precision vector and its evaluation value. The motion vector predictor detection circuit according to claim 2. 4. The motion prediction vector detection circuit according to claim 3, wherein the selection means is configured to output a vector corresponding to the smallest evaluation value among the evaluation values as an optimum vector.