JP3524545B2 - Manufacturing method of circuit component built-in module - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit component built-in module and a method for manufacturing the same, and more particularly, to a semiconductor chip built in an electrically insulating substrate to achieve a thin structure and to form a multi-stage laminated module for high-density mounting. And a method for manufacturing the same.

[0002]

2. Description of the Related Art As various electronic information devices have become higher in performance and smaller in size in response to the remarkable development of the information and communication industry in recent years, circuit components used in such electronic information devices have become higher in density and higher in function. In order to realize each of these characteristics, there is an increasing demand for ultra-thin modules of circuit components and electronic elements, that is, modules with built-in circuit components.

Since there is a limit to the technique of mounting the circuit component on the surface layer of the substrate in order to make the circuit component extremely thin, a recess is formed in the substrate and the semiconductor chip is arranged in the recessed portion to reduce the thickness of the substrate. There is proposed a technology for realizing high-density mounting of circuit components (Patent Documents 1 to 3 below). In this technique, after mounting an active component such as a semiconductor chip in the recess of the substrate, a resin is applied to the recess to seal the semiconductor chip and the connection between the substrate and the semiconductor chip in order to protect the semiconductor chip.

Further, there has been proposed a technique for realizing high-density mounting by increasing the number of circuit boards. The conventional method of forming a through-through-hole structure by drilling on a substrate (glass-epoxy substrate) in which glass fiber cloth is impregnated with epoxy resin has a limit to high density, and therefore LSI (large scale integrated circui
There was a problem that the wiring patterns between t) and parts were not connected in the shortest distance. However, in order to solve such a problem, an inner via hole connection technique has been proposed (Patent Documents 4 to 5 below). The inner via hole connection technique as described above can connect only a specific laminated layer and is excellent in mountability of a semiconductor chip.

Further, Japanese Patent Application Laid-Open Publication No. 2004-242242 proposes, as an example of a circuit component built-in module, a module having high heat dissipation performance in which semiconductor chips are built in a circuit board having high thermal conductivity, and the circuit boards are stacked in multiple stages. Has been done.

The following Non-Patent Document 7 has been proposed as another known example. An example thereof will be described with reference to FIGS. 12A and 12B. A glass-epoxy substrate 1002 (FIG. 12A) on which a flexible semiconductor chip 1001 having a thickness of 50 to 100 μm is mounted is stacked to form a multi-stage stacked memory package 1003 (FIG. 12B) for high density mounting. Figure 1
In 2A, 1004 is a protruding electrode of the semiconductor chip 1001, 1005 is a surface electrode of a glass-epoxy substrate 1002, 1006 is a sealing resin, 1007 is a glass-epoxy substrate, 1008 is a via, 1009 is a wiring, and 1010 is a recess space. .

[0007]

[Patent Document 1] Japanese Unexamined Patent Publication No. 5-259372

[Patent Document 2] Japanese Patent Laid-Open No. 11-103147

[Patent Document 3] Japanese Patent Laid-Open No. 11-163249

[Patent Document 4] JP-A-63-47991

[Patent Document 5] JP-A-6-268345

[Patent Document 6] Japanese Patent Laid-Open No. 11-220262

[0008]

[Patent Document 7] ICEP Proceeding Stacking Semiconduct
or Packages, 2001, P16-21

[0009]

However, the recessed space 1010 is provided in the circuit board, and the semiconductor chip 100 is provided therein.
In the technique of arranging No. 1, regardless of whether a ceramic substrate or a resin substrate is used, there is a problem that a large amount of cost is required for the step of processing the concave portion on the substrate and the production yield is reduced. In addition, in the technique of arranging the semiconductor chip on the glass-epoxy substrate by using the sealing resin, the through-hole plating via-hole connection technique is used, but since the material used for the substrate is usually resin such as glass-epoxy, the substrate itself. The thermal conductivity of the module was low and the heat dissipation performance of the module was insufficient, resulting in a loss of reliability.

Further, in a circuit component built-in module in which circuit boards are stacked in multiple stages, in the case where a plurality of semiconductor chips are stacked in the vertical direction, the thickness of the entire module becomes excessive, and high density packaging is limited. was there. SRAM (stati
(c random access memory), flash memory, and other types of memory semiconductor chips with different types of memory chips stacked in the vertical direction, the thickness of the semiconductor chips is constrained in order to reduce the thickness. The number of layers was 3 to 4 at most, and high density packaging was insufficient.

On the other hand, development of a technique for mounting a semiconductor chip on a substrate after polishing the semiconductor chip on a wafer is also active, but such a thin semiconductor chip has poor handleability and is mounted on the substrate. The production efficiency represented by sex was low.

Further, as shown in FIGS. 12A-B, a multi-stage laminated memory package 1 in which thin semiconductor chips are laminated
In 003, the thickness of the substrate 1002 is dominant, and it is difficult to provide a stack of, for example, about 8 stages within a specific module thickness range. In addition, in this multi-layer laminated module, a via formed by plating is generally used as an interlayer connection method, and a complicated process is required to enhance the adhesion between layers. Then, the semiconductor chip is mounted on the substrate 10.
It becomes difficult to mount the module in the No. 02, and a void is formed around the semiconductor chip, which may impair the reliability of the obtained module, for example, there is a risk of steam explosion in the reflow process during moisture absorption.

In such a thin multi-layer laminated module, in order to increase the strength of the substrate 1002, it is difficult to embed a semiconductor chip in the substrate 1002 when a glass-epoxy substrate is used, for example, as shown in FIG. , L (inductor), C (capacitor), R (resistor)
It becomes necessary to mount the chip components 1104 and the like on the outermost layer surface of the module, and there have been restrictions on the structural design of the circuit board including the optimum placement of the circuit components for the purpose of high-density mounting.

The present invention solves the above-mentioned problems in the prior art, and is a high-density mounted circuit component built-in module used in various electronic information devices that are thin and have high performance and size. And a method for manufacturing the same.

[0015]

In order to achieve the above object, a method for manufacturing a circuit component built-in module of the present invention comprises a first electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin, and A plurality of wiring patterns formed on at least the main surface of the electrically insulating substrate, a semiconductor chip built in the electrically insulating substrate and electrically connected to the wiring pattern, and the plurality of wiring patterns electrically Manufacture of a circuit component built-in module including an inner via formed so as to penetrate through the electrically insulating substrate
A method of forming a through hole in the electrically insulating substrate.
Prepare a plate-shaped body filled with thermosetting conductive material
Process and wiring pattern formed on the release carrier
The semiconductor chip is mounted on the non-wiring surface of the semiconductor chip.
And the wiring pattern of the release carrier.
On the surface where the turn is formed, the wiring pattern and the penetration
Make sure that the holes are filled with the conductive material so that they match.
By aligning and stacking the plate-shaped bodies and applying pressure
Embedding the semiconductor chip in the plate-like body, and
After that, by heating the mixture and the conductive
Step of curing the substance and peeling the release carrier
It is characterized by including a process .

[0016] In the method of manufacturing the circuit component built-in module of the present invention includes a first electrically insulating substrate made from a mixture comprising an inorganic filler and a thermosetting resin, it is formed on at least the main surface of the electrically insulating substrate Multiple wiring patterns,
A semiconductor chip built in the electrically insulating substrate and electrically connected to the wiring pattern, and an inner via formed through the electrically insulating substrate so as to electrically connect the plurality of wiring patterns. A method of manufacturing a circuit component built-in module, including: a step of forming a through hole in the electrically insulating substrate to prepare a plate-like body filled with a thermosetting conductive substance therein; and a wiring pattern Was formed
The semiconductor chip is mounted on the multilayer board, and
A step of grinding a non-wiring surface of a semiconductor chip;
The wiring pattern of the multilayer board on which chips are mounted and the
Make sure that the holes filled with the conductive material match.
By stacking the multi-layer substrate and the plate-shaped body and applying pressure,
And embedding the semiconductor chip in the plate-like body,
Then, the mixture and the conductive material are heated by heating.
The method is characterized by including a step of curing the volatile substance .

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION In a circuit component built-in module of the present invention, a semiconductor chip is mounted on a wiring pattern formed on a release carrier, and the semiconductor chip is embedded in an electrically insulating substrate to obtain the electrically insulating property. The characteristic is that the inner via formed through the substrate electrically connects the wiring pattern taken out from the surface of the semiconductor chip and the inner via. As a result, the module with built-in circuit components can be made thinner, and a high-performance and miniaturized multi-stage stacked module can be obtained.

In the method of the present invention, after mounting a semiconductor chip, the semiconductor chip is mounted in a range of 30 μm to 100 μm.
Grind to the following thickness. If the thickness of the above range,
It is suitable for obtaining a multi-layered module that is thin and compact. Further, even if the non-wiring surface of the semiconductor chip is ground to a thickness within the above range, there is no problem in performance.

If the thickness of the circuit component built-in module is 80 to 200 μm, it is suitable for thinning and downsizing.

The semiconductor chip is a wafer level chip scale package (CSP).
It is preferably a semiconductor. This is because it is suitable for quality assurance in addition to being thin and compact.

The step of embedding the semiconductor chip in a plate-like body is performed by removing the release carrier on which the wiring pattern is formed.
A step of embedding two semiconductor chips in the thickness direction in the plate-shaped body with their upper surfaces facing each other by stacking and pressing the plate-shaped body with the plate-shaped body sandwiched between them and applying pressure. Is preferably. This is because it is suitable for thinning and downsizing without creating a wasted space.

The wiring pattern is further formed on the other main surface of the electrically insulative substrate, and the electrically insulative substrate has the upper surfaces of the semiconductor chips facing each other. Of the two semiconductor chips, one of the two semiconductor chips is electrically connected to a wiring pattern formed on the main surface of the electrically insulating substrate, and the other is the other main part of the electrically insulating substrate. You may electrically connect to the wiring pattern formed in the surface. This is because this method is also suitable for thinning and downsizing without making useless space.

It is preferable that the wiring pattern formed on at least the main surface of the electrically insulating substrate is a part of the wiring pattern on the surface layer of the multilayer wiring substrate laminated on the electrically insulating substrate. By using a multilayer wiring board, not only high integration and high performance can be achieved, but also strength and handling are improved.

It is preferable that a passive component is further built in the electrically insulating substrate, and the passive component is electrically connected to any one of the plurality of wiring patterns. High performance can be achieved by incorporating passive components at the same time. The passive element is, for example, at least one selected from an inductor, a capacitor, and a resistor (hereinafter, also referred to as LCR).

The connecting portion between the semiconductor chip and the wiring pattern is made of an underfill resin, an electrically insulating film (NC).
F: Non Conductive Film) or an anisotropic conductive film containing conductive particles (ACF: Anisotropic Conductive Film)
It is preferable to reinforce by. Here, the underfill material indicates a sealing resin, which is composed of, for example, an inorganic filler and an epoxy resin, and is used by a method of injecting as a liquid resin composition.

It is also possible to form a multi-stage laminated module by laminating 4 to 8 layers of the circuit component built-in module. At this time, it is preferable that adjacent circuit component built-in modules are electrically connected by the inner vias. In this way, the layers can be stacked in any number.

An electrically insulating substrate having an inner via is disposed between the adjacent circuit component built-in modules, and the electrically insulative substrate has the same composition as the electrically insulating substrate constituting the circuit component built-in module. It is preferable. If the same composition is used, even if a multi-stage laminated module is formed, the physical properties of each layer can be kept the same.

When 4 to 8 layers of the circuit component built-in module are laminated to form a multi-stage laminated module, an electrically insulating substrate provided with an inner via is arranged between adjacent circuit component built-in modules, and the electrically insulating property is obtained. A film-like passive element may be arranged on the substrate.

The release carrier is preferably a metal sheet or a resin sheet.

The resin sheet is preferably at least one resin film selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulphite, polyethylene, polypropylene and fluororesin. The preferable thickness of the release carrier is 30 to 100 μm. Fluororesin is, for example, polytetrafluoroethylene (PTF).
E), tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer (PFA), tetrafluoroethylene-hexafluoropropylene copolymer (FE
P), polyvinyl fluoride, polyvinylidene fluoride and the like.

The metal sheet may be copper foil. Further, the release carrier may be a copper foil, the metal wiring pattern may be a copper foil, and the release layer between the release carrier and the wiring pattern may be a chrome plating layer.

When a metal foil having a thickness of 30 μm or more, such as a copper foil, is used for the release carrier, a copper foil wiring pattern is formed via a metal plating layer, for example, a Cr plating layer or a Ni plating layer. It may have been done. The wiring pattern can be formed by, for example, adhering a copper foil to the release carrier in a plating process, and then performing a photolithography process and an etching process. By doing so, the copper foil surface after peeling the carrier sheet can be cleaned more than when the resin film is used for the carrier. That is,
Since the electroplating interface is directly exposed, it is possible to expose a less oxidized and shiny untreated copper foil interface.

It is preferable that the semiconductor chip and the passive element are subjected to a continuity test before being embedded in the first plate-shaped body. If this is done, the yield of products will increase. Of course, it is also preferable to inspect after manufacturing the circuit component built-in module.

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a circuit component built-in module 112 according to this embodiment. The circuit component built-in module 112 has a configuration in which the semiconductor chip 103 is built in the electrically insulating substrate 101. 102
b and 102c are wiring patterns formed on the main surface of the electrically insulating substrate 101, and 102a is a wiring pattern formed on the other main surface of the electrically insulating substrate 101. Each wiring pattern is made of copper foil or a conductive resin composition. The wiring patterns 102a and 102b are electrically connected via an inner via 104 formed so as to penetrate the electrically insulating substrate 101. The semiconductor chip 103 has bumps 10
It is electrically connected to the wiring pattern 102c through 5. The connecting portion between the semiconductor chip 103 and the wiring pattern 102c is sealed and reinforced by the electrically insulating sheet 106. In addition to the electrically insulating sheet 106, the connecting portion is a sealing resin such as an underfill material, an electrically insulating film (NCF), or an anisotropic conductive film (ACF) containing conductive particles.
It may be reinforced with a tive film).

The semiconductor chip 103 in the circuit component built-in module 112 needs to have a thickness of 30 to 100 μm, preferably 30 to 50 μm. 100
If the thickness exceeds μm, the module with a built-in circuit component cannot be made thin, and in the case of a multi-layer stacked module, sufficient high-density mounting may not be realized. The thickness of the circuit component built-in module 112 is 80 to 200 μm.

In this embodiment, active components, that is, transistors, ICs (integrated circuits), LSIs (large s) are used.
In addition to semiconductor chips such as cale integrated circuits), passive components, that is, chip components having various L (inductor), C (capacitor) and R (resistor) functions of 1005 and 0603 sizes, surface acoustic wave (SAW) devices, Alternatively, a capacitor formed by printing and a film-like element having a resistance function may be connected to the wiring pattern 102c and built in the circuit component built-in module 112.

The electrically insulating substrate 101 is made of a mixture containing an inorganic filler and a thermosetting resin. Examples of the inorganic filler include Al ₂ O ₃ , MgO, BN, AlN and Si.
O ₂ etc. can be used. As the thermosetting resin, epoxy resin, phenol resin, cyanate resin, or polyphenylene ether resin can be used. Epoxy resin is particularly preferable because it has high heat resistance.

The content of the inorganic filler in the mixture is
It is preferably 70 to 95% by weight. Further, it is preferable that the inorganic filler is densely packed in order to enhance the thermal conductivity and the like of the electrically insulating substrate. For example, in order to lower the dielectric constant of the substrate, if SiO ₂ (silica filler) is used and its content is 80% by weight or more, the thermal conductivity becomes 1 W / m · K or more. Further, in order to increase the thermal conductivity of the substrate, if AlN (aluminum nitride) filler is used as the inorganic filler and the content thereof is 95% by weight, the thermal conductivity becomes about 10 W / m · K. When Al ₂ O ₃ is 88% by weight, the thermal conductivity is about 3-4 W / m · K.

The average particle size of the inorganic filler is 0.1 to 1
The range of 00 μm is preferable. In addition to the inorganic filler, the mixture may contain a dispersant, a colorant, a coupling agent, a release agent, etc., if necessary.

The inner via 104 is made of a cured product of a conductive resin composition. This conductive resin composition is preferably composed of a mixture of 85 to 92% by weight of metal particles and 8 to 15% by weight of a thermosetting resin. For the metal particles, for example, gold, silver, copper, nickel or the like having high conductivity or a mixture thereof can be used. Of these, copper is preferable because it has less migration. An epoxy resin, a phenol resin, a cyanate resin, or a polyphenylene ether resin can be used as the thermosetting resin. Of these, epoxy resins are preferable because they have high heat resistance.

The bump 105 may be either a plated bump or a stud bump, but a stud bump is preferable from the viewpoint of enhancing the reliability of connection with the wiring pattern 102.

According to this structure, since the semiconductor chip of 30 to 100 μm is built in the electrically insulating substrate, and the wiring pattern of the module is connected by the inner via filled in the through hole of the substrate, the circuit component is built in. The module can be made sufficiently thin. Further, the semiconductor chip is built in the electrically insulating substrate to be shielded from the outside air, deterioration due to moisture is prevented, and the reliability of the circuit component built-in module is enhanced. Further, rewiring and quality inspection are facilitated, restrictions on the structural design of the circuit board are reduced, and LGA (land grid array) electrodes having various configurations can be manufactured.

An example of a method of manufacturing the circuit component built-in module 112 according to this embodiment will be described with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, a semiconductor carrier 203 having a thickness of 200 to 400 μm is formed on a bump 2 by using a release carrier 207 having a wiring pattern 202c formed thereon.
Flip chip mounting is carried out on the wiring pattern 202c via 05. For the release carrier 207, an organic resin film such as a polyester film, polyethylene terephthalate, polyphenylene sulfide, or a fluororesin can be used, and various metal foils such as copper foil and aluminum foil can also be used. The release carrier 207 may be coated with an appropriate organic film to form a release layer.

The wiring pattern 202c is the release carrier 2
It can be formed by electroplating copper having a thickness of about 9 to 35 μm on the surface of 07. Alternatively, a copper foil may be attached to the surface of the release carrier 207, and then a photolithography process and an etching process may be performed. Wiring pattern 202
In order to improve the adhesiveness with the composite sheet 201, c is preferably roughened by depositing fine metal particles on its surface. The wiring pattern 202c may be an untreated Cu foil without a rust preventive layer, or its surface may be subjected to a coupling treatment in order to improve adhesion and oxidation resistance. In addition to copper, the wiring pattern 202c may be formed by electroplating tin, zinc, nickel, gold, or the like, or the surface thereof may be solder-plated from a tin-lead alloy, tin-silver-bismuth-based material, or the like. Alternatively, lead-free solder plating may be applied.

In this embodiment, the semiconductor chip 2 is provided by interposing the electrically insulating sheet 206 between the semiconductor chip 203 and the wiring pattern 202c during flip chip mounting.
03 and the wiring pattern 202c are reinforced. Then, heating and pressurization are performed, and as shown in FIG.
05 via the semiconductor chip 203 and the wiring pattern 202
Complete the connection with c. Instead of the bump 205, a conductive adhesive may be used. As the conductive adhesive, for example, gold, silver, copper, or a silver-palladium alloy kneaded with a thermosetting resin can be used. Instead of the conductive adhesive, a gold bump or a solder bump manufactured by a gold wire bonding method is used as the semiconductor chip 203.
They may be connected to each other by heat treatment and melting. It is also possible to use a conductive adhesive and a solder bump together.

Instead of using the electrically insulating sheet 206, a sealing resin such as an underfill material is used for the wiring pattern 2.
02c and the semiconductor chip 203 may be injected.
When the connection portion is reinforced with the sealing resin, the stress generated by the difference in the coefficient of thermal expansion between the semiconductor chip 203 and the composite sheet 201 is absorbed by the entire sealing resin, and the stress concentration can be effectively suppressed, so that the semiconductor chip 203 can be prevented. Composite sheet 2
It is also possible to prevent the occurrence of a gap between the semiconductor chip 203 and the wiring pattern 202c when the semiconductor chip 203 is embedded in the wiring 01. Other than the sealing resin, an electrically insulating film (NCF) or an anisotropic conductive film (ACF) containing conductive particles can be used if necessary.

Next, as shown in FIG. 2C, the semiconductor chip 203 is ground to a grinding line in the figure by a grinder or the like whose surface layer is composed of diamond abrasive grains, to a thickness of 30 to 100 μm, preferably 30 to 100 μm. Process to 50 μm. Although the grinding method is used here, other methods such as a lapping method and an electric discharge machining method may be used. However, in the case of processing at high speed, it is preferable to fix the mold release carrier to a mold jig or the like and perform the grinding method. According to this method, a semiconductor chip having a thickness of about 200 to 400 μm can be easily processed at a high speed to about 50 to 100 μm without damaging it.

Subsequently, as shown in FIG. 2D, the release carrier 207 on which the semiconductor chip 203 is mounted and the through hole 20.
4 and the composite sheet 201 having the through holes 20
Position and stack 4 while being careful not to distort the position and shape. The composite sheet 201 is manufactured by mixing an inorganic filler and an uncured thermosetting resin to form a paste-like mixture, and molding the mixture into a plate-shaped body having a constant thickness. In addition, in the through hole 204,
A conductive resin composition containing metal particles and an uncured thermosetting resin is filled in advance.

2E, the semiconductor chip 203 is embedded in the composite sheet 201, and then the mixture of the composite sheet 201 and the through holes 2 are formed.
Heating is performed at a temperature (for example, 150 to 260 ° C.) which is equal to or higher than the temperature at which the conductive resin in 04 is cured. As a result, the composite sheet 201 becomes the electrically insulating substrate 201a, and the through holes 204 become the inner vias 204a. At this time, the wiring patterns 202a and 202b and the electrically insulating substrate 201a are firmly adhered. In addition, by applying a pressure of 10 to 200 kg / cm ² during heating,
It is possible to improve the transferability of the wiring pattern to the obtained circuit component built-in module 212 and the reliability of via connection.

Thereafter, as shown in FIG. 2F, the release carrier 207 is mechanically peeled from the electrically insulating substrate 201a, the wiring patterns 202b and 202c are transferred onto the electrically insulating substrate 201a, and the circuit component built-in module is formed. Get 212.

After this, the circuit component built-in module 2
A resist is printed on the main surface 12 and the other main surface to form the wiring patterns 202a and 202b on the circuit component built-in module 2
12 may be fixed, underfill may be injected into the wiring pattern portion, or the circuit component built-in module 21
The wiring patterns 202a and 202b may be sealed by stacking an uncured resin sheet on 2.

According to this manufacturing method, since the semiconductor chip mounted on the release carrier is processed into a thin shape, a thin circuit component built-in module having a thickness of 80 to 200 μm can be stably manufactured.

Moreover, since a mixture of an inorganic filler and a thermosetting resin is used for the electrically insulating substrate, it is not necessary to sinter at a high temperature unlike a ceramic substrate, and the substrate can be easily manufactured.

Furthermore, since the electrically insulating substrate contains the inorganic filler, the heat generated in the semiconductor chip is quickly dissipated to the outside, and the reliability of the circuit component built-in module is improved. By changing the type of the inorganic filler and the content rate in the substrate, it is possible to easily manufacture a circuit component built-in module having various characteristics by changing the linear expansion coefficient, thermal conductivity, dielectric constant, etc. of the substrate. You can
For example, by making the linear expansion coefficient of the substrate close to that of the semiconductor chip, the occurrence of cracks due to temperature changes can be effectively prevented, and by lowering the dielectric constant of the substrate, a high-frequency circuit with small dielectric loss can be obtained. Module can be manufactured.

Furthermore, since a bare semiconductor chip generally requires a quality check before it is mounted on a substrate, it is difficult to handle and the cost is limited. However, according to this manufacturing method, Since the state in which the semiconductor chip is built in the substrate is regarded as the initial package form and the quality of the semiconductor chip can be checked, the problem of so-called KGD (known good die) as a module can be cleared. Here, KGD means that an inspection (burn-in inspection) including a continuity inspection in a heated state is performed, and only acceptable products are treated as packaged products.

(Second Embodiment) FIG. 3A shows a sectional view of a circuit component built-in module 312 according to the present embodiment.
The circuit component built-in module 312 includes the semiconductor chip 303.
However, it has a configuration in which it is built in the electrically insulating substrate 301 in the form of a wafer level chip scale package (wafer level CSP) having a sufficiently thin chip thickness. Separately, the multilayer substrate 303a is also integrated and incorporated. 302
a is a wiring pattern formed on the main surface of the electrically insulating substrate 301, and 302b is a wiring pattern formed on the other main surface of the electrically insulating substrate 301. Wiring pattern 3
02a and 302b are electrically connected via an inner via 304 formed so as to penetrate the electrically insulating substrate 301.

FIG. 3B shows a wafer level CSP 303a.
An example of the configuration in which is mounted on the multilayer substrate 306 for rewiring is shown. The circuit component built-in module 312 includes the metal bumps 30.
It is connected to the multilayer substrate 306 via 5.

The semiconductor chip 303 has a thickness of 30 to 10
It is necessary to be 0 μm, preferably 30 to 50
μm. If the thickness exceeds 100 μm, the circuit component built-in module 312 cannot be thinned, which may cause inconvenience in realizing high-density mounting. The thickness of the circuit component built-in module 312 is 300 to 600 μm.

According to the structure shown in FIG. 3A, when the wafer level CSP 303a having a small number of pins is used, the wafer level CSP 303a is flip-chip mounted and at the same time, the wiring pattern including the rewiring is formed. Since the substrate is not necessary, the module can be thinned more effectively. On the other hand, as shown in FIG. 3B, when the multilayer substrate 306 for rewiring is required, the effect of reducing the thickness of the circuit component built-in module 312 is more conspicuously expressed, which greatly contributes to high density mounting.

Further, according to this configuration, the semiconductor chip 3
03 is built in the circuit component built-in module 312 in a CSP state, that is, in a form in which quality is guaranteed.
The problem of is basically solved.

3C and 3D show an example in which another semiconductor package 307 is mounted and laminated on the multilayer substrate 306 or the electrically insulating substrate 301. In this way, the wiring pattern formed on at least the main surface of the electrically insulating substrate 301,
If the wiring pattern in the first layer of the multilayer substrate 306 matches, the circuit component built-in module 312
The applicable range of is expanded. For example, after the semiconductor chip 303 having a CPU function is processed into a thin shape and embedded in an electrically insulating substrate, a semiconductor package 307 having a memory function is provided.
By mounting and stacking (memory package), a thin and space-saving functional block can be configured.

An example of a method of manufacturing the circuit component built-in module 312 according to this embodiment will be described below with reference to FIGS. 4A to 4C.

First, as shown in FIG. 4A, a wafer level CSP 403a is flip-chip mounted on a multi-layer substrate 406 by a reflow process, and the semiconductor chip 403 is ground to a grinding line in the drawing by a grinder or the like to have a thickness of 30. ˜100 μm, preferably 30 to 50 μm. Although the grinding method is used here, other methods such as a lapping method and an electric discharge machining method may be used. However, when processing at high speed, it is preferable to fix the multilayer substrate 306 to a mold jig or the like and perform the grinding method. According to this method, a semiconductor chip having a thickness of about 200 to 400 μm can be easily processed at a high speed to about 50 to 100 μm without damaging it.

Subsequently, as shown in FIG. 4B, the multi-layer substrate 406 on which the wafer level CSP 403a is mounted and the composite sheet 401 are stacked and pressed to embed the wafer level CSP 403a in the composite sheet 401. Next, heating is performed at a temperature (for example, 150 to 260 ° C.) at which the mixture of the composite sheet 401 is cured. As a result, the composite sheet 401 becomes the electrically insulating substrate 401a (FIG. 4C). Reference numeral 412 is a circuit component built-in module.

Thereafter, as shown in FIG. 4C, for example, the memory package 407 can be mounted on the multilayer substrate 406 and stacked. According to this manufacturing method, even if the memory packages 407 are stacked, the total thickness T is 1 to
A thin circuit component built-in module 412 having a thickness of 2 mm can be stably manufactured. In addition, since the wafer level CSP uses the multilayer substrate mounted by the reflow process,
The production efficiency can be improved.

(Third Embodiment) FIG. 5 shows a sectional view of a circuit component built-in module 512 according to the present embodiment. The members corresponding to the circuit component built-in module 112 according to the first embodiment are made of the same kind of material subjected to the same treatment.
The circuit component built-in module 512 includes a semiconductor chip 503.
a and 503b are incorporated in the electrically insulating substrate 501 with their upper surfaces facing each other. 502b and 5
02c is a wiring pattern formed on the main surface of the electrically insulating substrate 301, and 502a and 502d are wiring patterns formed on the other main surface of the electrically insulating substrate 501.
The wiring patterns 502a and 502b are the electrically insulating substrate 5
It is electrically connected through an inner via 504 formed so as to penetrate 01. Semiconductor chips 503a and 50
3b is electrically connected to the wiring pattern 502d and the wiring pattern 502c via bumps 505, respectively. Between the semiconductor chips 503a and 503b, the thickness of the inorganic filler and the thermosetting resin is 50 to 100 μm.
m buffer layer 507 is formed. 506 is a layer of an electrically insulating sheet.

According to this structure, it is possible to mount the semiconductor chips on the circuit component built-in module with higher density. This effect becomes more prominent when the circuit component built-in modules are laminated to form a multi-stage laminated module.

An example of a method of manufacturing the circuit component built-in module 512 according to this embodiment will be described below with reference to FIGS.
Will be described with reference to.

First, as shown in FIG. 6A,
Ni and Au are formed on the wiring patterns 602b and 602c.
A semiconductor chip 603a having a thickness of 200 to 400 μm is formed by using a release carrier 607a whose layer is formed by electroplating.
Are flip-chip mounted on the wiring pattern 602c via the bumps 607a. Next, the semiconductor chip 603a
To a grinding line in the figure with a grinder or the like to have a thickness of 30 to 100 μm, preferably 30 to 50 μm.
To process.

Next, as shown in FIG. 6B, a 0603 size chip capacitor 603c is mounted on the wiring pattern 602b on the release carrier 607a. When the connecting portion between the semiconductor chip 603a and the wiring pattern 602c is reinforced by a sealing resin such as an underfill material, when the semiconductor chip 603a is flip-chip mounted with the separation distance from the chip capacitor 603c being within 0.5 mm,
Since the sealing resin protrudes by about 0.5 mm and becomes an obstacle, it is preferable to use an electrically insulating film (NCF) having substantially the same area as the area occupied by the semiconductor chip 603a instead of the sealing resin.

Then, as shown in FIG. 6C, the through hole 60
4, composite sheet 601 and semiconductor chip 6
03a and the mold release carrier 607a on which the chip capacitor 603c is mounted, and the mold release carrier 607b on which the semiconductor chip 603b is mounted are aligned and overlapped while being careful not to distort the position and shape of the through hole 604. 6
Reference numeral 05a is a bump on the release carrier.

Next, pressure is applied to the semiconductor sheets 603a and 603b as shown in FIG.
After embedding in 01, the composite sheet 601 is heated at a temperature (for example, 150 to 260 ° C.) higher than the temperature at which the mixture of the composite sheet 601 and the conductive resin in the through holes 604 cure. As a result, the composite sheet 601 becomes the electrically insulating substrate 601.
a, and the through hole 604 is filled with a conductive resin to become an inner via 604a.

Thereafter, as shown in FIG. 6E, the release carriers 607a and 607b are respectively attached to the electrically insulating substrate 601.
a mechanically peeled from the wiring pattern 602a, 60
2b is transferred onto the electrically insulating substrate 601a to obtain the circuit component built-in module 612. Here, since two semiconductor chips are built in the thickness direction of the electrically insulating substrate 601a and the unit module is relatively thick, the release carrier can be easily peeled off.

According to this manufacturing method, since the second plate-like body (electrically insulating substrate 601a) contains the inorganic filler and the thermosetting resin component, the semiconductor chip and the passive element are not damaged and the semiconductor is not damaged. It is possible to manufacture a module including a chip and a passive element. Therefore, for example, a bulky passive element such as a 0603 size capacitor chip or a film-like passive element can be built in the module. Then, this manufacturing method solves the structural design constraint of the circuit board including the optimum arrangement of the circuit components, such as the semiconductor chip and the passive element can be arranged close to each other.

(Fourth Embodiment) FIG. 7B shows a cross-sectional view of a multi-stage stacked module 712 according to the present embodiment. The multi-stage laminated module 712 has a configuration in which the circuit component built-in modules 112 according to the first embodiment are laminated in multiple stages.

Multi-Layered Module 7 According to this Embodiment
An example of the manufacturing method of 12 will be described below with reference to FIGS. 7A-B.

First, the mixture of the composite sheet 701 and the through holes 70 are heated at a heating temperature in the range of 100 to 130 ° C.
Embodiment 1 except that the conductive resin composition in 4 is maintained in a semi-cured or partially-cured state (B stage state).
In the same manner as described above, circuit component built-in modules 701a to 701
d is manufactured (FIG. 7A).

Next, the respective circuit component built-in modules are laminated while controlling the pressure to form a multi-stage laminated module 712 having a four-stage structure (FIG. 7B). In FIGS. 7A-B, 702
a to 702b are wirings formed on both surfaces of the inner via 704, 703a to 703d are semiconductor chips, 705 is a pump formed on the surface of the semiconductor chip, 707a and 707.
Reference numeral 07b is a release carrier.

The multi-stage stacking module 712 can be stacked one after another or collectively.
In the case of stacking them all at once, the manufacturing process can be simplified, such as the step of transferring the wiring pattern is unnecessary.

According to the present embodiment, for example, in the case of the four-stage structure, a thin multi-stage laminated module having a thickness of 400 to 600 μm can be obtained.

(Embodiment 5) FIG. 9B is a sectional view of a multi-stage laminated module 813 according to this embodiment.

The multi-stage laminated module 813 has a structure in which the circuit component built-in modules 512 according to the second embodiment are laminated in multiple stages with the resin sheets 811 provided between adjacent circuit component built-in modules.

According to this structure, the rewiring portions of the terminals of the semiconductor chip built in the circuit component built-in module can be formed by forming two layers in the thickness direction, and the wiring patterns can be three-dimensionally intersected. This makes it possible to increase the degree of freedom in designing the structure of the circuit board. For example, in the case of a multi-layer laminated module having an eight-stage configuration, the thickness is as thin as about 1 mm, and the applicable range is widened. For example, a multi-stage laminated module having a total thickness of 1.5 mm or less when mounted on a mother board can be obtained.

Multi-stage stacked module 8 according to the present embodiment
An example of the manufacturing method of No. 13 will be described below with reference to FIGS. 8A-D and 9A-B.

First, the mixture of the composite sheet 801 and the through-hole 80 are heated at a heating temperature in the range of 100 to 130 ° C.
Embodiment 2 except that the conductive resin composition in 4 is maintained in a semi-cured or partially-cured state (B stage state).
A circuit component built-in module 810 is manufactured in the same manner as.

Next, as shown in FIG. 8A, the release carrier 807a on one surface of the circuit component built-in module 810 is mechanically peeled off. 803a and 803b are semiconductor chips, 8
Reference numeral 07b is a backside release carrier.

Next, as shown in FIG. 8B, the circuit sheet built-in modules 810a and 81 which are adjacent to the resin sheet 811 (B stage state) having the inner via 804b.
0b between them, and they are aligned with each other carefully from the adhesive surface side of the release carrier of the circuit component built-in module from which the release carrier has been peeled off, and stacked.

Next, after pressure is applied to form a laminated state as shown in FIG. 8C, the composite sheet 801 and the resin sheet 8 are formed.
11 and the laminate is heated at a temperature (for example, 150 to 260 ° C.) at which the thermosetting resin in the through holes 804 is cured or higher. Here, the heating temperature may be suppressed to about 130 ° C. to maintain the B stage state. The material of the resin sheet 811 is not particularly limited as long as it is in the B stage state, but a mixture having the same composition as the mixture used for the composite sheet 801 is used, and preferably the mixture used for the composite sheet 801 and the inorganic filler are used. It is better to use a mixture of equal contents.

Then, as shown in FIG. 8D, the release carriers 807a, 80a on the upper and lower surfaces of the multi-layer laminated module 812 are formed.
7b is mechanically peeled off.

Thereafter, as shown in FIG. 9A, a resin sheet 811b (B stage state) is arranged between the adjacent multi-stage laminating modules 812a and 812b, and further resin sheets 811a and 811c (B stage state) are placed in the laminate. Place them one above the other, carefully align and stack, pressurize and stack, then
A temperature equal to or higher than the temperature at which the resin sheet 811 and the uncured thermosetting resin in the through hole 804 are cured (for example, 150 to
It is heated at 260 ° C.) to obtain an 8-stage multi-stage stacked module 813 as shown in FIG. 9B.

According to this manufacturing method, the release carrier is peeled off from only one side of the circuit component built-in module and laminated, so that the release carrier protects the wiring pattern during pressurization, and air oxidation of the wiring pattern is prevented. To be prevented. Further, the resin sheet 811 acts as a buffer layer for avoiding contact of the single module, and effectively prevents the semiconductor chip from being damaged during stacking and pressing.

Further, by peeling the release carriers on the upper and lower main surfaces of the multi-layered module to expose the terminal electrodes, the quality inspection such as the continuity inspection can be more thoroughly performed before the multi-layered lamination.

(Sixth Embodiment) FIG. 10D shows a cross-sectional view of a multi-stage stacked module 912 according to the present embodiment. The multi-layered module 912 is the same as the multi-layered module 813 according to the fifth embodiment, except that a resin sheet 811 is replaced by a connection sheet 915 in which a film capacitor 914 and a film resistor 913 are arranged.

According to this structure, the film-shaped capacitor can be disposed closer to the semiconductor chip than the distance corresponding to the thickness of the module, and the capacitor can effectively function as a bypass capacitor. In addition, the capacity of the capacitor can be increased.

An example of the method of manufacturing the circuit component built-in module according to this embodiment will be described below with reference to FIGS. 10A-D and 11A-C.

First, the circuit component built-in module 910 is manufactured in the same manner as in the fifth embodiment. Then, as shown in FIG. 10A, the release carrier 907a on one surface of the circuit component built-in module 910 is mechanically peeled off. 901 is a composite sheet, 903a and 903b are semiconductor chips,
Reference numeral 904 is an inner via, 905 is a bump, and 907b is a back surface release carrier.

Separately, a connecting sheet 915 is prepared as shown in FIGS. First, as shown in FIG. 11A, a release carrier 907a having a film-shaped capacitor 914 printed thereon, a release carrier 907b having a film-shaped resistor 913 printed thereon, and a resin sheet 911 having a through hole 904 are positioned. Combined and stacked, Figure 11B
The laminated state as shown in FIG. Here, the release carrier 9
A predetermined wiring pattern is formed on 07a and 907b. Further, the capacitor 914 and the resistor 913 are formed by vapor deposition, sputtering, MOCVD (metal-organic chemical va).
por) or a thin film forming method, or screen printing or the like on the release carriers 907a and 907b. The material of the resin sheet 911 is not particularly limited as long as it is in the B stage state, but a mixture having the same composition as the mixture used for the composite sheet 901 is used, and preferably the mixture used for the composite sheet 901 and the inorganic material are used. It is preferable to use a mixture having the same filler content. Next, as shown in FIG. 11C, the release carriers 907a and 907b are attached from the upper and lower surfaces of the resin sheet 911.
Is mechanically peeled off, the resistor 913 and the capacitor 914 are transferred to the resin sheet 911, and then embedded in the resin sheet 911 to produce a connection sheet 915.

Thereafter, as in the fifth embodiment, FIG.
As shown in B, the connection sheet 915 is arranged between the adjacent circuit component built-in modules 910 and 910, and they are aligned and stacked, and pressed to obtain a laminated state as shown in FIG. 10C. As shown, the release carriers 907 a and 907 are attached from the upper and lower surfaces of the multi-layer stacked module 912.
b is mechanically peeled off. As a result, four semiconductor chips
A multi-stage laminated module 912 that is laminated in stages is obtained.

According to this embodiment, the bypass capacitor can be arranged in the immediate vicinity of the bare semiconductor terminal electrode, so that the characteristics having high noise characteristics can be exhibited.

[0102]

As described above, the present invention provides a high density packaged circuit component built-in module for use in various electronic information devices having a small thickness, high performance and miniaturization, and a method for manufacturing the same. it can.

[Brief description of drawings]

FIG. 1 is a sectional view showing a circuit component built-in module according to a first embodiment of the present invention.

2A to 2F are process cross-sectional views showing the method for manufacturing the circuit component built-in module according to the first embodiment of the present invention.

3A to 3D are cross-sectional views showing a circuit component built-in module according to the second embodiment of the present invention.

4A to 4C are process cross-sectional views showing the method of manufacturing the circuit component built-in module according to the second embodiment of the present invention.

FIG. 5 is a sectional view showing a circuit component built-in module according to a third embodiment of the present invention.

6A to 6E are process cross-sectional views showing the method of manufacturing the circuit component built-in module according to the third embodiment of the present invention.

7A to 7C are process cross-sectional views showing the method for manufacturing the multi-stage stacked module in the fourth embodiment of the present invention.

8A to 8D are process cross-sectional views showing the method for manufacturing the multi-stage stacked module in the fifth embodiment of the present invention.

9A-9B are process cross-sectional views showing the method for manufacturing the multi-stage stacked module in the fifth embodiment of the present invention.

10A to 10D are process cross-sectional views showing the method for manufacturing the multi-stage stacked module in the sixth embodiment of the present invention.

11A to 11C are process cross-sectional views showing the method for manufacturing a multi-stage stacked module in the sixth embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a multi-layer stacked module according to the prior art.

FIG. 13 is a sectional view showing another multi-layer stacked module according to the prior art.

[Explanation of symbols]

101,201a, 301,401a, 501,601a Electrically insulating substrate 102,102a, 102c, 202a, 202b, 202c, 302a, 502a, 502c, 502d, 6
02a, 602b, 602c Wiring pattern 103,203,303,403,503a, 503b, 603,603a, 603b, 1001,1104
Semiconductor chip 104,204a, 304,504,604a, 804b inner via 105,205,505,605b bumps 106,206,506 electrically insulating sheet 112,212,312,412,512,612,701a, 810,910 circuit component built-in module 201,401,601,701,801,901 composite sheet 204,604,704,804,904 holes 207,607a, 707a, 707b, 807a, 907a, 907b release carrier 305 metal Bump 306,406 Multilayer substrate 307 Semiconductor package 407 Memory package 507 Buffer layer 603c Chip capacitor 712,812,812a, 813,912 Multi-layer laminated module 811,811a, 811b, 911 Resin sheet 913 Resistor 914 Capacitor 915 Connection sheet 1002 Glass-epoxy substrate 1003 Multi-layer laminated memory package

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiyuki Yamamoto, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Seiichi Nakatani, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Yuhaku St. 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Kazuo Otani 1006, Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (72) Invention Employee Yoshinobu Idogawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Tosaku Nishiyama, 1006 Kadoma, Kadoma City Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (56) References JP 2001- 244638 (JP, A) JP 9-283698 (JP, A) JP 2000-183283 (JP, A) JP 2001-68624 (JP, A) International publication 01/069670 ( O, A1) (58) investigated the field (Int.Cl. ^7, DB name) H01L 25/00 - 25/18

Claims (17)

(57) [Claims] 1. A first electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a main surface of the electrically insulating substrate, and the electrically insulating substrate. A circuit component including a semiconductor chip built in the substrate and electrically connected to the wiring pattern, and an inner via formed through the electrically insulating substrate so as to electrically connect the plurality of wiring patterns. A method of manufacturing a built-in module, comprising the steps of forming a through-hole in the electrically insulating substrate to prepare a plate-like body filled with a thermosetting conductive substance therein, and forming the plate-like body on a release carrier. the semiconductor chip is mounted on the wiring pattern, before Symbol a step the non-wiring surface you cut Ken semiconductor chip, then the surface on which the wiring pattern is formed of the release carrier, wherein the wiring pattern transmural As part conductive material in the hole is filled are matched, superimposed by aligning the plate-like body, and burying the semiconductor chip to the plate-like body in by pressurizing, followed by heating Accordingly, the method for manufacturing a circuit component built-in module, comprising: a step of curing the mixture and the conductive substance; and a step of peeling the release carrier. 2. The non-wiring surface of the semiconductor chip is ground.
Including a step of making a thickness of 30 μm or more and 100 μm or less,
The thickness of the circuit component built-in module is 80 to 200 μm.
The manufacturing of the circuit component built-in module according to claim 1.
Method. 3. A semiconductor chip ground on the release carrier.
Includes the process of mounting passive components that are taller than
2. The circuit component built-in module according to claim 1, wherein
Manufacturing method. 4. The step of embedding the semiconductor chip in the plate-shaped body is performed by aligning and stacking the plate-shaped body while sandwiching the plate-shaped body by using two release carriers each having the wiring pattern formed thereon. The method for manufacturing a circuit component built-in module according to claim 1 , which is a step of burying two semiconductor chips in the thickness direction in the plate-shaped body with their upper surfaces facing each other by pressing. 5. The wiring pattern is further formed on the other main surface of the electrically insulating substrate, and the electrically insulating substrate is electrically insulated with the semiconductor chips facing each other. Two semiconductor chips are embedded in the thickness direction of the electrically insulating substrate, one of the two semiconductor chips is electrically connected to a wiring pattern formed on the main surface of the electrically insulating substrate, and the other is of the electrically insulating substrate. The method for manufacturing a circuit component built-in module according to claim 1 , wherein the wiring pattern is electrically connected to a wiring pattern formed on the other main surface. 6. A mixture containing an inorganic filler and a thermosetting resin.
A first electrically insulating substrate made of a material, and the electrically insulating substrate
Multiple wiring patterns formed on at least the main surface of the board
When, built in the electrically insulating substrate, conductive to the wiring pattern
The semiconductor chip electrically connected to the plurality of wiring patterns so as to electrically connect
The inner via formed through the electrically insulating substrate
A method of manufacturing a module having a built-in circuit component, the method comprising: forming a through hole in the electrically insulating substrate,
The step of preparing a plate-shaped body filled with the conductive substance , and the semiconductor chip on the multilayer substrate on which the wiring pattern is formed.
After mounting, the non-wiring surface of the semiconductor chip on the multilayer board is ground.
And a wiring pattern of the multi-layer substrate on which the semiconductor chip is mounted
And the part filled with the conductive material in the through hole is aligned.
So that the multi-layer substrate and the plate-like body are stacked and pressed.
By embedding the semiconductor chip in the plate-like body
And then heating the mixture and the conductive material.
Circuit part characterized by including a step of curing a volatile substance
Manufacturing method of built-in module. 7. incorporates an additional passive components in the electrically insulating substrate, wherein the passive component manufacturing method of the circuit component built-in module according to claim 1 electrically connected to any of said plurality of wiring patterns. 8. The method for manufacturing a circuit component built-in module according to claim 7 , wherein the passive element is at least one selected from an inductor, a capacitor, and a resistor. 9. An underfill resin, an electrically insulating film (N) is formed at a connection portion between the semiconductor chip and the wiring pattern.
CF: Non Conductive Film or ACF: Anisotropic Conductive Fil
The method for manufacturing a circuit component built-in module according to claim 1 , wherein the module is reinforced by m). 10. The circuit component built-in module is 4-8.
The method for manufacturing a circuit component built-in module according to claim 1 , wherein adjacent circuit component built-in modules are electrically connected by the inner vias when the multi-layered module is formed by stacking layers. 11. A second electrically insulative substrate having an inner via is arranged between the adjacent circuit component built-in modules, and the second electrically insulative substrate constitutes the circuit component built-in module. 11. The method for manufacturing a circuit component built-in module according to claim 10 , wherein the same composition as that of the electrically insulating substrate is used. 12. The circuit component built-in module is 4-8.
An electrically insulating substrate having an inner via is arranged between adjacent circuit component built-in modules when forming a multi-layer laminated module by laminating layers, and a film-like passive element is arranged on the electrically insulating substrate. Item 2. A method for manufacturing a circuit component built-in module according to Item 1 . 13. The method for manufacturing a circuit component built-in module according to claim 1 , wherein the circuit component built-in module has a thickness of 100 to 150 μm. 14. The method for manufacturing a circuit component built-in module according to claim 1 , wherein the release carrier is a metal sheet or a resin sheet. 15. The resin sheet is polyimide, polyethylene terephthalate, polyethylene naphthalate,
The method for manufacturing a circuit component built-in module according to claim 14 , which is at least one resin film selected from polyphenylene sulfite, polyethylene, polypropylene, and fluororesin. 16. The metal sheet is a copper foil according to claim 1
4. A method of manufacturing a circuit component built-in module according to item 4 . 17. The release carrier is a copper foil, the wiring pattern is a copper foil, according to claim 1, a release layer between the wiring pattern and the release carrier is formed by chromium plating layer Of manufacturing a circuit component built-in module of.