JP3522555B2 - Surface treatment method for semiconductor substrate - Google Patents

Surface treatment method for semiconductor substrate

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Publication number
JP3522555B2
JP3522555B2 JP34151298A JP34151298A JP3522555B2 JP 3522555 B2 JP3522555 B2 JP 3522555B2 JP 34151298 A JP34151298 A JP 34151298A JP 34151298 A JP34151298 A JP 34151298A JP 3522555 B2 JP3522555 B2 JP 3522555B2
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JP
Japan
Prior art keywords
semiconductor substrate
oxide film
surface treatment
treatment method
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP34151298A
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Japanese (ja)
Other versions
JP2000173975A (en
Inventor
健夫 加藤
英之 近藤
和成 高石
Original Assignee
三菱住友シリコン株式会社
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Publication of JP2000173975A publication Critical patent/JP2000173975A/en
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  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体基板の表面
粗さ(凹凸)を低減する半導体基板の表面処理方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate surface treatment method for reducing the surface roughness (irregularities) of a semiconductor substrate.

【0002】[0002]

【従来の技術】半導体基板の表面の微視的な粗さは一般
にマイクロラフネス(microroughness)と呼ばれてい
る。これまでこの表面粗さがデバイスの酸化膜耐圧など
のデバイス特性に悪影響を及すことが指摘されている。
このマイクロラフネスは1μm以下数nmのオーダの表
面粗さである。近年、バッファードフッ酸洗浄液(以
下、緩衝HFという。)とH22との混合液にシリコン
基板を浸漬することにより、シリコン基板のマイクロラ
フネスを低減又は緩和する方法が提案されている(Mura
matsu et al.,Proc 4th Int SympClean Technol Semico
nd Devices Manuf, p436(1996))。この方法におけるマ
イクロラフネスの低減又は緩和のメカニズムは次の通り
である。即ち、上記混合液中ではH22によるシリコン
基板の表面の酸化と緩衝HFによる表面酸化膜のエッチ
ングが同時に発生する。このH22による基板表面の酸
化の際に、表面の凸部では周囲から酸化性物質が容易に
供給されるが、表面の凹部では酸化性物質が供給されに
くい。このため凸部の方が凹部よりも酸化が進み易い。
従って酸化された部位は逐次エッチングされるが、より
酸化の進んだ凸部が酸化の進まない凹部よりもより一層
エッチングされることから、シリコン基板の表面の凹
凸、即ちマイクロラフネスが低減又は緩和される。
2. Description of the Related Art The microscopic roughness of the surface of a semiconductor substrate is generally called microroughness. It has been pointed out that this surface roughness adversely affects the device characteristics such as the oxide film breakdown voltage of the device.
This microroughness is a surface roughness on the order of 1 μm or less and several nm. In recent years, a method of reducing or mitigating the microroughness of a silicon substrate by immersing the silicon substrate in a mixed solution of a buffered hydrofluoric acid cleaning solution (hereinafter referred to as buffer HF) and H 2 O 2 has been proposed ( Mura
matsu et al., Proc 4th Int SympClean Technol Semico
nd Devices Manuf, p436 (1996)). The mechanism for reducing or mitigating the microroughness in this method is as follows. That is, in the above mixed solution, the oxidation of the surface of the silicon substrate by H 2 O 2 and the etching of the surface oxide film by the buffer HF occur simultaneously. When the substrate surface is oxidized by this H 2 O 2, the oxidizing substance is easily supplied from the surroundings to the convex portions on the surface, but it is difficult to supply the oxidizing substance to the concave portions on the surface. Therefore, the convex portion is more likely to be oxidized than the concave portion.
Therefore, the oxidized portion is sequentially etched, but since the more oxidized convex portion is etched more than the non-oxidized concave portion, the unevenness of the surface of the silicon substrate, that is, microroughness is reduced or alleviated. It

【0003】[0003]

【発明が解決しようとする課題】しかし、デバイスの製
造に使用されるシリコン基板の表面が(100)面であ
る場合、BHFにより基板表面をエッチングしたときに
はエッチング溶液中のOHイオンは(111)面を表出
させる異方性を有するため、このエッチングだけに依拠
した上記従来の方法では、(100)面の表面粗さのよ
り一層の低減は困難であった。本発明の目的は、半導体
基板の表面粗さをより一層低減し得る半導体基板の表面
処理方法を提供することにある。
However, when the surface of the silicon substrate used for manufacturing the device is the (100) plane, when the substrate surface is etched by BHF, the OH ions in the etching solution are (111) plane. It is difficult to further reduce the surface roughness of the (100) plane by the above-mentioned conventional method that relies only on this etching because it has anisotropy that causes An object of the present invention is to provide a surface treatment method for a semiconductor substrate, which can further reduce the surface roughness of the semiconductor substrate.

【0004】[0004]

【課題を解決するための手段】請求項1に係る発明は、
図1及び図2に示すように電解液11中に半導体基板1
3と半導体基板13に密着するか又は0.1nm〜10
μmの範囲で均一な間隔をあけて配置された平均表面粗
さが1μm未満の電極板14とをそれぞれ浸漬し、半導
体基板13と電極板14との間に電位差を与えることに
より半導体基板13の表面に酸化膜18を形成し、半導
体基板13表面に形成された酸化膜18をエッチング液
21中に浸漬して除去する半導体基板の表面処理方法で
ある。請求項2に係る発明は、請求項1に係る発明であ
って、電極板14が劈開性層状グラファイト、仕上げ研
磨したシリコン基板又はエピタキシャル成長膜を有する
シリコン基板である表面処理方法である。
The invention according to claim 1 is
As shown in FIG. 1 and FIG.
3 to the semiconductor substrate 13 or 0.1 nm to 10 nm
The electrode plates 14 having an average surface roughness of less than 1 μm, which are arranged at uniform intervals in the range of μm, are immersed respectively, and a potential difference is applied between the semiconductor substrate 13 and the electrode plates 14 so that the semiconductor substrate 13 This is a surface treatment method for a semiconductor substrate in which an oxide film 18 is formed on the surface and the oxide film 18 formed on the surface of the semiconductor substrate 13 is immersed in an etching solution 21 to be removed. The invention according to claim 2 is the invention according to claim 1, which is the surface treatment method, wherein the electrode plate 14 is a cleavable layered graphite, a silicon substrate that has been subjected to finish polishing, or a silicon substrate having an epitaxial growth film.

【0005】請求項3に係る発明は、請求項1又は2に
係る発明であって、半導体基板13と電極板14との間
に電位差を与える電圧が直流電圧又はバイアスしたパル
ス電圧である表面処理方法である。請求項4に係る発明
は、請求項1ないし3いずれかに係る発明であって、電
解液11がKCl、HF、NaCl又はK2SO4の水溶
液である表面処理方法である。
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the voltage for providing a potential difference between the semiconductor substrate 13 and the electrode plate 14 is a DC voltage or a biased pulse voltage. Is the way. The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the electrolytic solution 11 is an aqueous solution of KCl, HF, NaCl or K 2 SO 4 .

【0006】請求項5に係る発明は、請求項1ないし4
いずれかに係る発明であって、エッチング液21がNH
4OH、KOH、NaOH、NH4OH/H22、HF、
HF/H22、緩衝HF又はHF/HClの水溶液であ
る表面処理方法である。請求項6に係る発明は、請求項
1ないし3いずれかに係る発明であって、電解液11及
びエッチング液21がそれぞれHF水溶液であって、同
一槽で半導体基板の表面に酸化膜18を形成した後、酸
化膜18を除去する表面処理方法である。
The invention according to claim 5 relates to claims 1 to 4.
In the invention according to any one, the etching solution 21 is NH
4 OH, KOH, NaOH, NH 4 OH / H 2 O 2 , HF,
The surface treatment method is an aqueous solution of HF / H 2 O 2 , buffered HF or HF / HCl. The invention according to claim 6 is the invention according to any one of claims 1 to 3, wherein the electrolytic solution 11 and the etching solution 21 are HF aqueous solutions, and the oxide film 18 is formed on the surface of the semiconductor substrate in the same bath. After that, the oxide film 18 is removed.

【0007】[0007]

【発明の実施の形態】請求項1に係る発明では、平均表
面粗さが1μm未満の電極板を使用する。この電極板と
して、表面処理される半導体基板の表面粗さより小さい
粗さの電極板を使用することが好ましい。この平均表面
粗さが1μm以上になると処理される半導体基板の表面
の凸部に対して電界集中が的確に行うことが困難にな
り、半導体基板の表面粗さを低減しにくくなる。電極板
の好ましい平均表面粗さは10nm未満である。また表
面処理される半導体基板としては、シリコン基板(シリ
コンウェーハ)が好ましいが、ゲルマニウム、ガリウム
ヒ素などの他の半導体基板でもよい。
BEST MODE FOR CARRYING OUT THE INVENTION In the invention according to claim 1, an electrode plate having an average surface roughness of less than 1 μm is used. As this electrode plate, it is preferable to use an electrode plate having a roughness smaller than the surface roughness of the semiconductor substrate to be surface-treated. When the average surface roughness is 1 μm or more, it becomes difficult to accurately concentrate the electric field on the convex portions on the surface of the semiconductor substrate to be processed, and it becomes difficult to reduce the surface roughness of the semiconductor substrate. The preferred average surface roughness of the electrode plate is less than 10 nm. The surface-treated semiconductor substrate is preferably a silicon substrate (silicon wafer), but may be another semiconductor substrate such as germanium or gallium arsenide.

【0008】図1に示すように、表面処理される半導体
基板13は上記電極板14とともに電解液11が貯えら
れた電解槽12に浸漬される。半導体基板13は電極板
14に対して、密着するか又は0.1nm〜10μmの
範囲で均一な間隔をあけて配置される。即ち、両板は板
表面を互いに平行に配置される。電極板14と半導体基
板13との間隔が10μmを超える場合には、基板13
の凸部に対して電界集中が起きにくく、凸部における選
択的な酸化が起こりづらくなるため好ましくない。半導
体基板13を陽極16に接続し電極板14を陰極17に
接続して陽極16と陰極17との間に電位差を与える
と、半導体基板13の表面の凸部に電界集中が起こり、
陽極側のこの凸部で電荷の移動を伴う反応が促進される
結果、基板表面の凸部にシリコン酸化膜18が形成され
る。図1では酸化膜18の部分を黒く塗りつぶして示し
ている。一方、基板表面の凹部は凸部と比べて電極板1
4から遠ざかっているため、電界集中は起きにくく、凹
部における酸化膜は形成されないか、形成されたとして
も凸部より薄く形成される。図2に示すように、酸化膜
18が表面に形成された半導体基板13を電解槽12か
ら取出して、エッチング槽19に貯えられたエッチング
液21中に所定の時間浸漬する。その結果、半導体基板
13の凸部に形成された酸化膜18がエッチングにより
除去され、これにより半導体基板13表面の凹凸が低減
される。図1に示すこの凸部への酸化膜の形成工程と、
図2に示す酸化膜のエッチング工程は1回以上繰返すこ
とにより、より凸部がなくなり、半導体基板の表面粗さ
が更に低減する。
As shown in FIG. 1, the surface-treated semiconductor substrate 13 is immersed in the electrolytic bath 12 in which the electrolytic solution 11 is stored together with the electrode plate 14. The semiconductor substrate 13 is in close contact with the electrode plate 14 or is arranged with a uniform interval in the range of 0.1 nm to 10 μm. That is, both plates are arranged such that the plate surfaces are parallel to each other. When the distance between the electrode plate 14 and the semiconductor substrate 13 exceeds 10 μm, the substrate 13
The electric field concentration is unlikely to occur on the convex portions, and selective oxidation on the convex portions is unlikely to occur, which is not preferable. When the semiconductor substrate 13 is connected to the anode 16 and the electrode plate 14 is connected to the cathode 17 and a potential difference is applied between the anode 16 and the cathode 17, electric field concentration occurs on the convex portion on the surface of the semiconductor substrate 13,
As a result of promotion of the reaction accompanied by the movement of charges in the protrusion on the anode side, the silicon oxide film 18 is formed on the protrusion on the substrate surface. In FIG. 1, the oxide film 18 is shown in black. On the other hand, the concave portion on the surface of the substrate is different from the convex portion in the electrode plate 1.
4, the electric field concentration is unlikely to occur, and the oxide film in the concave portion is not formed, or even if it is formed, it is formed thinner than the convex portion. As shown in FIG. 2, the semiconductor substrate 13 on the surface of which the oxide film 18 is formed is taken out of the electrolytic bath 12 and immersed in the etching solution 21 stored in the etching bath 19 for a predetermined time. As a result, the oxide film 18 formed on the convex portion of the semiconductor substrate 13 is removed by etching, thereby reducing the unevenness on the surface of the semiconductor substrate 13. A step of forming an oxide film on the convex portion shown in FIG.
By repeating the etching process of the oxide film shown in FIG. 2 once or more, the convex portions are further eliminated, and the surface roughness of the semiconductor substrate is further reduced.

【0009】請求項2に係る発明では、電極板として劈
開性層状グラファイト、仕上げ研磨したシリコン基板又
はエピタキシャル成長膜を有するシリコン基板を用いる
と、これらのグラファイト、シリコン基板又はエピタキ
シャル成長膜の表面は平滑であって、請求項1記載の平
均表面粗さを有するため、特別の加工をすることなく本
発明に適用することができる。また処理される半導体基
板に対して、金属不純物がないことを要求される場合、
これらのグラファイト又はシリコン基板は電解中に電解
液に金属イオンを溶出しないため好ましい。請求項3に
係る発明では、直流電圧又はバイアスしたパルス電圧を
陽極16と陰極17との間に印加する。直流電圧が印加
される第一の場合には、図3(a)に示すように、陰極
17が接地され、陽極16に+V1の直流電圧が印加さ
れる。この直流電圧は0.5〜50Vの範囲が好まし
い。0.5V未満では凸部でも酸化が起こりにくく、5
0Vを超えると凹部も酸化してしまう不具合を生じる。
また直流電圧が印加される第二の場合には、図3(b)
に示すように、陽極16に+V1のバイアス電圧が印加
され、かつ陰極17に−V2の直流電圧が印加される。
更にバイアスしたパルス電圧が印加される場合には、図
3(c)に示すように、陽極16に0〜+V1ののバイ
アス電圧が印加され、かつ陰極17に0〜−V2のバイ
アス電圧が印加され、これらの電圧の繰返し周波数は
0.1〜100Hzに設定されることが好ましい。
In the invention according to claim 2, when a cleavable layered graphite, a silicon substrate having a finish polishing or a silicon substrate having an epitaxial growth film is used as the electrode plate, the surface of the graphite, the silicon substrate or the epitaxial growth film is smooth. Since it has the average surface roughness according to claim 1, it can be applied to the present invention without any special processing. Also, when it is required that the semiconductor substrate to be processed is free of metal impurities,
These graphite or silicon substrates are preferable because they do not elute metal ions in the electrolytic solution during electrolysis. In the invention according to claim 3, a DC voltage or a biased pulse voltage is applied between the anode 16 and the cathode 17. In the first case where a DC voltage is applied, the cathode 17 is grounded and a DC voltage of + V 1 is applied to the anode 16, as shown in FIG. This DC voltage is preferably in the range of 0.5 to 50V. If it is less than 0.5 V, oxidation is unlikely to occur even in the convex portion.
If it exceeds 0 V, the concave portion may be oxidized, which is a problem.
In the second case, in which a DC voltage is applied, FIG.
As shown in, a bias voltage of + V 1 is applied to the anode 16 and a DC voltage of −V 2 is applied to the cathode 17.
When a further biased pulse voltage is applied, as shown in FIG. 3C, a bias voltage of 0 to + V 1 is applied to the anode 16 and a bias voltage of 0 to −V 2 is applied to the cathode 17. Is applied, and the repetition frequency of these voltages is preferably set to 0.1 to 100 Hz.

【0010】請求項4に係る発明では、電解液11とし
てKCl、HF、NaCl又はK2SO4の水溶液が例示
される。処理される半導体基板に対して、金属不純物が
ないことを要求される場合、電解液には金属イオンを含
まないHFが好ましい。請求項5に係る発明では、エッ
チング液21としてNH4OH、KOH、NaOH、N
4OH/H22、HF、HF/H22、緩衝HF又は
HF/HClの水溶液が例示される。この中でHF、緩
衝HFが酸化膜のみをエッチングするので好ましい。請
求項6に係る発明では、電解液11及びエッチング液2
1がそれぞれHF水溶液である場合、図1に示すように
電解槽12中のHF水溶液に半導体基板13及び電極板
14を浸漬し、半導体基板13に電圧を印加して基板1
3表面に酸化膜18を形成する。引続いて、同一の電解
槽12のHF水溶液中に電圧を印加せずに半導体基板1
3を所定時間浸漬することにより酸化膜18を除去す
る。このように請求項6に係る発明では、電解液とエッ
チング液をHF水溶液のように同一の液により構成した
場合には、この液を貯える槽を同一槽とすることができ
るため、半導体基板の表面処理工程を簡略化することが
でき、図1に示す電解槽12内で、電解とエッチングの
両処理が行われる。
In the invention according to claim 4, an example of the electrolytic solution 11 is an aqueous solution of KCl, HF, NaCl or K 2 SO 4 . If the semiconductor substrate to be treated is required to be free of metal impurities, the electrolyte is preferably HF containing no metal ions. In the invention according to claim 5, NH 4 OH, KOH, NaOH, N is used as the etching liquid 21.
Examples thereof include aqueous solutions of H 4 OH / H 2 O 2 , HF, HF / H 2 O 2 , buffered HF and HF / HCl. Of these, HF and buffer HF are preferable because they etch only the oxide film. In the invention according to claim 6, the electrolytic solution 11 and the etching solution 2
When 1 is an HF aqueous solution, as shown in FIG. 1, the semiconductor substrate 13 and the electrode plate 14 are immersed in the HF aqueous solution in the electrolytic cell 12, and a voltage is applied to the semiconductor substrate 13 to apply the substrate 1 to the substrate 1.
An oxide film 18 is formed on the surface. Subsequently, the semiconductor substrate 1 is applied to the same HF aqueous solution in the electrolytic bath 12 without applying a voltage.
The oxide film 18 is removed by immersing 3 for a predetermined time. Thus, in the invention according to claim 6, when the electrolytic solution and the etching solution are composed of the same solution such as an HF aqueous solution, the tanks for storing this solution can be the same tank, so that the semiconductor substrate The surface treatment process can be simplified, and both electrolysis and etching treatments are performed in the electrolytic bath 12 shown in FIG.

【0011】[0011]

【実施例】次に本発明の具体的態様を示すために、本発
明の実施例を比較例とともに説明する。 <実施例1>図1に示す電解槽12を使用し、下記の条
件で結晶方位が(100)のシリコン基板13を表面処
理した。このシリコン基板13の平均表面粗さ(Ra)
は0.90nmであり、この値は原子間力顕微鏡(AF
M)により10μm角の面積範囲で測定した。また電極
板14は平均表面粗さ(Ra)が0.14nmで、結晶
方位が(100)のシリコン基板を使用した。電解槽1
2中に電解液11として5重量%HF水溶液を貯え、こ
の中に被処理物のシリコン基板13と電極板14を互い
に表面を接触させて浸漬し、シリコン基板13側に+5
Vの電圧を5分間印加してシリコン基板13表面にシリ
コン酸化膜を形成した。引続いて上記5重量%HF水溶
液中にシリコン基板13を5分間浸漬して上記酸化膜を
除去した後、最後にシリコン基板13を水洗し、乾燥し
た。このように表面処理されたシリコン基板13の平均
表面粗さ(Ra)を測定した。その結果、Raは0.6
7nmであった。
EXAMPLES Next, examples of the present invention will be described together with comparative examples in order to show specific embodiments of the present invention. <Example 1> Using the electrolytic cell 12 shown in FIG. 1, a silicon substrate 13 having a crystal orientation of (100) was surface-treated under the following conditions. Average surface roughness (Ra) of this silicon substrate 13
Is 0.90 nm, which is the atomic force microscope (AF
M) was measured in an area range of 10 μm square. The electrode plate 14 used was a silicon substrate having an average surface roughness (Ra) of 0.14 nm and a crystal orientation of (100). Electrolyzer 1
A 5% by weight HF aqueous solution was stored as an electrolytic solution 11 in 2 and the silicon substrate 13 and the electrode plate 14 of the object to be treated were immersed in the solution with their surfaces in contact with each other to give +5 to the silicon substrate 13 side.
A voltage of V was applied for 5 minutes to form a silicon oxide film on the surface of the silicon substrate 13. Subsequently, the silicon substrate 13 was immersed in the 5 wt% HF aqueous solution for 5 minutes to remove the oxide film, and finally the silicon substrate 13 was washed with water and dried. The average surface roughness (Ra) of the silicon substrate 13 thus surface-treated was measured. As a result, Ra is 0.6
It was 7 nm.

【0012】<比較例1>実施例1と同様に図1に示す
電解槽12を使用し、シリコン基板13を表面処理し
た。但し、この比較例1ではシリコン基板13側に電圧
を印加しないで上記5重量%HF水溶液中にシリコン基
板13を5分間浸漬した後、水洗し乾燥したシリコン基
板13の平均表面粗さ(Ra)を実施例1と同様の方法
で測定した。その結果、Raは0.88nmであった。
<Comparative Example 1> As in Example 1, the electrolytic cell 12 shown in FIG. 1 was used and the silicon substrate 13 was surface-treated. However, in Comparative Example 1, the average surface roughness (Ra) of the silicon substrate 13 was obtained by immersing the silicon substrate 13 in the 5 wt% HF aqueous solution for 5 minutes without applying a voltage to the silicon substrate 13 side, and then washing and drying it. Was measured in the same manner as in Example 1. As a result, Ra was 0.88 nm.

【0013】<比較評価>上記実施例1及び比較例1の
結果から明らかなように、実施例1のシリコン基板13
の平均表面粗さ(Ra)は0.90nmから0.67n
mまで大幅に低減されている。これに対し、比較例1の
シリコン基板13の平均表面粗さ(Ra)は0.90n
mから0.88nmまで低減されているが、その低減の
割合は実施例1に比べて小さく、実施例1の低減能力が
比較例1よりも優れていることが判る。
<Comparison Evaluation> As is clear from the results of Example 1 and Comparative Example 1, the silicon substrate 13 of Example 1 is obtained.
Average surface roughness (Ra) of 0.90 nm to 0.67 n
It has been significantly reduced to m. On the other hand, the average surface roughness (Ra) of the silicon substrate 13 of Comparative Example 1 is 0.90n.
Although it is reduced from m to 0.88 nm, the reduction rate is smaller than that in Example 1, and it is understood that the reducing ability of Example 1 is superior to that of Comparative Example 1.

【0014】[0014]

【発明の効果】以上述べたように、本発明の半導体基板
の表面処理方法によれば、電解液中に半導体基板と半導
体基板に密着するか又は0.1nm〜10μmの範囲で
均一な間隔をあけて配置された平均表面粗さが1μm未
満の電極板とをそれぞれ浸漬し、半導体基板に電圧を印
加して基板表面に酸化膜を形成し、半導体基板をエッチ
ング液中に浸漬して上記酸化膜を除去するようにしたの
で、酸化膜が基板の凸部に集中して形成され、この凸部
に形成された酸化膜がエッチングにより除去される。こ
の結果、エッチングだけで凹凸を減らした従来の方法と
比べて、本発明の方法では半導体基板の表面粗さをより
一層低減することができる。
As described above, according to the method for surface-treating a semiconductor substrate of the present invention, the semiconductor substrate and the semiconductor substrate are brought into close contact with each other in the electrolytic solution, or a uniform interval is set in the range of 0.1 nm to 10 μm. An electrode plate having an average surface roughness of less than 1 μm, which is placed apart from each other, is immersed in each of them, a voltage is applied to the semiconductor substrate to form an oxide film on the substrate surface, and the semiconductor substrate is immersed in an etching solution to perform the above oxidation. Since the film is adapted to be removed, the oxide film is concentratedly formed on the convex portion of the substrate, and the oxide film formed on the convex portion is removed by etching. As a result, the surface roughness of the semiconductor substrate can be further reduced by the method of the present invention as compared with the conventional method in which the unevenness is reduced only by etching.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電解液を用いて基板表面に酸化膜を形
成する状況を模式的に示す図。
FIG. 1 is a diagram schematically showing a situation in which an oxide film is formed on the surface of a substrate using the electrolytic solution of the present invention.

【図2】本発明のエッチング液を用いて酸化膜を除去す
る状況を模式的に示す図。
FIG. 2 is a diagram schematically showing a situation in which an oxide film is removed using the etching liquid of the present invention.

【図3】その陽極及び陰極間に印加される電圧を示す
図。
FIG. 3 is a diagram showing a voltage applied between the anode and the cathode.

【符号の説明】[Explanation of symbols]

11 電解液 13 半導体基板 14 電極板 16 陽極 17 陰極 18 酸化膜 21 エッチング液 11 Electrolyte 13 Semiconductor substrate 14 electrode plate 16 Anode 17 cathode 18 Oxide film 21 Etching liquid

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平8−181094(JP,A) 特開 平10−293294(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/304 - 21/3063 H01L 21/308 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-181094 (JP, A) JP-A-10-293294 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/304-21/3063 H01L 21/308

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電解液(11)中に半導体基板(13)と前記半
導体基板(13)に密着するか又は0.1nm〜10μmの
範囲で均一な間隔をあけて配置された平均表面粗さが1
μm未満の電極板(14)とをそれぞれ浸漬し、 前記半導体基板(13)と前記電極板(14)との間に電位差を
与えることにより前記半導体基板(13)の表面に酸化膜(1
8)を形成し、 前記半導体基板(13)表面に形成された酸化膜(18)をエッ
チング液(21)中に浸漬して除去する半導体基板の表面処
理方法。
1. An average surface roughness which is in close contact with the semiconductor substrate (13) and the semiconductor substrate (13) in the electrolytic solution (11) or which is arranged with a uniform interval in the range of 0.1 nm to 10 μm. Is 1
An electrode film (14) having a thickness of less than μm is immersed in each of the electrodes, and a potential difference is applied between the semiconductor substrate (13) and the electrode plate (14) to form an oxide film (1) on the surface of the semiconductor substrate (13).
A method for surface treatment of a semiconductor substrate, which comprises forming 8) and removing the oxide film (18) formed on the surface of the semiconductor substrate (13) by immersing it in an etching solution (21).
【請求項2】 電極板(14)が劈開性層状グラファイト、
仕上げ研磨したシリコン基板又はエピタキシャル成長膜
を有するシリコン基板である請求項1記載の表面処理方
法。
2. The electrode plate (14) is a cleavable layered graphite,
The surface treatment method according to claim 1, wherein the surface-polished silicon substrate or the silicon substrate has an epitaxially grown film.
【請求項3】 半導体基板(13)と電極板(14)との間に電
位差を与える電圧が直流電圧又はバイアスしたパルス電
圧である請求項1又は2記載の表面処理方法。
3. The surface treatment method according to claim 1, wherein the voltage that gives a potential difference between the semiconductor substrate (13) and the electrode plate (14) is a DC voltage or a biased pulse voltage.
【請求項4】 電解液(11)がKCl、HF、NaCl又
はK2SO4の水溶液である請求項1ないし3いずれか記
載の表面処理方法。
4. The surface treatment method according to claim 1, wherein the electrolytic solution (11) is an aqueous solution of KCl, HF, NaCl or K 2 SO 4 .
【請求項5】 エッチング液(21)がNH4OH、KO
H、NaOH、NH4OH/H22、HF、HF/H2
2、緩衝HF又はHF/HClの水溶液である請求項1
ないし4いずれか記載の表面処理方法。
5. The etching solution (21) is NH 4 OH, KO.
H, NaOH, NH 4 OH / H 2 O 2 , HF, HF / H 2 O
2. An aqueous solution of buffered HF or HF / HCl.
5. The surface treatment method according to any one of 4 to 4.
【請求項6】 電解液(11)及びエッチング液(21)がそれ
ぞれHF水溶液であって、同一槽で半導体基板(13)の表
面に酸化膜(18)を形成した後、前記酸化膜(18)を除去す
る請求項1ないし3いずれか記載の表面処理方法。
6. The electrolytic solution (11) and the etching solution (21) are each an HF aqueous solution, and after the oxide film (18) is formed on the surface of the semiconductor substrate (13) in the same tank, the oxide film (18) is formed. ) Is removed, the surface treatment method according to any one of claims 1 to 3.
JP34151298A 1998-12-01 1998-12-01 Surface treatment method for semiconductor substrate Expired - Lifetime JP3522555B2 (en)

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JP3522555B2 true JP3522555B2 (en) 2004-04-26

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Country Link
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