JP3520049B2 - PBGA package incorporating ball grid - Google Patents

PBGA package incorporating ball grid

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Publication number
JP3520049B2
JP3520049B2 JP2000617492A JP2000617492A JP3520049B2 JP 3520049 B2 JP3520049 B2 JP 3520049B2 JP 2000617492 A JP2000617492 A JP 2000617492A JP 2000617492 A JP2000617492 A JP 2000617492A JP 3520049 B2 JP3520049 B2 JP 3520049B2
Authority
JP
Japan
Prior art keywords
package
ball
grid
cavity
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000617492A
Other languages
Japanese (ja)
Other versions
JP2002544670A (en
Inventor
プテイ，クロード
ストリユ，イブ
Original Assignee
ブル・エス・アー
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Publication of JP2002544670A publication Critical patent/JP2002544670A/en
Application granted granted Critical
Publication of JP3520049B2 publication Critical patent/JP3520049B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】本発明は、電子カードにＢＧＡ（「Ｂａｌ
ｌ Ｇｒｉｄ Ａｒｒａｙ」）パッケージを接続する分
野に関し、特にＰＢＧＡ（「Ｐｌａｓｔｉｃ ＢＧ
Ａ」）パッケージに関する。The present invention provides a BGA ("Bal
l Grid Array ”) connection field, especially PBGA (“ Plastic BG ”)
A ") package.

【０００２】「キャビティー・ダウン（ｃａｖｉｔｙ
ｄｏｗｎ）」と呼ばれる空洞（キャビティー）を備えた
ＰＢＧＡタイプの標準パッケージは、「チップ」（「ｃ
ｈｉｐ」）とも称されるＩＣを内部に収容する空洞を含
む。"Cavity down
A standard package of PBGA type with a cavity called "down" is called "chip"("c").
Includes a cavity that houses an IC, also referred to as a "hip").

【０００３】このタイプのパッケージでは、パッケージ
へのチップの接続ゾーンおよびパッケージへのハンダボ
ールアレイの接続ゾーンが、パッケージの同一レベル、
一般には、パッケージの下面、すなわち、パッケージを
カードに組み付けるときにプリント回路カードの正面に
くる面に配置される。In this type of package, the connection zone of the chip to the package and the connection zone of the solder ball array to the package are at the same level of the package,
Generally, it is located on the bottom surface of the package, that is, the surface that faces the front of the printed circuit card when the package is assembled to the card.

【０００４】ボールアレイは、プリント回路カードにチ
ップを電気的かつ機械的に結合する。Ball arrays electrically and mechanically couple a chip to a printed circuit card.

【０００５】半導体層から構成されるチップの作動面お
よび接続線、たとえばボンディング線を、機械的に、ま
た環境に対して保護するために、チップおよびその接続
線の外部を被覆するカプセル封入材料、たとえば電気的
に中性である熱硬化性樹脂を使用する。An encapsulating material which covers the outside of the chip and its connecting lines in order to protect the operating surface and the connecting lines of the chip, which are composed of semiconductor layers, for example the bonding lines, mechanically and against the environment, For example, an electrically neutral thermosetting resin is used.

【０００６】このような方法は、特に、米国特許ＵＳ５
３９７９２１Ａ号に記載されている。Such a method is described in particular in US Pat.
397921A.

【０００７】上記のＢＧＡパッケージに前記の方法を適
用すると、樹脂により被覆された線の高さを、ボールの
高さと釣り合わせなければならないという欠点を有す
る。ボールの高さは通常、約０．６ｍｍであり、ボール
間のピッチは約１．２７ｍｍである。When the above method is applied to the above BGA package, there is a drawback in that the height of the wire covered with the resin must be balanced with the height of the ball. The height of the balls is typically about 0.6 mm and the pitch between the balls is about 1.27 mm.

【０００８】このため、殆ど「金」、またはボールボン
ディング（「ｂａｌｌ ｂｏｎｄｉｎｇ」）技術を使用
することが必要になり、その場合、パッケージは「電解
金」メタライゼーションを含まなければならない。これ
は「フィーダ」の使用を要し、「フィーダ」は、金属被
覆後、高周波、また特にクロック信号にとってのアンテ
ナと同じ線端を残したままにしてしまう。This almost necessitates the use of "gold", or "ball bonding" techniques, in which case the package must include "electrolytic gold" metallization. This requires the use of a "feeder" which, after metallization, leaves the same line ends as the antenna for high frequencies and especially for clock signals.

【０００９】線の配線ループの制御に加えて、線を完全
に被覆するためのコーティング高さも同様に制御しなけ
ればならない。In addition to controlling the wire loops of the wire, the coating height to completely cover the wire must be controlled as well.

【００１０】一般に、粘性の高い接着ビードをパッケー
ジへの線の接続ゾーンの周囲に配置して、線およびチッ
プを適正にコーティングするように、もともとは非常に
流動的なコーティング樹脂の留め壁の役割をするように
する。Generally, a highly viscous adhesive bead is placed around the connecting zone of the wire to the package to serve as a retaining wall for the originally very fluid coating resin to properly coat the wire and chip. Try to do

【００１１】留め壁はまた、パッケージへのボールの接
続ゾーンにコーティング樹脂がはみ出さないようにする
こともできる。The retaining wall can also prevent the coating resin from squeezing out into the connection zone of the ball to the package.

【００１２】もう１つの不都合は、プリント回路カード
へのパッケージ組付け時の、ボールの沈下現象に関す
る。この現象もまたつぶれ（「ｃｏｌｌａｐｓｅ」）と
いう表現で知られている。Another inconvenience relates to the sinking phenomenon of the ball when the package is mounted on the printed circuit card. This phenomenon is also known by the expression "collapse".

【００１３】実際、組付け時に、ボールを構成する合
金、一般には再溶融した錫−鉛合金の表面張力が、カー
ド上へとボールの沈下を引き起こす。In fact, during assembly, the surface tension of the alloys that make up the ball, typically the remelted tin-lead alloy, causes the ball to sink onto the card.

【００１４】かくして、一般に高さ０．６ｍｍ、ピッチ
１．２７ｍｍ、組付け前の当初の直径０．７６ｍｍであ
るボールは、高さが約０．２ｍｍ減少する。この現象
は、特に、一体とされたヒートシンクがパッケージ上部
の面積全体を覆う場合に増大する。その結果、ボールが
相互に短絡することがある。Thus, a ball, which is typically 0.6 mm high, 1.27 mm pitch, and has an initial diameter of 0.76 mm before assembly, has a height reduction of about 0.2 mm. This phenomenon is exacerbated especially when the integrated heat sink covers the entire area of the top of the package. As a result, the balls may short circuit to each other.

【００１５】本発明は、上記の欠点を解消することを目
的とする。The present invention aims to overcome the above drawbacks.

【００１６】このため、本発明は、ＩＣが固定される空
洞を含み、ＩＣの作動面が、パッケージへのボールアレ
イの接続レベルでパッケージに電気的に接続され、ボー
ルアレイが、ＩＣと、パッケージを組み立てるプリント
回路カードとを機械的かつ電気的に結合するＩＣ用パッ
ケージを目的とする。このパッケージは、ＩＣとボール
の接続レベルに取り付けられた、ボールを収容する電気
的に中性の、剛性追加層を備えることを特徴とする。Thus, the present invention includes a cavity in which the IC is fixed, the working surface of the IC being electrically connected to the package at the level of connection of the ball array to the package, the ball array being the IC and the package. A package for an IC that mechanically and electrically couples a printed circuit card for assembling. The package is characterized by an electrically neutral, stiffening layer containing the ball mounted at the connection level of the IC and the ball.

【００１７】本発明は特に、パッケージへのボールの組
付け、いわゆるパッケージの「ボールボンディン」を容
易にするとともに、接続線およびチップを保護するとい
う長所を有する。The invention has the particular advantage of facilitating the mounting of the balls in the package, the so-called "ball bondin" of the package, and the protection of the connecting lines and the chips.

【００１８】本発明はさらに、カードに対してパッケー
ジを所定距離だけ離し、従って、パッケージとカードと
の間でスペーサの役割を果たすことができる。The present invention further allows the package to be separated from the card by a predetermined distance, thus acting as a spacer between the package and the card.

【００１９】本発明の他の長所および特徴は、添付図面
に関してなされた以下の説明を読めば、明らかになるで
あろう。Other advantages and features of the invention will become apparent on reading the following description given in relation to the accompanying drawings.

【００２０】図では、同じ要素に同じ参照記号を付して
おり、図の縮尺率は尊重されていない。In the figures, the same elements are provided with the same reference symbols and the scale of the figures is not respected.

【００２１】また、パッケージを組み付けるプリント回
路カードは、図示していない。The printed circuit card on which the package is assembled is not shown.

【００２２】ＰＢＧＡパッケージへのボール組付け法、
パッケージへのチップ組付け法、パッケージへのチップ
接続法、ならびにカードへのパッケージ組付け法は、公
知であるので説明を省く。A method of mounting a ball on a PBGA package,
The method of assembling the chip into the package, the method of connecting the chip to the package, and the method of assembling the package into the card are well known, and therefore their description is omitted.

【００２３】図１は、ＰＢＧＡパッケージの下面を示
す。FIG. 1 shows the bottom surface of the PBGA package.

【００２４】図２は、図１のカット軸ＡＡによる図１の
パッケージの部分断面図である。FIG. 2 is a partial sectional view of the package of FIG. 1 taken along the cut axis AA of FIG.

【００２５】一般に、「キャビティー・ダウン」ＰＢＧ
Ａパッケージは、銅製で平行六面体の剛性支持体１から
構成され、ほぼ中央にある空洞２を含み、この空洞がチ
ップ３を収容し、チップは、熱伝導性の接着剤５を介し
て空洞２の底４に固定されている。Generally, "cavity down" PBG
The A package consists of a parallelepiped rigid support 1 made of copper, containing a cavity 2 approximately in the center, which contains a chip 3, which is bonded via a thermally conductive adhesive 5 to the cavity 2. It is fixed to the bottom 4 of the.

【００２６】支持体１はさらに、一般に可撓性の誘電性
基板６を支持し、誘電性基板は、空洞２の周辺、従って
チップ３の周辺に配置されている。The support 1 further supports a generally flexible dielectric substrate 6, which is arranged around the cavity 2 and thus around the chip 3.

【００２７】基板６は、その片面に、所定の設計に従っ
て配置されて、ボンディング線およびボールの接続ゾー
ンを含む導電性エリア７ｉを支持する。The substrate 6 is arranged on one side according to a predetermined design and carries a conductive area 7i containing the bonding lines and the ball connection zones.

【００２８】基板６は、反対の面に、たとえば空洞２の
底４にチップ３を固定したものと同じ接着剤９を用いて
支持体１に固定される導電性の平面８を含む。The substrate 6 comprises, on the opposite side, a conductive plane 8 which is fixed to the support 1 by means of the same adhesive 9 that fixes the chip 3 to the bottom 4 of the cavity 2, for example.

【００２９】空洞２の底４と反対側のチップ３の作動面
１０は、接続線１１ｉ、ここでは、同じく「ボンディン
グ」線と呼ばれる接続線を介して導電性エリア７ｉに電
気的に接続される。The working surface 10 of the chip 3 opposite the bottom 4 of the cavity 2 is electrically connected to the conductive area 7i via a connecting line 11i, here also called a "bonding" line. .

【００３０】導電性エリア７ｉは、空洞２を起点とし
て、この空洞２に対して径方向に広がっており、図１に
示したように、所定の設計に従ってパッケージの周辺に
配置された導電性端子１２ｉにそれぞれ続いている。The conductive area 7i extends from the cavity 2 in the radial direction starting from the cavity 2 and, as shown in FIG. 1, the conductive terminals arranged around the package according to a predetermined design. 12i respectively.

【００３１】導電性端子１２ｉは、図２と３に示したよ
うにハンダボール１３ｉをそれぞれ受容するように構成
される。Conductive terminals 12i are configured to receive solder balls 13i, respectively, as shown in FIGS.

【００３２】ボールアレイを形成するボール１３ｉは、
カードにパッケージが組み付けられると、チップ３およ
びカードを電気的かつ機械的に結合する。The balls 13i forming the ball array are
When the package is assembled to the card, the chip 3 and the card are electrically and mechanically coupled.

【００３３】パッケージにおける線１１ｉおよびボール
１３ｉの配線は、導電性エリア７ｉおよび導電性端子１
２ｉの面に対応する同一レベルＮｃで行われる。The wiring of the line 11i and the ball 13i in the package is the conductive area 7i and the conductive terminal 1.
It is performed at the same level Nc corresponding to the surface of 2i.

【００３４】図３は、本発明によるＰＢＧＡパッケージ
を、同じく図１のカット軸ＡＡに沿った部分横断面で概
略的に示している。FIG. 3 schematically shows a PBGA package according to the invention in a partial transverse section also along the cutting axis AA of FIG.

【００３５】このパッケージは、図２に示したパッケー
ジの底と同じ構造を含み、さらに、パッケージに線１１
ｉおよびボール１３ｉを接続するレベルＮｃの下のレベ
ルに、ボール１３ｉを収容する追加層１４を含んでい
る。この追加層は、ボール１３ｉの間に延びており、パ
ッケージへの線１１ｉの接続ゾーンＺｃを被覆しないよ
うに空洞２に対して後退している。This package contains the same structure as the bottom of the package shown in FIG.
Below the level Nc connecting i and the ball 13i, an additional layer 14 containing the ball 13i is included. This additional layer extends between the balls 13i and is recessed with respect to the cavity 2 so as not to cover the connection zone Zc of the line 11i to the package.

【００３６】追加層１４は、所定の機械的な剛性を有
し、電気的に中性である。The additional layer 14 has a predetermined mechanical rigidity and is electrically neutral.

【００３７】追加層１４は、ボール１３ｉをそれぞれ収
容する複数の開口部１５ｉを備えたグリッドを画定す
る。開口部は、約０．２ｍｍの小さい遊びを伴ってボー
ル１３ｉを収容するように十分に広く選択される。The additional layer 14 defines a grid with a plurality of openings 15i for accommodating the balls 13i, respectively. The opening is chosen wide enough to accommodate the ball 13i with a small play of about 0.2 mm.

【００３８】グリッド１４は、カードにパッケージを組
み付けるときに、レジンまたはプリフォームとして接着
により取り付けるか、あるいは製造時にパッケージの構
造に組み込むことができる。The grid 14 can be adhesively attached as a resin or preform when the package is assembled to the card, or incorporated into the structure of the package during manufacture.

【００３９】記載された実施形態によれば、グリッド１
４は、接着により取り付けられている。According to the described embodiment, the grid 1
4 is attached by adhesion.

【００４０】接着層１６は、接続端子１２ｉを被覆しな
いように、またグリッド１４の開口部１５ｉの内部に入
り得ないように、たとえばセリグラフィースクリーンま
たはプリフォームを用いて塗布される。The adhesive layer 16 is applied so as not to cover the connection terminals 12i and so as not to enter the inside of the openings 15i of the grid 14, for example, by using a serigraphy screen or a preform.

【００４１】コーティング材料１７は、チップ３を含む
第１の空洞２よりも広い第２の空洞１８を形成する、グ
リッド１４が残した空間を埋める。The coating material 17 fills the space left by the grid 14, forming a second cavity 18 wider than the first cavity 2 containing the chip 3.

【００４２】このとき、グリッド１４は、ボール１３ｉ
の位置決めグリッドの役割と、チップ３の作動面１０お
よび接続線１１ｉを被覆するコーティング材料１７のた
めの障害物の役割との２つの役割を果たすことが分か
る。グリッド１４の内周は、接続レベルＮｃに接着さ
れ、ボール１３ｉおよび線１１ｉの間で留め壁を形成す
る。At this time, the grid 14 has balls 13i.
It can be seen that it plays two roles, the role of the positioning grid of 1 and the role of an obstacle for the coating material 17 covering the working surface 10 of the chip 3 and the connecting lines 11i. The inner circumference of the grid 14 is glued to the connection level Nc and forms a retaining wall between the ball 13i and the line 11i.

【００４３】しかも、この追加層またはグリッド１４
は、１個のボール当たりの重量が非常に重く、一般的に
はボール１個につき５０ｍｇを越えるパッケージの場
合、所定の厚みに応じてスペーサの役割を果たすことも
できる。これは特に、パッケージの全面を覆う一体化さ
れたヒートシンクを備えたパッケージの場合にいえる。Moreover, this additional layer or grid 14
Can also act as a spacer depending on the given thickness, for packages with a very high weight per ball, generally over 50 mg per ball. This is especially true for packages that include an integrated heat sink that covers the entire surface of the package.

【００４４】こうしたスペーサとしての役割により、チ
ップに対してパッケージを所定距離だけ離し、ボールの
沈下を制御することができる。With such a role as a spacer, the package can be separated from the chip by a predetermined distance to control the sinking of the ball.

【００４５】さらに、追加層により、パッケージをカー
ドに取り付けるとき、ボール間の電気的な絶縁を確保す
ることができる。In addition, the additional layer can ensure electrical insulation between the balls when the package is attached to the card.

【００４６】追加層は、ボール間のピッチが同じであっ
て１．２７ｍｍである場合、ボールの直径を大きくし、
たとえば０．７６ｍｍの代わりに０．９６ｍｍにするこ
とによって、ハンダ容量を増加可能にするという長所を
備える。The additional layer increases the diameter of the balls when the pitch between the balls is the same and is 1.27 mm,
For example, by using 0.96 mm instead of 0.76 mm, the solder capacity can be increased.

【００４７】従って、組み付けられたパッケージの熱サ
イクル下における信頼性が高くなる。Therefore, the reliability of the assembled package under the thermal cycle is enhanced.

【００４８】この特徴は、温度の制約が大きい用途、特
に自動車の用途では、とりわけ重要である。This feature is especially important in applications where there are significant temperature constraints, especially automotive applications.

【００４９】カード上のハンダ付けされるジョイントま
たはリング（「ｒｉｎｇ」）の高さは、実質的に高くす
ることができ、通常は、０．５ｍｍの代わりに０．７ｍ
ｍである。ハンダ付けされたジョイントは、一般に、パ
ッケージ周辺のコンポーネントがハンダ付けされる銅メ
ッキに対応する。The height of the soldered joint or ring ("ring") on the card can be substantially higher, typically 0.7 m instead of 0.5 mm.
m. Soldered joints generally correspond to copper plating to which components around the package are soldered.

【００５０】この結果、配線の制約がゆるめられ、ウェ
ッジ「ｗｅｄｇｅ」技術によるアルミニウム線の利用が
検討可能になる。As a result, the restrictions on wiring are relaxed, and the use of aluminum wires by the wedge "wedge" technique can be considered.

【００５１】パッケージは、その場合、「電解金」仕上
げよりも安価な「無電解金」仕上げをすることができ、
アンテナ（メタライゼーションフィーダ）はない。The package can then have a "electroless gold" finish, which is cheaper than the "electrolytic gold" finish,
There is no antenna (metallization feeder).

【００５２】限定的ではない例として、以下に、本発明
によるパッケージの寸法ならびに、パッケージの各構成
層に使用される材料、およびその個々の厚みを挙げる。By way of non-limiting example, the following gives the dimensions of the package according to the invention, as well as the materials used for the individual constituent layers of the package and their respective thicknesses.

【００５３】例として挙げられたこの例は、寸法交差を
考慮したものではない。This example, given by way of example, does not consider dimensional intersection.

【００５４】パッケージは、一辺が３５ｍｍの平行六面
体である。The package is a parallelepiped whose one side is 35 mm.

【００５５】中央空洞２は、一辺が１５ｍｍの正方形を
画定し、その深さは４０ｍｍである。中央空洞は、一辺
１３ｍｍ、厚さ０．４０ｍｍのほぼ平行六面体の形のチ
ップ３を受容するように構成される。チップ５は、銀を
添加したエポキシ樹脂である厚さ０．１０ｍｍの接着剤
５を介して、空洞２の底４に固定される。The central cavity 2 defines a square with a side of 15 mm and a depth of 40 mm. The central cavity is configured to receive a chip 3 in the form of a substantially parallelepiped 13 mm on a side and 0.40 mm thick. The chip 5 is fixed to the bottom 4 of the cavity 2 via an adhesive 5 having a thickness of 0.10 mm, which is an epoxy resin containing silver.

【００５６】空洞２の辺は、パッケージの辺にそれぞれ
平行である。The sides of the cavity 2 are parallel to the sides of the package.

【００５７】パッケージは、突出部を含めて測った厚さ
が０．７ｍｍの支持体１から構成され、空洞２の底４に
対応する支持体１の厚さは、０．３ｍｍである。The package is composed of a support 1 having a thickness of 0.7 mm including the protrusion, and the thickness of the support 1 corresponding to the bottom 4 of the cavity 2 is 0.3 mm.

【００５８】支持体１は、銅製である。The support 1 is made of copper.

【００５９】支持体１は、その内面に、複数の層の積層
を含み、これについて、パッケージの厚みが薄い方から
順に説明する。The support 1 includes, on its inner surface, a stack of a plurality of layers, which will be described in order from the smallest package thickness.

【００６０】第１の層９は、厚さ０．１０ｍｍのエポキ
シ接着層である。The first layer 9 is an epoxy adhesive layer having a thickness of 0.10 mm.

【００６１】この層は、支持体１に可撓性基板６を固定
する役割をする。This layer serves to fix the flexible substrate 6 to the support 1.

【００６２】第２の層８は、導電性の面に対応し、厚さ
１７μｍの銅製である。The second layer 8 corresponds to the conductive surface and is made of copper with a thickness of 17 μm.

【００６３】第３の層６は、厳密な意味での可撓性基板
に対応し、厚さ５０μｍのポリイミド製である。The third layer 6 corresponds to a flexible substrate in a strict sense, and is made of polyimide having a thickness of 50 μm.

【００６４】第４の層７ｉは、導電性エリアに対応し、
厚さ１７μｍの銅製である。The fourth layer 7i corresponds to the conductive area,
It is made of copper with a thickness of 17 μm.

【００６５】ボール１３ｉおよび接続線１１ｉが固定さ
れるのは、この第４の層７ｉである。It is this fourth layer 7i that the balls 13i and the connecting wires 11i are fixed.

【００６６】第５の層１６は、厚さ０．１０ｍｍの接着
層であり、積層の第４の層７ｉ、すなわち接続レベルＮ
ｃに、「追加層」と呼ばれる第６の層１４を固定するよ
うに構成される。The fifth layer 16 is an adhesive layer having a thickness of 0.10 mm, and is the fourth layer 7i of the laminated layer, that is, the connection level N.
It is configured to fix a sixth layer 14 called "additional layer" to c.

【００６７】追加層１４は、厚さ０．５ｍｍのエポキシ
樹脂製である。追加層は、１．２７ｍｍのピッチでグリ
ッドを画定し、複数のボール１３ｉを収容するための複
数の開口部１５ｉを含んでおり、ボール１３ｉの直径
は、選択された例では、たとえば０．９６ｍｍである。
開口部１５ｉの形は、ほぼ円筒形で、断面が円形であ
る。The additional layer 14 is made of an epoxy resin having a thickness of 0.5 mm. The additional layer defines a grid with a pitch of 1.27 mm and includes a plurality of openings 15i for receiving a plurality of balls 13i, the diameter of the balls 13i being, for example, 0.96 mm in the selected example. Is.
The opening 15i has a substantially cylindrical shape and a circular cross section.

【００６８】グリッド１４の開口部１５ｉの直径は、ボ
ール１３ｉの直径よりも実質的に大きく、約１．０５ｍ
ｍである。The diameter of the opening 15i of the grid 14 is substantially larger than the diameter of the ball 13i and is about 1.05 m.
m.

【００６９】ボールの直径および再溶融後に許容できる
最大高は、スペーサの役割と、パッケージへのボール１
３ｉの位置決めの役割を果たすグリッド１４の最大の厚
みを画定する。The diameter of the ball and the maximum height allowed after remelting depend on the role of the spacer and the ball 1 into the package.
It defines the maximum thickness of the grid 14 which serves for the positioning of 3i.

【００７０】コーティング材料１７、たとえばエポキシ
接着剤は、チップ３の作動面１０ならびに接続線１１ｉ
を被覆する。この材料は、積層の第５の層１６および第
６の層１４により広がりを留められ、また、可撓性の基
板６に接着されたグリッド１４により内周を画定された
第１の空洞よりも広幅の第２の空洞１８に封入される。 ［図面の簡単な説明］The coating material 17, eg epoxy adhesive, is applied to the working surface 10 of the chip 3 as well as to the connecting wires 11i.
To cover. This material is less spread out by the fifth and sixth layers 16 and 14 of the stack and is less than the first cavity bounded by the grid 14 adhered to the flexible substrate 6. It is enclosed in the wide second cavity 18. [Brief description of drawings]

【図１】ボールアレイを備えたＰＢＧＡパッケージの下
面図である。FIG. 1 is a bottom view of a PBGA package including a ball array.

【図２】図１に示したパッケージの部分横断面図であ
る。FIG. 2 is a partial cross-sectional view of the package shown in FIG.

【図３】本発明によるパッケージの部分横断面図であ
る。FIG. 3 is a partial cross-sectional view of a package according to the present invention.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平11−97576（ＪＰ，Ａ) 特開 平８−88293（ＪＰ，Ａ) 特開 平10−256424（ＪＰ，Ａ) 特開 平10−112472（ＪＰ，Ａ) 特開 平８−250835（ＪＰ，Ａ) 米国特許5397921（ＵＳ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 - 23/15 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-11-97576 (JP, A) JP-A-8-88293 (JP, A) JP-A-10-256424 (JP, A) JP-A-10- 112472 (JP, A) JP-A-8-250835 (JP, A) US Pat. No. 5397921 (US, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23 / 12-23 / 15

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ＩＣ（３）が固定される空洞（２）を含
み、ＩＣ（３）の作動面（１０）が、パッケージへのボ
ールアレイ（１３ｉ）の接続レベル（Ｎｃ）で接続線
（１１ｉ）によりパッケージに電気的に接続され、ボー
ルアレイが、ＩＣ（３）と、パッケージが組み付けられ
るプリント回路カードとを機械的かつ電気的に結合す
る、「キャビティー・ダウン」型のＩＣ用パッケージで
あって、ＩＣ（３）とボール（１３ｉ）の接続レベル
（Ｎｃ）に取り付けられた電気的に中性な剛性のグリッ
ド（１４）を含み、その開口部（１３ｉ）が、所定の遊
びを伴ってボールを収容するために十分に広く選択さ
れ、グリッド（１４）が、スペーサを画定し、スペーサ
の厚みが、ボール（１３ｉ）の直径と、カードにパッケ
ージを組付けた後に許容可能なボールの最大高とに応じ
て決定されることを特徴とするパッケージ。1. A cavity (2) in which an IC (3) is fixed, the working surface (10) of the IC (3) connecting lines (Nc) at a connection level (Nc) of a ball array (13i) to a package. 11i) is electrically connected to the package, and the ball array mechanically and electrically couples the IC (3) and the printed circuit card on which the package is assembled to a "cavity down" type IC package. And an electrically neutral rigid grip attached to the connection level (Nc) of the IC (3) and the ball (13i).
A grid (14) defining a spacer , the opening (13i) of which is selected wide enough to accommodate the ball with a predetermined play.
Is the diameter of the ball (13i) and the package on the card.
Depending on the maximum height of the ball allowed after mounting
Package according to claim Rukoto determined Te. 【請求項２】 グリッド（１４）が、このグリッドが収
容するボール（１３ｉ）のための位置決めグリッドを画
定することを特徴とする請求項１に記載のパッケージ。2. Package according to claim 1, characterized in that the grid (14) defines a positioning grid for the balls (13i) which it contains. 【請求項３】 グリッド（１４）が、ＩＣ（３）が固定
される第１の空洞（２）よりも広幅の第２の空洞（１
８）を画定し、その開口部が、パッケージへのＩＣ
（３）の接続ゾーン（Ｚｃ）により画定されることを特
徴とする請求項２に記載のパッケージ。3. A second cavity (1) in which the grid (14) is wider than the first cavity (2) in which the IC (3) is fixed.
8) defining an IC whose opening is to the package
Package according to claim 2 , characterized in that it is defined by the connection zone (Zc) of (3). 【請求項４】 第２の空洞（１８）が、ＩＣ（３）の作
動面（１０）とパッケージへのＩＣの接続線（１１ｉ）
とを完全に被覆するコーティング材料（１７）を含むこ
とを特徴とする請求項３に記載のパッケージ。4. A second cavity (18) defines a working surface (10) of the IC (3) and a connecting wire (11i) of the IC to the package.
Package according to claim 3 , characterized in that it comprises a coating material (17) which completely covers and. 【請求項５】 グリッド（１４）が、パッケージへのＩ
Ｃ（３）の接続ゾーン（Ｚｃ）とボールアレイ（１３
ｉ）との間にコーティング材料のための留め壁を画定す
ることを特徴とする請求項４に記載のパッケージ。5. The grid (14) provides an I to package package.
C (3) connection zone (Zc) and ball array (13
Package according to claim 4 , characterized in that it defines a retaining wall for the coating material with i). 【請求項６】 グリッド（１４）が、パッケージの組立
時に接着により取り付けられることを特徴とする請求項
１から５のいずれか一項に記載のパッケージ。6. Package according to any one of claims 1 to 5 , characterized in that the grid (14) is attached by gluing during assembly of the package. 【請求項７】 グリッド（１４）が、製造時にパッケー
ジの構造に組み込まれることを特徴とする請求項１から
５のいずれか一項に記載のパッケージ。7. The method according to claim 1, wherein the grid (14) is integrated into the structure of the package during manufacture.
5. The package according to any one of 5 .
JP2000617492A 1999-05-10 2000-05-04 PBGA package incorporating ball grid Expired - Lifetime JP3520049B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR99/05930 1999-05-10
FR9905930A FR2793606B1 (en) 1999-05-10 1999-05-10 PBGA HOUSING WITH INTEGRATED BILLING GRILLE
PCT/FR2000/001201 WO2000068991A1 (en) 1999-05-10 2000-05-04 Pbga package with integrated ball grid

Publications (2)

Publication Number Publication Date
JP2002544670A JP2002544670A (en) 2002-12-24
JP3520049B2 true JP3520049B2 (en) 2004-04-19

Family

ID=9545407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000617492A Expired - Lifetime JP3520049B2 (en) 1999-05-10 2000-05-04 PBGA package incorporating ball grid

Country Status (4)

Country Link
EP (1) EP1099253A1 (en)
JP (1) JP3520049B2 (en)
FR (1) FR2793606B1 (en)
WO (1) WO2000068991A1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888293A (en) * 1994-09-19 1996-04-02 Mitsui High Tec Inc Semiconductor mounting device and mounting method for semiconductor device using the same
JP3453663B2 (en) * 1994-09-28 2003-10-06 大日本印刷株式会社 Surface mount type semiconductor device
JP2812238B2 (en) * 1995-03-10 1998-10-22 日本電気株式会社 Mounting method of LSI package having metal bump
KR0157899B1 (en) * 1995-09-22 1998-12-01 문정환 Coupling structure for bonding semiconductor device of subsrate
JPH10112472A (en) * 1996-10-07 1998-04-28 Toshiba Corp Semiconductor device and its manufacture
JPH10256424A (en) * 1997-03-12 1998-09-25 Toshiba Corp Package for semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array

Also Published As

Publication number Publication date
WO2000068991A1 (en) 2000-11-16
JP2002544670A (en) 2002-12-24
EP1099253A1 (en) 2001-05-16
FR2793606A1 (en) 2000-11-17
FR2793606B1 (en) 2003-06-13

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