JP3518835B2 - Transmission equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a device for transmitting, receiving and reproducing moving image signals.

[0002]

2. Description of the Related Art In recent years, image processing technology, especially compression technology for image information and audio information, has made remarkable progress and is capable of transmitting high-quality moving images and audio even on a transmission line having a small capacity. became. By the way, in the above system, a data group sent on the transmission path is called a program stream (PS), and the main contents are system clock reference (SCR) information and compressed data. S
The CR information is information for synchronizing the receiving side system CK with the transmitting side system clock (CK), and the details will be described later. Since each piece of information in the stream is associated with a unique header, the receiving side can easily identify and separate each piece of information by searching the header.

FIG. 7 shows the overall configuration of a transmission system in the prior art. The PS creation unit 2 is a system C on the transmission side.
The video encoder (VENC) 2-1 which operates according to the system CK11 from the K generator 14 first creates compressed data information from the video signal input to the terminal 1. Then, transmission transmission CK12 from the transmission line (transmission unit 3)
According to the above, the program stream (PS) 6 to which the header, SCR information and the like are added is created and output. The transmission unit 3 transmits and sends the program stream 6 concerned CK12
In accordance with the above, the data is fetched from the transmission data terminal and transmitted to the reception data terminal in the form of being output as the program stream 7 together with the transmission reception CK13. Generally, the program stream 6 and the program stream 7 may be delayed in time due to various pre-processing and post-processing of transmission, but if the transmission path is in a normal state, the data content is completely the same. Is. Also, transmission sending CK12 and transmission receiving CK1
The frequencies of 3 are exactly the same.

The PS analysis unit 4 identifies and separates the program stream 7 of the transmission path speed obtained from the transmission unit 3 into SCR information and compressed data information based on the header thereof. Also, the extracted SCR information 8, the hold value 9 of the receiving side system time clock (STC) counter 4-3, the extracted SC
A signal EN indicating the update of R is also output. Extracted SCR information 8
And the hold value 9 of the receiving side STC counter 4-3 is VC
It is input to the O controller 5 and is controlled to generate a system CK16 having the same frequency as the system CK11 used on the transmitting side. This system CK16 is supplied to the PS analyzer 4. Compressed data information is the system CK
12 is decoded into decompressed image data and output.

The internal configuration and operation of each unit will be described in more detail. The PS creation unit 2 uses VENC2-1, FiFo (F
irst In First Out) Memory 2-2, STC counter 2-
3, header controller 2-4, latch 2-5, switch 2-
It consists of 6. A control signal generated from the system CK11 or the system CK11 system related to the input video is supplied to the VENC 2-1, the writing side of the FiFo memory 2-2, and the STC counter 2-3. For example, its frequency is 27 MHz. The read side of the FiFo memory 2-2, the header controller 2-4, the latch 2-5, and the switch 2-6 are supplied with a transmission CK12 related to the transmission unit 3 or a control signal generated by the system. It In addition, the read side of the FiFo memory 2-2, the latch 2
-5, the switch 2-6 operates in synchronization with the transmission CK12 in response to the control signal from the header controller 2-4.
VENC2-1 is an abbreviation for Video Encoder, and VEN
C2-1 converts the input video into compressed data information according to the system CK11. The compressed data information is instantaneously output in synchronization with 27 MHz, but there is also a period during which the output is paused, and the final average information amount becomes a data rate smaller than the capacity of the transmission unit 3. This compressed data information is written in the FiFo memory 2-2 at 27 MHz,
The data is read out by the transmission and transmission CK12 and converted into the rate of the transmission unit 3.

The header controller 2-4 outputs the SC output by itself.
After adding the R header by the switch 2-6, the latch 2-
5 outputs, that is, the switching unit 2-6 is controlled so as to selectively add SCR information, and subsequently, an output of the FiFo memory 2-2 which is compressed data information, that is, compressed data is selected after adding a header for compressed data. The operation is periodically repeated to complete the program stream 6. STC
The counter 2-3 is a counter that operates in the system CK and is, so to speak, a clock that is used as a reference by the transmitting side and the receiving side. The latch 2-5 holds the STC counter value in accordance with the control signal from the header controller 2-4 and uses it as SCR information. This SCR information is added to the program stream 6 in a substantially constant cycle, and the cycle is a maximum of 0.7 seconds, but it is usually set to about 50 msec. P
The program stream 6 output from the S creation unit 2 is SC
The R header, the SCR information, the compressed data header, the compressed data information, and the like are repeated, and finally form a data group at 6.144 Mbps, for example.

The transmission section 3 generally uses a public telephone line network, and the usable transmission rate is often specified by the network side. Therefore, the transmission CK to the PS creator 2 is supplied from the transmission unit 3. Therefore, in general, the system CK
11 and the transmission CK12 for transmission have an asynchronous relationship, and FiF
When the memory 2-2 is about to underflow, the header controller 2-4 inserts padding data, which has no meaning in terms of content, into the program stream in place of the compressed data information to increase the transmission data. Note that the padding data header is naturally added prior to the insertion.

Next, the receiving side will be described. The PS analysis unit 4 includes a header analyzer 4-4, a FiFo memory 4-2,
The SCR extractor 4-6, the receiving side STC counter 4-3, the latch 4-5, and the VDEC 4-1 are included. What is VDEC?
Abbreviation for Video Decoder. Header analyzer 4-4, F
Write side of the iFo memory 4-2, SCR extractor 4-6
To the transmission CK13 (frequency 6.144 MHz) or a control signal generated by the transmission CK13.
The reading side of the FiFo memory 4-2, the receiving side STC counter 4-3, and the VDEC 4-1 have the receiving side system CK1.
6 (frequency 27 MHz) or a control signal generated by the system is supplied. The header analyzer 4-4 searches for each header in the program stream 7 and stores the information following the header in the FiFo memory 4-2 or S.
The control signal to be taken into the CR extractor 4-6 and the latch 4
The control signal EN for holding the value of the STC counter 4-3 on the receiving side at that time is output to -5. VDEC4-1
Decodes and reproduces the original image from the compressed data information of the FiFo memory 4-2. In addition, when compression processing has been applied,
Some deterioration of image quality will occur. The PS analyzer 4 also outputs the decoded reproduction image signal, the extracted SCR information 8, and the hold value 9 of the receiving side STC counter 4-3.

Next, the structure and operation of the VCO controller 5 will be described. The VCO controller 5 includes a difference detector 5-1 and an AMP5-
2 and LPF5-3. Difference detector 5-1
Compares the SCR information 8 with the hold value 9 of the receiving side STC counter, and outputs the analog error amount e corresponding to the difference. Then, the error amount e is AMP5-2 and L
Gain, offset, frequency characteristics, etc. are set to V with PF5-3.
It is converted into an output f adapted to the control range of CO15.
The VCO 15 operates to increase or decrease the output frequency according to the voltage of the control signal f. The VCO control unit 5 compares the STC counter value hold output 9 on the receiving side with the SCR information 8 which is the value of the SCR extractor 4-6, and controls the frequency of the receiving system CK16 so that the difference between the two becomes constant. . For example, when the SCR information 8 is larger than the reception side STC counter output 9, the VCO 15 is controlled so that the frequency of the system CK16 becomes high. Conversely, when the SCR information 8 is smaller than the hold value 9 of the STC counter on the receiving side, the VCO is set so that the frequency of the system CK16 becomes low.
Control 15.

By repeating these operations,
STC counter 4-3 on the receiving side and STC counter 2 on the transmitting side
In -3, the counting operation is continued while outputting almost the same value, and the frequencies of the receiving side system CK16 and the transmitting side system CK11 are also the same. In other words, the receiving side also has a clock that moves at the same tempo as the reference clock of the transmitting side. In addition to solving the above problems, this timepiece can also be used to realize a synchronous operation of video and audio when compressing and expanding them.

By the way, suppose that the receiving side system CK16
Described below is the problem when the frequencies of the receiving side system CK11 do not match. For example, the receiving system CK1
2 is 27.27 MHz, the frequency of the transmitting system CK11 is 27.00 MHz, and the receiving frequency is 1% higher. A moving image displays a fixed number of frame images per second, and if the number of frames per second is 27.00 MHz, the number of frames per frame is 27.27 MHz, which is 30.3 per second. Therefore, after 10 seconds, the PS creation unit 2 on the transmission side transmits only an image of 300 frames, but the PS analysis unit 4 on the reception side must output 303 frames, which causes a contradiction. That is, F which is the receiving side buffer of the PS analysis unit 4
The iFo memory 4-2 underflows and outputs incorrect data. Then, the VDEC 4-1 causes an adverse effect of reproducing an abnormal decoded image in accordance with the erroneous compressed data information.

Next, the relationship between the input and output of the VCO controller 5 will be shown. Here, {} in Expression 1 indicates that the digital value in {} is converted into an analog value. Also, Equation 2
G indicates the gain, and D indicates the offset value. Also, L
The frequency characteristic of PF5-3 is omitted, and the value after the steady state is used. e = A {SCR information 8-STC counter hold value 9} ………… (1) f = G × e + D …………………………………………………… (2) { When the digital value of the SCR information 8-STC counter hold value 9} is 0, the analog value of e is 0 V, and when the digital value is +1, the analog value of e is +1 m.
V, if the digital value is -1, it outputs -1 mV. It is assumed that G is 2, and D is set so that f becomes 2.5V when e = 0V. Note that e
The frequency of the receiving system CK at = 0 V, that is, f = 2.5 V will be referred to as the center frequency.

In the VCO 15, the control signal f is 2.
If it is 5V, CK of 27.000000MHz is output. Further, if the control signal f is 0.5V higher than 3.0V, the CK having a frequency higher than 27,000 270 MHz and +10 ppm is vice versa.
It outputs a system CK with a frequency of 6.999730 MHz and -10 ppm lower. When the frequency of the transmission side system CK11 is 27.000000 MHz, the frequency generated by the VCO 15 under the control of the transmission device of this system is finally 27.000000 MHz and the same as the transmission side system CK11. Become. That is, VCO15
To generate 27.000000 MHz, f is 2.
This is because it must be 5V, e is 0V, and the difference between {SCR information 8-STC counter hold value 9} is 0 in the end.

Next, consider a case where the frequency of the system CK11 on the transmitting side is deviated from 27.0270 MHz by +10 ppm. In this case, the frequency generated by the VCO 15 is 27.000 after reaching the final steady state.
Must be 270 MHz. Therefore, VC
In order for O15 to generate 27,000 270 MHz, f must be 3.0V and e is 0.25V,
After all, {SCR information 8-STC counter hold value 9}
Difference is 250. In other words, in this system, when the frequency of the system CK11 on the transmitting side and the center frequency of the system CK16 on the receiving side are deviated, in order to generate the control voltage f for correcting the frequency deviation, {S
The CR information 8-STC counter hold value 9} must have a deviation. As a result, the clocks on the transmitting side and the receiving side have time differences.

The problems caused by this deviation will be described below. In the case of compressed image data, several frames, for example, 15
The compression rate is a constant value in units of grouping into frames, but the compression rate varies from frame to frame in each moment. Below, a prediction image P consisting of only the difference information between the intra image I having the DC component information and the previous screen is shown.
The case of decoding and reproducing consecutive images from and will be described using specific numerical values. The order of image transmission is I, P,
P, P, I, P, P, and P are repeated. here,
Normally, the compression encoded data amount of the image I and the image P is about 3: 1, so 300 Kb /
For f and image P, the encoding amount of 100 Kb / f is 1/30
Occurs every second. 150 transmission capacity every 1/30 seconds
Kb / f, the image I is 2/30 seconds and the image P is 0.
It is transmitted in 6/30 seconds. In this way, compressed data is
It fluctuates instantaneously, but if we consider it over a 4-frame period, it is I, P, P, P, and 300 Kb / f + (10
0 Kb / f) x 3 total 600 Kb, the total capacity that can be transmitted during this is 600 Kb / f which is four times 150 Kb / f
Is the same as

In order to cope with the fluctuation of the compressed data, a FiFo memory is used as a buffer memory for temporary storage. The fluctuating compressed data is temporarily stored in the FiFo memory, and when the compressed data is accumulated to some extent, output is started at a constant speed to solve the problem. However, if the storage method here is insufficient, the output data will be exhausted during the period when the amount of generated compressed data is less than the extraction amount, that is, during the period of the image P. During the period of the image I whose generated amount exceeds the taken-out amount, the FiFo memory memory overflows and abnormal data is output in any case. This is a problem not only on the transmitting side but also on the receiving side. The reading of the data stored on the receiving side, that is, the start of decoding, avoids the above problem by giving an instruction from the transmitting side. Specifically, the reception side is instructed by inserting information about the time to start decoding into the program stream. To allow for this shift, an expensive F with a much larger storage capacity
Since the iFo memory is used and the VENC output is stored until transmission, a new problem arises in that the delay time from input to output increases in the transmission device as a whole.
Therefore, the STC counter, that is, the time difference between the transmitting side and the receiving side becomes a serious problem.

[0017]

In the above-mentioned prior art, there is a frequency deviation or frequency drift of the system CK11 on the transmission side, or a setting error or a variation when setting D in the above equation 2 by analog means. , Sending side ST
There is a drawback that the count values of the C counter 2-3 and the receiving side STC counter 4-3 are deviated. The present invention eliminates these drawbacks, and even if there is a frequency shift or drift of the system CK11 on the transmission side, or a setting error or fluctuation of D in the above equation 2, the STC counter 2-3 on the transmission side is present.
The purpose is to keep the count value of the STC counter 4-3 on the receiving side in a constant relationship.

[0018]

In order to achieve the above object, the present invention provides a voltage value generation for correcting a frequency shift and drift of the system CK11 on the transmission side as {SCR information 8-STC counter hold value. No. 9} is generated from another part, and its value is {SCR information 8-
It is changed according to the situation of the hold value 9} of the STC counter. FIG. 1 is a block diagram showing an overall configuration using a VCO controller 5B of the present invention. The PS creation unit 2, the transmission unit 3, and the PS analyzer 4 have the same operations as those described in the related art. In FIG. 1, the output e of the difference detector 5-1 is connected to the input terminal of the adder 5-4 and the input terminal IN of the integrator 5-5. Output terminal O of integrator 5-5
The output signal es from the UT is connected to the other input terminal of the adder 5-4. The output ec of the adder 5-4 is AM
It is connected to the input terminal of P5-2. Controller 5-
6, the SCR information 8 is input to the input terminal IN1 and the STC counter hold value 9 is input to IN2. Further, the EN signal 17 is input to the terminal ST. The control signal Ps from the output terminal Os is connected to the control terminal Sc terminal of the integrator 5-5.

Next, the operation of the present invention will be described.
The adder 5-4 outputs ec which is the result of adding the signals e and es applied to the two input terminals. Integrator 5
-5 is a terminal I when the control signal Ps is input to the Sc terminal.
The value of N1 is cumulatively added and output to the terminal OUT. The controller 5-6 outputs the control signal Ps once when the absolute value of the difference between the terminals IN1 and IN2 is larger than K for a certain number of times (M times). The controller 5-6 is
When the terminal ST is at the digital signal level and changes from "L" to "H", the operation including the above determination is performed once. A time chart of these operation examples is shown in FIG. As an initial condition,
M is 4 times, K is 50, output es of integrator 5-5 is 0V,
It is assumed that the transmission side system CK has a deviation of +10 ppm and {SCR information 8-STC counter hold value 9} is +110. After the first time, the {SCR information 8-STC counter hold value 9} shifts the control voltage f from 2.5 V to 3.0 V in order to shift the VCO 15 by +10 ppm. Therefore, the output e of the difference detector 5-1
Changes to 110, 240, 340, 420,
A total of 4 times, a value of 50 or more.

Therefore, the controller 5-6 outputs the Ps signal at the fifth time. As a result, the integrator 5-
5 is the output of the difference detector 5-1 e = + 0.42V
Is cumulatively added to the initial value of 0V and es is + 0.42V
Is output. After the fifth time, the {SCR information 8-STC counter hold value 9} is 210, 90, 110, 100.
And again, the value becomes 50 or more four times in total. Therefore, at the 9th time, the controller 5-6 again sets the P
The s signal is output. As a result, the integrator 5-5 cumulatively adds e = + 0.10 V, which is the output of the difference detector 5-1, and the integrated value +0.42 V up to the previous time, and adds + as es.
Outputs 0.52V. After the 9th time, {SCR information 8-
The STC counter hold value 9} is 50, 5, -2 because the VCO control voltage f becomes 3.02V and approaches the target.
The value changes from 0 to -10, and a value of 50 or more occurs only once in the four times this time. Therefore, the controller 5-
6 does not output the Ps signal. As a result, the integrator 5-
5 maintains + 0.52V output as es.

After that, since the {SCR information 8-STC counter hold value 9} only corrects a minute difference, it fluctuates only around 0, and the VCO controller 5 reaches a steady state. Even if the frequency of the transmission system CK11 deviates from the center value, the correction voltage corresponding to the frequency deviation of the transmission system CK11 is shared and output by the integrator 5-5, so e is almost 0, that is, {SCR. Information 8-STC
The counter hold value 9} is also almost 0. Therefore, the system CK of the transmission side STC counter 2-3 and the system CK of the reception side STC counter 4-3 match regardless of whether or not the frequency of the transmission side system CK11 deviates from the center value.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a controller 5-6 for realizing the present invention is shown below in FIG. Subtractor 5-6-
The SCR information 8 from the terminal IN1 is input to the + input of 1, and the STC counter hold value 9 from the terminal IN2 is input to the − input. The output of the subtractor 5-6-1 is input to the comparators 5-6-2 and 5-6-3. NOR5-6-
The output of the comparator 5-6-2 and the output of the comparator 5-6-3 are input to the circuit 4. FF (flip flop) 5-6
The output of NOR 5-6-4 is input to the D terminal of −5. The D terminal of FF5-6-6 receives the output of FF5-6-5, and the D terminal of FF5-6-7 receives FF5-6-6.
The output of is connected. The EN signal from the terminal ST is input to the CK terminals of the FFs 5-6-5 to 7. Each FF5
The outputs of -6-5 to 7 are further input to AND5-6-9. The EN signal is also input to AND5-6-9. The output of AND5-6-9 is connected to the Os terminal.

Next, this operation will be described. The subtractor 5-6-1 converts the SCR information 8 which is a digital value into S
The TC counter hold value 9 is subtracted, and the result is output as a digital value. The comparator 5-6-2 outputs the level "H" if the input digital value is K or more,
If it is less than K, level "L" is output. Comparator 5-6-
3 outputs a level "H" if the input digital value is -K or less, and outputs a level "L" if it is -K or more. The NOR 5-6-4 outputs "H" if any of the two inputs is the level "H". FF5-6-5-7
Takes in and outputs the digital level applied to the D terminal at the moment when the signal at the CK terminal changes from the level "L" to the level "H". The AND 5-6-9 outputs the level "H" as the signal Ps from the terminal Os when the levels of all the five input signals are "H". NOR5-6-4 is SC
If the difference between the R information 8 and the STC counter hold value 9 is within ± K, "H" is output. The EN signal to the terminal ST has a level "L" every time new SCR information is extracted.
→ Change from "H" to "L". FF5-6-5-7,
Whether or not the difference between the SCR information 8 for the past three times and the STC counter hold value 9 is within ± K is stored as levels “H” and “L”. AND5-6-9, if the results of the past three times and the current one time, four times in total, are "H", EN
The level "H" is output from the terminal Os as the signal Ps instructing the update of the integration during the period when the signal is "H" → "L".

FIG. 4 shows an embodiment for realizing the integrator 5-5. The terminal IN is connected to the input of the AD converter 5-5-1, and the output of the AD converter 5-5-1 is connected to the input of the level converter 5-5-5. Adder 5-
The output of the level converter 5-5-5 and the output of the FF 5-5-3 are connected to the two inputs of 5-2. Adder 5
The output of -5-2 is connected to FF5-5-3. FF5
The output of -5-3 is connected to the input of the DA converter 5-5-4. The terminal Sc is connected to the CK terminal of FF5-5-3. The output of the DA converter 5-5-4 is terminal O
Connected to UT. Next, the operation will be described. AD
The converter 5-5-1 converts the analog value e applied to the terminal IN into a parallel digital value and outputs it. The adder 5-5-2 displays the parallel digital output of the FF 5-5-3, which is a digital representation of the integration result up to the previous time, and the current e
FF5-
Output to the D terminal of 5-3. The FF 5-5-3 is updated to a new parallel digital value only when the Ps signal via the terminal Sc changes from "L" to "H", and the value is output. When the Ps signal does not change from “L” to “H” and remains “L”, the parallel digital value up to the previous time is output as it is without updating. The parallel digital output of the FF 5-5-3 is converted into the analog voltage es by the DA converter 5-5-4. Level converter 5-5-5
Is a multiplier that changes the relationship between the input and the output at a fixed ratio, where o = k × i, where i is the input and o is the output.
In the above description, k = 1.

V having a configuration different from that of the VCO controller 5B of FIG.
The CO control unit 5C is shown in FIG. The input terminal ST of the controller 5-7 is connected to the EN signal, and the output terminal Os is connected to the Sc terminal of the integrator 5-5. Controller 5-7
Outputs a signal Ps for performing integration when the EN signal is input a certain number of times. A time chart of this operation example is shown in FIG. The initial conditions are the same as in FIG. 2, M is four times,
K is 50, the output es of the integrator 5-5 is 0V, the transmission side system CK has a deviation of +10 ppm, and {SCR information 8-ST.
The C counter hold value 9} is assumed to be +110. 1
After the first time, the {SCR information 8-STC counter hold value 9} shifts the control voltage f from 2.5 V to 3.0 V in order to shift the VCO 15 by +10 ppm. Therefore, the output e of the difference detector 5-1 is 110,
The controller 5-7 outputs the Ps signal at the fifth time as it changes from 240 to 340 to 420. As a result, the integrator 5-5 cumulatively adds e = + 0.42V, which is the output of the difference detector 5-1, with the initial value of 0V, and outputs + 0.42V as es. After the fifth time, the {SCR information 8-STC counter hold value 9} is 210,9.
It changes from 0, 110, and 100, and the controller 5-7 outputs the Ps signal at the ninth time.

As a result, the integrator 5-5 cumulatively adds e = + 0.1V which is the output of the difference detector 5-1 and the integrated value up to the previous time + 0.42V, and outputs + 0.52V as es. . After the ninth time, the VCO control voltage f is 3.02 V in {SCR information 8-STC counter hold value 9}.
In order to approach the target, it changes to 50, 5, -20, -10, and the controller 5-7 outputs the Ps signal for the 13th time. As a result, the integrator 5-5 causes the difference detector 5
The output of −1, e = −0.10 V, and the integrated value up to the previous time, +0.52 V, are cumulatively added, and es is +0.42.
Output V. Since the subsequent {SCR information 8-STC counter hold value 9} only corrects a minute difference, it only fluctuates around 0, and the VCO control unit 5C
Almost steady state is reached. The VCO control unit 5 described above
In B and 5C, the LPF 5-3 is for adjusting the response characteristics and the like of the VCO 15, and is not essential. Further, although the difference detector 5-1 outputs the difference between the extracted SCR information 8 and the hold value 9 of the receiving side STC counter, which is input as a digital value, as an analog value e, each section has been described. Output with
Digital values are integrated, and at the input side to AMP5-2,
The same effect can be obtained with a configuration in which a DA converter converts the analog value.

[0027]

According to the present invention, the STC counters on the transmitting side and the receiving side are controlled to have a constant relationship regardless of the presence or absence of a deviation from the center value of the system CK frequency on the transmitting side and the magnitude of the deviation. It is possible to provide a transmission device capable of performing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a timing chart explaining the operation of the present invention.

FIG. 3 is a controller 5-of the VCO controller 5B of the present invention.
6 is a block diagram showing an example.

FIG. 4 is a block diagram showing an embodiment of an integrator 5-5 of the present invention.

FIG. 5 is a block diagram showing a configuration of a VCO control unit 5C of the present invention.

FIG. 6 is a timing chart showing the operation of the VCO controller 5C of the present invention.

FIG. 7 is a block diagram showing an entire conventional transmission device.

[Explanation of symbols]

1: Input video terminal, 2: PS creation unit, 2-3: transmission side STC counter, 3: transmission unit, 4: PS analysis unit, 4-
3: STC counter on receiving side, 4-6: SCR extractor,
5: VCO control unit, 5-1: difference detector, 5-2: AM
P, 5-3: LPF, 5-4: adder, 5-5: integrator, 5-5-1: AD converter, 5-5-2: adder, 5-5-3: FF (flip-flop ), 5-5
4: DA converter, 5-5-5: Level converter, 5-
6: controller, 5-6-1: subtractor, 5-6-2:
Comparator, 5-6-3: Comparator, 5-6-4: NOR, 5
-6-5 to 7: FF, 5-6-4: AND, 5-7: Controller, 8: Extracted SCR information, 9: Reception side STC counter hold output, 10: Output video terminal, 11: Transmission side system CK , 12: Transmission sending CK, 13: Transmission receiving CK, 14: Transmission side system CK generator, 15: VC
O, 16: Receiving system CK.

Claims (3)

(57) [Claims] 1. A program stream composed of header information, system clock reference (SCR) information and various data information is created from a source signal input in synchronization with a system clock on the transmitting side, and is transmitted in response to a transmission CK. A program stream creating section for outputting, a transmitting section for taking in the program stream synchronized with the transmission and sending clock, and outputting a program stream synchronized with the transmitting and receiving clock, and the input section for synchronizing with the transmitting and receiving clock The hold value at the time of extracting the SCR information extracted from the program stream and the receiving side system time clock (STC) counter operating at the receiving side system clock and the timing signal at the time of the extraction are output, Reproduced in synchronization with the system clock on the receiving side And a VCO control section for calculating and generating a control signal for controlling the receiving side system clock according to the difference between the SCR information and the hold value of the receiving side STC counter. In a transmission device having a VCO that varies the reception side system clock frequency according to the control signal, the VCO control unit cumulatively adds a value corresponding to the difference between the SCR information and the hold value of the reception side STC counter. A transmission device comprising means for performing. 2. The transmission device according to claim 1, wherein the VC is
As an O control unit, a difference detector that detects a difference between the SCR information and the hold value of the reception side STC counter, and a control signal that corresponds to a change in the difference between the SCR information and the hold value of the reception side STC counter are output. And a summing and adding means for summing and adding a value corresponding to the difference according to the control signal. 3. The transmission device according to claim 2, wherein the VC is
A transmission device characterized in that the cumulative addition means of the O control unit is controlled to cumulatively add a value corresponding to the difference at a predetermined cycle corresponding to the control signal.