JP3516887B2 - Noise shaping method and circuit - Google Patents
Noise shaping method and circuitInfo
- Publication number
- JP3516887B2 JP3516887B2 JP24482999A JP24482999A JP3516887B2 JP 3516887 B2 JP3516887 B2 JP 3516887B2 JP 24482999 A JP24482999 A JP 24482999A JP 24482999 A JP24482999 A JP 24482999A JP 3516887 B2 JP3516887 B2 JP 3516887B2
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- input
- coefficient
- signal
- integrator
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Description
【０００１】[0001]
【発明の属する技術分野】本発明はＤ／Ａ・Ａ／Ｄ変換
時に発生する量子化雑音を信号帯域外に強く分布させ、
信号帯域内の量子化雑音を小さくすることにより高精度
Ａ／Ｄ・Ｄ／Ａ変換器を得るノイズシェーピング回路の
高次数化に関するものである。BACKGROUND OF THE INVENTION The present invention distributes quantization noise generated during D / A / A / D conversion strongly outside the signal band,
The present invention relates to increasing the order of a noise shaping circuit that obtains a highly accurate A / D / D / A converter by reducing the quantization noise in the signal band.
【０００２】[0002]
【従来の技術】従来、入力から信号のフィードフォワー
ドパスを有するノイズシェーピング回路は「ノイズシェ
ーピング方法および回路：特許２６２１７２１」に示す
ように２次のループフィルタを１段で用いるのが基本で
あった。図４に「特許２６２１７２１」に示す従来回路
例を示す。入力を１０、出力を１１とし、入力１０に係
数ｋ０を乗じたものから遅延回路１９の出力を減算器１
４で減算し、その出力を積分器１２で積分する。積分器
１２の出力に係数ｋ４を乗じた結果から入力１０に係数
ｋ０を乗じたものにさらに係数ｋ３を乗じたものを減算
器１５で減算し、その出力を積分器１３で積分する。積
分器１３の出力に係数ｋ６を乗じた信号と積分器１２の
出力に係数ｋ５を乗じた信号とを加算器１６で加算しそ
の出力を量子化器１８に入力する。量子化器１８の出力
を出力１１とするとともに、遅延回路１９の入力とする
構成となっている。2. Description of the Related Art Conventionally, a noise shaping circuit having a feed forward path of a signal from an input basically uses a second-order loop filter in one stage as shown in "Noise shaping method and circuit: Japanese Patent No. 2621721". . FIG. 4 shows an example of a conventional circuit shown in "Patent 2621721". The input of 10 and the output are 11, the output of the delay circuit 19 is subtracted from the input 10 multiplied by the coefficient k0.
4 is subtracted, and the output is integrated by the integrator 12. From the result of multiplying the output of the integrator 12 by the coefficient k4, the one obtained by multiplying the input 10 by the coefficient k0 and further by the coefficient k3 is subtracted by the subtractor 15, and the output is integrated by the integrator 13. A signal obtained by multiplying the output of the integrator 13 by the coefficient k6 and a signal obtained by multiplying the output of the integrator 12 by the coefficient k5 are added by the adder 16, and the output is input to the quantizer 18. The output of the quantizer 18 is used as the output 11 and the input of the delay circuit 19 is used.
【０００３】この回路でｋ０＝Ｋ３＝ｋ４＝ｋ５＝ｋ６
＝１．０、Ｙ：出力、Ｘ：入力、Ｑ：量子化雑音とし、
ｚを遅延量とすると２次△−Σ回路と全く同一の（数
１）式で示されるノイズシェーピング特性が得られ、か
つループ安定度は係数ｋ３を有するパスにより位相遅れ
が改善されるため２次△−Σ回路より向上する。In this circuit, k0 = K3 = k4 = k5 = k6
= 1.0, Y: output, X: input, Q: quantization noise,
When z is the delay amount, the noise shaping characteristic expressed by the equation (1), which is exactly the same as that of the second-order Δ-Σ circuit, is obtained, and the loop stability is improved because the phase delay is improved by the path having the coefficient k3. It is improved from the next Δ-Σ circuit.
【０００４】
Ｙ＝Ｘ＋(１−ｚ-1)2Ｑ （数１）
図５は図４の従来例を３次以上の高次ノイズシェーピン
グ特性にする従来回路構成であり「ＣＭＯＳアナログ回
路設計技術、ｐｐ１１３：（株）トリケプス」に記載さ
れている例である。図４において積分器を直列にＮ段接
続し、各積分器出力に各々ａ1からａk-1の係数を乗算し
たものを全て加算器１７で加算する構成となっている。
図６は３次ノイズシェーピング特性を得る例である。本
回路の特性は（数２）式となり量子化雑音Ｑに３次のノ
イズシェーピング特性がかかることが判る。Y = X + (1−z −1 ) 2 Q (Equation 1) FIG. 5 shows a conventional circuit configuration in which the conventional example of FIG. , Pp113: Tri-Ceps Co., Ltd. ”. In FIG. 4, N stages of integrators are connected in series, and the adder 17 adds all the outputs of the integrators multiplied by the coefficients a 1 to a k−1 .
FIG. 6 is an example of obtaining the third-order noise shaping characteristic. The characteristic of this circuit is given by the equation (2), and it can be seen that the quantization noise Q has a third-order noise shaping characteristic.
【０００５】
Y = a0X+(1-z-1)3Q/[(1-z-1)2+a2(1-z-1)z-1+a3z-1] （数２）
しかし、このような積分器を直接に直列接続する方式で
は、積分器での９０°位相遅れの積み重なりによりルー
プが不安定になるため、ループを安定化させるための係
数の設計が難しいという欠点があった。Y = a 0 X + (1-z -1 ) 3 Q / [(1-z -1 ) 2 + a 2 (1-z -1 ) z -1 + a 3 z -1 ] (Equation 2 However, in the method of directly connecting such integrators in series, the loop becomes unstable due to the stacking of 90 ° phase delays in the integrator, which makes it difficult to design the coefficient for stabilizing the loop. was there.
【０００６】[0006]
【発明が解決しようとする課題】以上説明したように、
従来のノイズシェーピング回路では安定性を考慮すると
ノイズシェーピング特性に限界があり、高次のノイズシ
ェーピング回路の実現が困難であった。本発明において
は上記の従来回路の欠点に鑑み、安定性が高く、係数設
計の簡易な高次ノイズシェーピング回路の実現を目的と
するものである。As described above,
In the conventional noise shaping circuit, considering stability, the noise shaping characteristic is limited, and it is difficult to realize a high-order noise shaping circuit. In view of the above-mentioned drawbacks of the conventional circuit, the present invention aims to realize a high-order noise shaping circuit having high stability and simple coefficient design.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明においては以下の手段を規定した。In order to achieve the above object, the following means are defined in the present invention.
【０００８】すなわち、請求項１においては、入力信号
に第１の係数を乗じた第１の信号から、量子化器出力信
号に１サンプリング時間の遅延を与えさらに第２の係数
を乗じた遅延信号を減算して得られる第２の信号を、第
１の積分器に入力することにより該第２の信号を積分
し、該第１の積分器の出力である第３の信号に第３の係
数を乗じた第４の信号から、該第１の信号にさらに第４
の係数を乗じた第６の信号を減算して第７の信号とし、
該第７の信号を第２の積分器に入力して積分し第８の信
号を得、該第１の積分器の出力に第５の係数を乗じた第
９の信号と第２の積分器の出力に第６の係数を乗じて得
られた第１０の信号とを加算した第１１の信号を出力と
する２次のループフィルタブロックを第１の２次ループ
フィルタブロックとし、この第１の２次ループフィルタ
ブロックと同一構成で、係数値が全て同一または異なる
さらには一部同一または異なるＮ個の２次ループフィル
タブロックを直列に接続し、最終段ブロックの出力と、
最終段のブロックを除く各２次ループフィルタブロック
の全ての積分器の出力に所定の係数をそれぞれ乗じた結
果とを加算し、該加算結果を量子化器に入力し、この量
子化器の出力信号を必要とする最終出力信号とする方法
を規定したものである。なお、上記の各係数値は０以上
１以下で、同じ値かまたは異なる値をとるものとする。
但し、これら係数値全てが同じ値を採ることもあるが、
場合によっては必ずしも同じ値をとるとは限らず、また
同時に全てが０となることもない。That is, according to the first aspect of the present invention, the delay signal obtained by delaying the quantizer output signal by one sampling time from the first signal obtained by multiplying the input signal by the first coefficient and further multiplying by the second coefficient is given. Is input to the first integrator to integrate the second signal, and the third signal, which is the output of the first integrator, has the third coefficient From the fourth signal multiplied by
The sixth signal multiplied by the coefficient is subtracted to obtain the seventh signal,
The seventh signal is input to the second integrator to be integrated to obtain the eighth signal, and the output of the first integrator is multiplied by the fifth coefficient to obtain a ninth signal and a second integrator. The second-order loop filter block that outputs the eleventh signal obtained by adding the tenth signal obtained by multiplying the output of the above by the sixth coefficient is used as the first second-order loop filter block. The same configuration as the second-order loop filter block, all of the coefficient values being the same or different, or partially the same or different, are connected in series, and the output of the final stage block is
Binding obtained by multiplying each of the predetermined coefficient to the output of all the integrators of the second order loop filter blocks except the block in the last stage
It defines a method of adding the result and the result , inputting the addition result to a quantizer, and making the output signal of this quantizer the required final output signal. The coefficient values are 0 or more and 1 or less, and have the same value or different values.
However, although all of these coefficient values may take the same value,
In some cases, they do not always take the same value, and all do not become 0 at the same time.
【０００９】請求項２においては、入力端子に第１の係
数器が接続され、該第１の係数器出力は第１の減算器の
一方の入力に接続され、該第１の減算器の他の一方の入
力端子には遅延回路の出力が第２の係数器を介して接続
され、該第１の減算器の出力は第１の積分器の入力に接
続され、該第１の積分器の出力は第３の係数器を介して
第２の減算器の一方の入力に接続され、該第２の減算器
の他の一方の入力には該第１の係数器出力が第４の係数
器を介して接続され、該第２の減算器の出力は第２の積
分器の入力に接続され、該第２の積分器の出力は第５の
係数器を介して第１の加算器の一方の入力に接続され、
該第１の加算器の他の一方の入力には該第１の積分器出
力が第６の係数器を介して接続されることにより第１の
２次ループフィルタブロックを形成し、該第１の加算器
の出力を第７の係数器を介して該２次ループフィルタブ
ロックと同一構成で、係数値が同一または異なるさらに
は一部同一または異なるＮ個の２次ループフィルタブロ
ックの入力に接続し、これら２次ループフィルタブロッ
クをＮ個直列に接続し、最終段のブロックを除く各２次
ループフィルタブロックに含まれる全ての積分器の出力
は所定の係数値を有する係数器を介して最終段のブロッ
クの出力と共に第２の加算器の入力に接続され、該第２
の加算器の出力は量子化器の入力に接続され、該量子化
器の出力は該遅延回路の入力に接続され、該遅延回路の
出力は該第１の２次ループフィルタブロックにおける該
第１の減算器と同様に各２次ループフィルタブロックの
入力側に配置された減算器の信号入力とは異なる他の一
方の入力に第９０乃至第９Ｎの係数器を介してそれぞれ
接続され、同時に該量子化器の出力を出力信号として送
出する構成である回路について規定している。In the present invention, the first coefficient unit is connected to the input terminal, the output of the first coefficient unit is connected to one input of the first subtractor, and the other of the first subtractor is connected. The output of the delay circuit is connected to one of the input terminals via the second coefficient unit, and the output of the first subtractor is connected to the input of the first integrator. The output is connected to one input of the second subtractor through the third coefficient unit, and the first coefficient unit output is connected to the other input of the second subtractor by the fourth coefficient unit. And the output of the second subtractor is connected to the input of the second integrator, and the output of the second integrator is connected to the input of the first adder via the fifth coefficient unit. Connected to the input of
The first integrator output is connected to the other one input of the first adder through a sixth coefficient unit to form a first second-order loop filter block, and the first second-order loop filter block is formed. The output of the adder is connected to the inputs of N second-order loop filter blocks having the same configuration as the second-order loop filter block through the seventh coefficient unit and having the same or different coefficient values or partially the same or different coefficient values. Then, N pieces of these secondary loop filter blocks are connected in series, and the outputs of all integrators included in each secondary loop filter block except the final stage block are finalized through a coefficient unit having a predetermined coefficient value. Stepped block
Connected to the input of the second adder together with the output of
The output of the adder of is connected to the input of the quantizer, the output of the quantizer is connected to the input of the delay circuit, and the output of the delay circuit is connected to the first of the first second-order loop filter block. Similar to the subtractor of the second-order loop filter block, it is connected to the other input different from the signal input of the subtractor arranged on the input side of each second-order loop filter block through the 90th to 9Nth coefficient units, and at the same time, It specifies a circuit that is configured to send the output of the quantizer as an output signal.
【００１０】請求項３においては、上記の請求項２に記
載のノイズシェーピング回路において、前記２段目以降
の２次ループフイルタブロックにおける前記第１及び第
２の二つの積分器の間に配置された前記減算器の一方の
入力として上記前段の前記第２の積分器出力に第８の係
数を乗じた信号を使用し、他の一方の減算器入力には直
前の積分器出力に第９の係数を乗じた信号を使用する方
法について規定している。[0010] In the third aspect, in the noise shaping circuit according to claim 2 above, wherein the first and the second loop filter block of the second stage and thereafter
Using the signal multiplied by the eighth coefficient of said second integrator output of the preceding stage as one input of which is disposed between the second two integrators the subtractor, the other one of the subtractor input Direct to
How to use the pre-signal multiplied by the coefficient of the ninth to the integrator output
It stipulates the law .
【００１１】請求項４においては、請求項２に記載のノ
イズシェーピング回路において、前記２段目以降の２次
ループフイルタブロックにおける前記第１及び第２の二
つの積分器の間に配置された前記減算器の一方の入力に
は、前段の２次ループフィルタブロックにおける前記第
２の積分器出力が第８の係数器を介して接続されてお
り、他の一方の前記減算器入力は第９の係数器を介して
直前の積分器出力に接続されている回路としている。[0011] In the fourth aspect, in the noise shaping circuit according to claim 2, disposed between the first and second of the two integrators in the secondary loop filter block of the second stage and thereafter the To one input of the subtractor
Is our second integrator output before SL in front of the second order loop filter block is connected through the coefficient unit of the eighth
And the other one of the subtractor inputs is connected through a ninth coefficient unit.
The circuit is connected to the output of the immediately preceding integrator .
【００１２】[0012]
【発明の実施の形態】図１に本発明による第１の実施の
形態を示す。すなわち、その構成は２次のループフィル
タ回路を多段に直列接続するものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment according to the present invention. That is, the configuration is such that secondary loop filter circuits are connected in series in multiple stages.
【００１３】１段当たりの２次ループフィルタ回路の構
成は図１の破線で囲まれた部分Ａに示すように、入力を
１０、出力を１１、量子化器を１８、遅延回路を１９と
したとき、以下のように構成される。入力１０に係数ｋ
０を乗じたものから遅延回路１９の出力に係数ｋ１２を
乗じたものを減算器１４で減算し、その出力を積分器１
２で積分する。積分器１２の出力に係数ｋ４を乗じて入
力１０に係数ｋ０を乗じたものにさらに係数ｋ３を乗じ
たものを減算器１５で減算し、その出力を積分器１３で
積分する。積分器１３の出力に係数ｋ６を乗じた信号と
積分器１２の出力に係数ｋ５を乗じた信号を加算器１６
で加算しその出力に係数ｋ１１を乗じたものを次段の入
力とすることにより１ブロックを構成しているものであ
る。As shown in a portion A surrounded by a broken line in FIG. 1, the configuration of the second-order loop filter circuit for each stage has 10 inputs, 11 outputs, 18 quantizers, and 19 delay circuits. Then, it is configured as follows. Input 10 with coefficient k
The product of 0 and the product of the output of the delay circuit 19 multiplied by the coefficient k12 are subtracted by the subtractor 14, and the output is integrated by the integrator 1.
Integrate with 2. The output of the integrator 12 is multiplied by the coefficient k4, the input 10 is multiplied by the coefficient k0, and the product of the coefficient k3 is subtracted by the subtractor 15, and the output is integrated by the integrator 13. The signal obtained by multiplying the output of the integrator 13 by the coefficient k6 and the signal obtained by multiplying the output of the integrator 12 by the coefficient k5 are added by the adder 16
1 and the output is multiplied by a coefficient k11 to be used as the input of the next stage to form one block.
【００１４】この２次ループフィルタブロックをＺ段直
列し、最終段ブロックの出力に最終段ブロック以外の２
次ループフィルタブロック回路の積分器出力に各々係数
を乗じて加算器１７で加算したものを量子化器１８の入
力とし、量子化器１８の出力を出力１１とするととも
に、遅延回路１９の入力とする回路構成となっている。
本実施の形態の具体的な例としてループフィルタを２段
直列接続した４次のノイズシェーピング次数を得る回路
構成の例を図２に示す。This second-order loop filter block is connected in Z stages in series, and the output of the final stage block is set to 2 except the final stage block.
The integrator output of the next loop filter block circuit is multiplied by each coefficient and added by the adder 17 to be the input of the quantizer 18, the output of the quantizer 18 being the output 11, and the input of the delay circuit 19 It has a circuit configuration.
As a specific example of the present embodiment, FIG. 2 shows an example of a circuit configuration for obtaining a fourth-order noise shaping order in which two stages of loop filters are connected in series.
【００１５】図２の回路において、ブロックＢは上記の
ブロックＡと同じ回路構成で、ブロックＡにおける係数
器ｋ０はブロックＢにおいては係数器ｋ１１、減算器１
４は減算器２４、積分器１２は積分器２２、係数器ｋ３
は係数器ｋ７、係数器ｋ４は係数器ｋ８、係数器ｋ５は
係数器ｋ９、減算器１５は減算器２５、積分器１３は積
分器２３、係数器ｋ６は係数器ｋ１０、係数器ｋ１２は
係数器ｋ１３、加算器１６は加算器２６にそれぞれ対応
している。ここで、係数器に関しては１以下で０以上の
値を目的に応じた条件を満たすように係数器ｋ０からｋ
１３に対して設定することにより、安定な４次ノイズシ
ェーピング特性を得ることが可能となる。この場合、係
数値全てが同時に０の値となることがないことはもち論
である。なお、図２において、加算器１７としては図１
に示すように２入力以上の多入力加算器の使用も可能で
あるが、図２に示すように２入力加算器を複数個直列接
続することによっても同様の結果が得られることは勿論
である。In the circuit of FIG. 2, the block B has the same circuit configuration as the above block A, and the coefficient unit k0 in the block A is the coefficient unit k11 and the subtracter 1 in the block B.
4 is a subtractor 24, integrator 12 is an integrator 22, and coefficient unit k3
Is coefficient unit k7, coefficient unit k4 is coefficient unit k8, coefficient unit k5 is coefficient unit k9, subtractor 15 is subtractor 25, integrator 13 is integrator 23, coefficient unit k6 is coefficient unit k10, and coefficient unit k12 is coefficient. The adder k13 and the adder 16 correspond to the adder 26, respectively. Here, regarding the coefficient units, values of 1 or less and 0 or more are set so that the coefficient units k0 to k can satisfy the condition according to the purpose.
Setting to 13 makes it possible to obtain stable fourth-order noise shaping characteristics. In this case, it is a matter of course that not all coefficient values are 0 at the same time. Note that in FIG. 2, the adder 17 shown in FIG.
Although it is possible to use a multi-input adder having two or more inputs as shown in FIG. 2, it is needless to say that the same result can be obtained by connecting a plurality of two-input adders in series as shown in FIG. .
【００１６】図３は本発明における第２の実施の形態を
示すもので、４次ノイズシェーピング特性を得る場合の
回路構成を示したものである。基本構成に関しては図２
に示した回路と同一であるが、図２では加算器１６の出
力に係数ｋ１１を乗じたものを次段ブロックの入力側の
係数、すなわち初段ブロックにおける係数ｋ０に相当す
る次段ブロックの係数器入力としていたが、本第２の実
施の形態では初段ブロックの積分器１３の出力を係数ｋ
７の入力とし、この係数ｋ７を乗じた結果を次段の２次
ループフィルタブロックの第２の減算器２５の一方の端
子に入力するものであり、その動作等は図２の回路と全
く同一である。また、図３の回路において、係数ｋ７を
乗算する信号を積分器１３の出力から直接ではなく、積
分器１３の出力に係数ｋ６を乗算した結果にさらに係数
ｋ７を乗算する構成としても同様の結果を得ることが出
来る。FIG. 3 shows a second embodiment of the present invention and shows a circuit configuration for obtaining a fourth-order noise shaping characteristic. Figure 2 for the basic configuration
2 is the same as that of the circuit shown in FIG. 2, but in FIG. Although the input is used, in the second embodiment, the output of the integrator 13 in the first stage block is set to the coefficient k.
7 and the result of multiplication by this coefficient k7 is input to one terminal of the second subtractor 25 of the secondary loop filter block of the next stage, and its operation and the like are exactly the same as those of the circuit of FIG. Is. Further, in the circuit of FIG. 3, the same result can be obtained even if the signal for multiplying the coefficient k7 is not directly output from the output of the integrator 13 but the result of multiplying the output of the integrator 13 by the coefficient k6 is further multiplied by the coefficient k7. Can be obtained.
【００１７】なお、図１および図３の回路において量子
化器１８をＡ／Ｄ変換器、遅延回路１９をＤ／Ａ変換器
とするとノイズシェーピングＡ／Ｄ変換器とすることが
できる。In the circuits of FIGS. 1 and 3, if the quantizer 18 is an A / D converter and the delay circuit 19 is a D / A converter, a noise shaping A / D converter can be obtained.
【００１８】[0018]
【発明の効果】本回路は積分器２個毎に出力の負帰還パ
スが入るため図５に示す従来回路と比べ安定に高次のノ
イズシェーピング特性が得られ、かつ同一構成の２次ル
ープフィルタ回路を繰り返し直列接続することからＬＳ
Ｉ化する場合にレイアウトを簡易化することが可能とな
る特徴を有している。In this circuit, since a negative feedback path of the output is provided for every two integrators, higher-order noise shaping characteristics can be obtained more stably than the conventional circuit shown in FIG. Since the circuits are repeatedly connected in series, LS
It has a feature that the layout can be simplified when converting to I.
【図１】本発明における第１の実施の形態を示す回路構
成図。FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.
【図２】上記第１の実施の形態の変形を２次の場合につ
いて示した回路構成図。FIG. 2 is a circuit configuration diagram showing a modification of the first embodiment for a secondary case.
【図３】本発明における第２の実施の形態を示す回路構
成図。FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention.
【図４】従来公知のノイズシェーピング基本回路の構成
図。FIG. 4 is a configuration diagram of a conventionally known noise shaping basic circuit.
【図５】従来公知の高次の接続によるノイズシェーピン
グ回路の構成図。FIG. 5 is a configuration diagram of a conventionally known noise shaping circuit by a high-order connection.
【図６】図５の回路を３次のフィルタに適用した場合の
等価回路図。6 is an equivalent circuit diagram when the circuit of FIG. 5 is applied to a third-order filter.
１０：入力 １１：出力 １２：積分器 １３：積分器 １４：減算器 １５：減算器 １６：加算器 １７：加算器 １８：量子化器 １９：遅延回路 ２２：積分器 ２３：減算器 ２４：減算器 ２５：減算器 ２６：加算器 ２７：加算器 ２７：加算器 ２８：加算器 ５１：減算器 ５２：積分器 ５３：減算器 ５ｎ：積分器 ａｉ（ｉ＝０〜ｋ）：系数器 ｋｉ（ｉ＝０〜ｚ）：系数器 10: Input 11: Output 12: integrator 13: integrator 14: Subtractor 15: Subtractor 16: Adder 17: Adder 18: Quantizer 19: Delay circuit 22: integrator 23: subtractor 24: Subtractor 25: Subtractor 26: Adder 27: Adder 27: Adder 28: Adder 51: Subtractor 52: Integrator 53: Subtractor 5n: Integrator ai (i = 0 to k): coefficient multiplier ki (i = 0 to z): coefficient multiplier
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H03M 3/02 H03M 1/08 H03M 7/36 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H03M 3/02 H03M 1/08 H03M 7/36
Claims (4)
から、量子化器出力信号に１サンプリング時間の遅延を
与えさらに第２の係数を乗じた遅延信号を減算して得ら
れる第２の信号を、第１の積分器に入力することにより
該第２の信号を積分し、該第１の積分器の出力である第
３の信号に第３の係数を乗じた第４の信号から、該第１
の信号にさらに第４の係数を乗じた第６の信号を減算し
て第７の信号とし、該第７の信号を第２の積分器に入力
して積分し第８の信号を得、該第１の積分器の出力に第
５の係数を乗じた第９の信号と第２の積分器の出力に第
６の係数を乗じて得られた第１０の信号とを加算した第
１１の信号を出力とする２次のループフィルタブロック
を第１の２次ループフィルタブロックとし、該第１の２
次ループフィルタブロックと同一構成で、係数値が同一
または異なるＮ個の２次ループフィルタブロックを直列
に接続し、最終段ブロックの出力と、最終段のブロック
を除く各２次ループフィルタブロックの全ての積分器の
出力に所定の係数をそれぞれ乗じた結果とを加算し、該
加算結果を量子化器に入力し、該量子化器の出力を最終
の出力信号とすることを特徴とするノイズシェーピング
方法。1. A delay signal obtained by delaying a quantizer output signal by one sampling time and further subtracting a delayed signal obtained by multiplying a second coefficient from a first signal obtained by multiplying an input signal by a first coefficient. The second signal is input to the first integrator to integrate the second signal, and the third signal, which is the output of the first integrator, is multiplied by a third coefficient to obtain a fourth signal. From the signal, the first
Signal is further subtracted by a sixth signal to obtain a seventh signal, the seventh signal is input to a second integrator and integrated to obtain an eighth signal, first integrator 9 multiplied by the fifth coefficient to the output of the signal and the eleventh signal obtained by adding the 10th signal obtained by multiplying a sixth coefficient of the output of the second integrator The second-order loop filter block that outputs
N secondary loop filter blocks having the same configuration as the next loop filter block and having the same or different coefficient values are connected in series, and the output of the final stage block and all the secondary loop filter blocks except the final stage block The result of multiplying the output of the integrator of
A noise shaping method, wherein an addition result is input to a quantizer, and an output of the quantizer is used as a final output signal.
１の係数器出力は第１の減算器の一方の入力に接続さ
れ、該第１の減算器の他の一方の入力端子には遅延回路
の出力が第２の係数器を介して接続され、該第１の減算
器の出力は第１の積分器の入力に接続され、該第１の積
分器の出力は第３の係数器を介して第２の減算器の一方
の入力に接続され、該第２の減算器の他の一方の入力に
は該第１の係数器出力が第４の係数器を介して接続さ
れ、該第２の減算器の出力は第２の積分器の入力に接続
され、該第２の積分器の出力は第６の係数器を介して第
１の加算器の一方の入力に接続され、該第１の加算器の
他の一方の入力には該第１の積分器出力が第５の係数器
を介して接続されることにより第１の２次ループフィル
タブロックを形成し、該第１の加算器の出力を第７の係
数器を介して該２次ループフィルタブロックと同一構成
で、係数値が同一または異なるＮ個の２次ループフィル
タブロックの入力に接続し、これら２次ループフィルタ
ブロックをＮ個直列に接続し、最終段のブロックを除く
各２次ループフィルタブロックに含まれる全ての積分器
の出力は所定の係数値を有する係数器を介して最終段の
ブロックの出力と共に第２の加算器の入力に接続され、
該第２の加算器の出力は量子化器の入力に接続され、該
量子化器の出力は該遅延回路の入力に接続され、該遅延
回路の出力は該第１の２次ループフィルタブロックにお
ける該第１の減算器と同様に各２次ループフィルタブロ
ックの入力側に配置された減算器の信号入力とは異なる
他の一方の入力に第９０乃至第９Ｎの係数器を介してそ
れぞれ接続され、同時に該量子化器の出力を出力信号と
して送出する構成であることを特徴とするノイズシェー
ピング回路。2. A first coefficient unit is connected to an input terminal, the output of the first coefficient unit is connected to one input of the first subtractor, and the other input of the first subtractor is connected. The output of the delay circuit is connected to the terminal via the second coefficient unit, the output of the first subtractor is connected to the input of the first integrator, and the output of the first integrator is the third Is connected to one input of the second subtractor via the coefficient unit of the second subtractor, and the output of the first coefficient unit is connected to the other input of the second subtractor via the fourth coefficient unit. The output of the second subtractor is connected to the input of the second integrator, and the output of the second integrator is connected to one input of the first adder via the sixth coefficient multiplier. is, in addition to one input of the first adder to form a first secondary loop filter block by the integrator output of the first is connected via a fifth coefficient unit, The output of the first adder is connected through a seventh coefficient unit to the inputs of N secondary loop filter blocks having the same configuration as the secondary loop filter block and having the same or different coefficient values. N loop filter blocks are connected in series, and the outputs of all integrators included in each secondary loop filter block except the final stage block are output from the final stage through a coefficient unit having a predetermined coefficient value .
Connected to the input of the second adder with the output of the block ,
The output of the second adder is connected to the input of the quantizer, the output of the quantizer is connected to the input of the delay circuit, and the output of the delay circuit is in the first second-order loop filter block. Similar to the first subtractor, the other one of the inputs different from the signal input of the subtractor arranged on the input side of each secondary loop filter block is connected via the 90th to 9Nth coefficient units, respectively. And a noise shaping circuit characterized in that the output of the quantizer is sent out as an output signal at the same time.
において、前記２段目以降の２次ループフイルタブロッ
クにおける前記第１及び第２の二つの積分器の間に配置
された前記減算器の一方の入力として前記前段の第２の
積分器出力に第８の係数を乗じた信号を使用し、他の一
方の減算器入力には直前の積分器出力に第９の係数を乗
じた信号を使用することを特徴とするノイズシェーピン
グ方法。3. A noise shaping method according to claim 1, wherein one of the subtractor disposed between said first and second two integrators in the secondary loop filter block of the second stage and thereafter using the second signal multiplied by the coefficient of the eighth to the integrator output of the previous SL front as the input, the other one
Multiply the output of the previous integrator by the ninth coefficient to the input of the other subtractor.
A noise shaping method characterized in that the same signal is used.
において、前記２段目以降の２次ループフイルタブロッ
クにおける前記第１及び第２の二つの積分器の間に配置
された前記減算器の一方の入力には、前段の２次ループ
フィルタブロックにおける前記第２の積分器出力が第８
の係数器を介して接続され、他の一方の前記減算器入力
は第９の係数器を介して直前の積分器出力に接続されて
いることを特徴とするノイズシェーピング回路。4. A noise shaping circuit according to claim 2, wherein one of the subtractor disposed between said first and second two integrators in the secondary loop filter block of the second stage and thereafter The input of is the secondary loop of the previous stage
The second integrator output before SL in the filter block 8
Of the other subtractor input connected through the coefficient multiplier of
Is connected to the output of the immediately previous integrator via a ninth coefficient multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24482999A JP3516887B2 (en) | 1999-08-31 | 1999-08-31 | Noise shaping method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24482999A JP3516887B2 (en) | 1999-08-31 | 1999-08-31 | Noise shaping method and circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001069009A JP2001069009A (en) | 2001-03-16 |
| JP3516887B2 true JP3516887B2 (en) | 2004-04-05 |
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ID=17124583
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24482999A Expired - Lifetime JP3516887B2 (en) | 1999-08-31 | 1999-08-31 | Noise shaping method and circuit |
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| Country | Link |
|---|---|
| JP (1) | JP3516887B2 (en) |
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|---|---|---|---|---|
| US6400297B1 (en) * | 2001-04-26 | 2002-06-04 | Cirrus Logic, Inc. | Method and system for operating two or more integrators with different power supplies for an analog-to-digital delta-sigma modulator |
| US8665128B2 (en) * | 2010-12-08 | 2014-03-04 | National Semiconductor Corporation | Sigma-delta difference-of-squares log-RMS to DC converter with forward path multiplier and chopper stabilization |
| US8665126B2 (en) * | 2010-12-08 | 2014-03-04 | National Semiconductor Corporation | ΣΔ difference-of-squares LOG-RMS to DC converter with forward and feedback paths signal squaring |
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| Publication number | Publication date |
|---|---|
| JP2001069009A (en) | 2001-03-16 |
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