CN101145786B - Using an integrating circuit sharing a triangular configuration and related method - Google Patents

Using an integrating circuit sharing a triangular configuration and related method Download PDF

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CN101145786B
CN101145786B CN 200610127485 CN200610127485A CN101145786B CN 101145786 B CN101145786 B CN 101145786B CN 200610127485 CN200610127485 CN 200610127485 CN 200610127485 A CN200610127485 A CN 200610127485A CN 101145786 B CN101145786 B CN 101145786B
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CN 200610127485
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CN101145786A (en )
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简弘伦
高得畲
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普诚科技股份有限公司
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Abstract

一种使用分时结构的积分三角电路包含一系数产生单元、一积分三角处理单元以及一存储单元。 Sharing structure using a delta-sigma circuit comprises a coefficient generating unit, a processing unit and a delta-sigma memory unit. 该系数产生单元用来产生积分三角运算的系数。 The coefficient generating means for generating a delta-sigma factor calculation. 该积分三角处理单元用来根据该系数产生单元所产生的积分三角运算的系数,执行积分三角运算。 The integration processing unit triangular cam means for integrating coefficient generated based on the coefficients generated in operation, integration is performed trigonometric. 该存储单元用来存储该积分三角处理单元的积分三角运算结果。 The storage unit for storing the delta-sigma sigma-delta calculation result processing unit. 其中,该积分三角电路用来通过该系数产生单元、该积分三角处理单元及该存储单元,执行多阶的积分三角运算。 Wherein the sigma-delta circuit through the means for generating the coefficient, the sigma-delta processing unit and the memory unit, performs a multi-order delta-sigma calculation.

Description

使用分时结构的积分三角电路及其相关方法 Using an integrating circuit sharing a triangular configuration and related method

技术领域 FIELD

[0001] 本发明提供一种积分三角电路(Sigma-Delta Circuit)及其方法,尤其指一种使用分时结构的积分三角电路及其方法。 [0001] The present invention provides a delta-sigma circuit (Sigma-Delta Circuit) and its method, particularly to a sigma-delta circuit and a method using a time division structure.

背景技术 Background technique

[0002] 目前的音频处理,多使用CPU(中央处理器,Central Processing Unit)或者DSP(数字信号处理器,Digital Signal Processor)等通用型处理器来实现,另一种方法,则是于FPGA (场式可编程逻辑门阵列,Fie 1 dProgrammabIe Gate Array)上实现, 由于积分三角调制器的操作频率范围低,可以很容易于FPGA上实现。 [0002] It audio processing, multi-use CPU (central processing unit, Central Processing Unit) or a DSP (digital signal processor, Digital Signal Processor) and the like general-purpose processors to implement, another method is to FPGA ( field programmable gate array, Fie 1 dProgrammabIe gate array implemented on), due to the low operating frequency range of the sigma-delta modulator, it can be easily achieved in on the FPGA. 积分三角调制器(Sigma-Delta Modulator)已被广泛地运用在模数转换器(A/D Converter)以及数模转换器(D/AConverter)上,主要因为积分三角调制器具有噪声整形(Noise Shaping)的能力, 能够抑制信号频宽内的量化噪声,进而提高信号噪声比(Signal ToNoise Ratio)。 Sigma-delta modulator (Sigma-Delta Modulator) has been widely used in the digital to analog converter and a (D / AConverter) analog to digital converter (A / D Converter), mainly due to the sigma-delta modulator has a noise shaping (Noise Shaping ) the ability to suppress quantization noise in the signal bandwidth, thereby increasing the signal to noise ratio (signal ToNoise ratio). 因此,在高解析度(Resolution)、中低速的应用电路中,积分三角调制器普遍受到欢迎。 Thus, in high resolution (Resolution), the low-speed application circuit, the sigma-delta modulator is generally welcomed.

[0003] 请参考图1。 [0003] Please refer to FIG 1. 图1为先前技术的一阶积分三角调制器10的示意图。 FIG 1 is a schematic diagram of a previously-order sigma-delta modulator 10 of art. 一阶积分三角调制器10包含一加法器12、一积分器13、一量化器(Quantizer) 14、一数模转换器16以及一滤波器18。 A first order sigma-delta modulator 10 comprises an adder 12, an integrator 13, a quantizer (Quantizer) 14, a digital to analog converter 16 and a filter 18. 积分三角的原理在于先粗略估测信号以算出误差,然后经过积分后,再进一步补偿误差。 Sigma-delta principle rough estimate is that the first error signal is calculated, and then, after integration, further compensation error. 如图ι所示,一输入信号Ini与数模转换器16的反馈信号sra进入加法器12相减,得到一误差信号Se,误差信号%再经过积分器13的积分,随后经由量化器14加以量化,由于量化误差会导致噪声亦被量化,最后再经过滤波器18将噪声滤除,以输出一输出信号Outl。 As shown in FIG iota, an input signal and a feedback signal Ini sra analog converter 16 into the adder 12 is subtracted to obtain an error signal Se, the error signal integrator% then through the integrator 13, the quantizer 14 via then be quantization noise due to quantization error was also cause quantization, and finally filtered through the noise filter 18 to output an output signal Outl.

[0004] 请参考图2。 [0004] Please refer to FIG 2. 图2为先前技术的二阶积分三角调制器20的示意图。 2 is a schematic diagram of a prior art second order sigma-delta modulator 20. 二阶积分三角调制器20包含一加法器12、一积分器13、一第二加法器22、一第二积分器23、一量化器14、一数模转换器16以及一滤波器18。 Second order sigma-delta modulator 20 comprises an adder 12, an integrator 13, a second adder 22, a second integrator 23, a quantizer 14, a digital to analog converter 16 and a filter 18. 积分三角调制器的阶数(Order)取决于反馈循环的个数。 Order sigma-delta modulator (Order) depending on the number of feedback loops. 如图2所示,一输入信号Inl与数模转换器16的反馈信号SFB进入加法器12相减,得到一误差信号Se,误差信号%再经过积分器13的积分以得到一积分信号Si。 2, the input signal a feedback signal SFB Inl and DAC 16 into the adder 12 is subtracted to obtain an error signal Se, the error signal integrator% then through the integrator 13 to obtain an integral signal Si. 积分信号Si再与数模转换器16的反馈信号SFB进入第二加法器22相减,随后经过第二积分器23的积分,再经由量化器14加以量化,由于量化误差会导致噪声一并被量化,最后再经过滤波器18将噪声滤除,以输出一输出信号Outl。 Si integrated signal and the feedback signal SFB and then digital to analog converter 16 into the second adder 22 are subtracted, then the second integrator 23 through the integrator, and then quantified via the quantizer 14, since the quantization error cause a noise and quantization, and finally filtered through the noise filter 18 to output an output signal Outl. 因此,二阶积分三角调制器20共做了两次的积分三角运算。 Therefore, the second-order sigma-delta modulator made a total of 20 points trigonometric twice.

[0005] 以此类推,随着积分三角运算的阶数增加,积分三角调制器的电路也越来越复杂。 [0005] and so on, as the order of sigma-delta operation, the sigma-delta modulator circuit is also more complex. 请参考图3,图3为先前技术的五阶积分三角调制器30的示意图。 Please refer to FIG. 3, a schematic view of fifth-order sigma-delta modulator 30 prior art of Figure 3. 如图3所示,五阶积分三角运算是由一第一积分三角处理单元PE1、一第二积分三角处理单元PE2、一第三积分三角处理单元PE3、一第四积分三角处理单元PE4以及一第五积分三角处理单元PE5来执行。 As shown, the fifth-order delta-sigma 3 is composed of a first integral calculation processing unit triangular PE1, a PE2 second delta-sigma processing unit, a third processing unit integrating the PE3 triangle, a triangular fourth integrator and a processing unit PE4 Sigma-Delta PE5 fifth processing unit to execute. 每一阶的积分三角处理单元至少包含一乘法器、一加法器及一积分器。 Each order delta-sigma processing unit comprises at least a multiplier, an adder and an integrator. 举例来说,第二积分三角处理单元PE2包含乘法器a (¾、b (2)、g(l) ,c (2)、积分器332、以及加法器321、322。在图3中,一输入信号Inl经过第一积分三角处理单元PEl进行第一阶的积分三角运算后,再依序经过第二阶、第三阶、第四阶及第五阶的积分三角运算。完成五阶的积分三角运算后,经由量化器34加以量化,再经由延迟器37延迟一单位时钟脉冲,最后输出一输出信号Outl。 通过五阶积分三角调制器30,可得出输入信号^il的五阶积分三角运算。然而,五阶积分三角调制器30至少需八个加法器、十八个乘法器及五个积分器,这些元件相当浪费硬件面积。 For example, the second processing unit PE2 sigma-delta multiplier comprising a (¾, b (2), g (l), c (2), an integrator 332, 321 and 322 and an adder. In FIG. 3, a after the input signals Inl a first-order delta-sigma arithmetic processing unit via a first delta-sigma PEl, and then sequentially through the second order, third order, fourth order and fifth-order delta-sigma calculation. completed fifth-order integrator after trigonometry, via the quantizer 34 to be quantized, and then delayed by one clock through the delay unit 37, an output signal of the final output Outl. 30, the input signal may be derived by the fifth-order sigma-delta modulator ^ il fifth-order sigma-delta operation. However, the fifth-order sigma-delta modulator 30 required at least eight adders, multipliers and eighteen five integrators, these hardware elements quite a waste area.

[0006] 由于音频处理仅为KHz级频率的处理,若直接实现会太过于浪费硬件成本。 [0006] Since the audio processing only treatment KHz frequency level, if the direct implementation would be too wasteful hardware costs. 因此目前的设计多使用CPU或者DSP等通用型处理器来实现,其硬件成本太高,且会造成操作频率上升,因此很难在FPGA上实现。 Therefore, the current design is often used like general-purpose CPU or DSP processors to implement, the hardware cost is too high and will cause the operating frequency is increased, it is difficult to achieve on the FPGA. 由于先前技术中,多阶的积分三角电路需使用很多加法器、乘法器及积分器,若使用于更多阶的积分三角运算,则需花费更多的加法器、乘法器及积分器,这些元件不仅增加制作成本也相对应增加了硬件面积。 Since the prior art, multi-order delta-sigma circuit need to use a lot of adders, multipliers and integrators, when used for more order delta-sigma operation, you need to spend more adders, multipliers and integrators, these element not only increases the production cost increases corresponding to the hardware area.

发明内容 SUMMARY

[0007] 本发明提供一种使用分时结构(Time Sharing Architecture)的积分三角电路, 该三角电路包含一系数产生单元、一积分三角处理单元以及一存储单元。 [0007] The present invention provides a sigma-delta circuit using a time-division structure (Time Sharing Architecture), which circuit comprises a triangular coefficient generating unit, a processing unit and a delta-sigma memory unit. 该系数产生单元用来产生积分三角运算的系数。 The coefficient generating means for generating a delta-sigma factor calculation. 该积分三角处理单元用来根据该系数产生单元所产生的积分三角运算的系数,执行积分三角运算。 The integration processing unit triangular cam means for integrating coefficient generated based on the coefficients generated in operation, integration is performed trigonometric. 该存储单元用来存储该积分三角处理单元的积分三角运算结果。 The storage unit for storing the delta-sigma sigma-delta calculation result processing unit. 其中,该积分三角电路用来通过该系数产生单元、该积分三角处理单元及该存储单元,执行多阶的积分三角运算。 Wherein the sigma-delta circuit through the means for generating the coefficient, the sigma-delta processing unit and the memory unit, performs a multi-order delta-sigma calculation.

[0008] 本发明提供一种于一积分三角电路中使用分时结构来处理音频的方法,该方法包含产生积分三角运算的系数,根据所产生的积分三角运算的系数,执行积分三角运算,以及存储积分三角运算结果。 [0008] The present invention provides a method of processing an audio time-sharing configuration in a sigma-delta circuit, the method comprising coefficient generating sigma-delta operation, according to the integral coefficients of the generated trigonometric, trigonometric integration is performed, and Sigma-Delta storage operation results. 其中通过上述步骤,执行多阶的积分三角运算。 Wherein the above steps, the implementation of multi-order delta-sigma calculation. 该方法还包含接收多个系数,接收一状态信号,以及根据该状态信号由该多个系数中选择一系数输出。 The method further comprises receiving a plurality of coefficients, receiving a status signal, and selecting a coefficient output by the plurality of coefficients according to the state signal. 该方法还包含对积分三角运算结果进行量化。 The method further includes the integral trigonometry to quantify the results.

附图说明 BRIEF DESCRIPTION

[0009] 图1为先前技术的一阶积分三角调制器的示意图。 [0009] FIG. 1 is a schematic diagram of a previously-order sigma-delta modulator techniques.

[0010] 图2为先前技术的二阶积分三角调制器的示意图。 [0010] FIG. 2 is a schematic view of the previous second order sigma-delta modulator techniques.

[0011] 图3为先前技术的五阶积分三角调制器的示意图。 [0011] FIG. 3 is a schematic view of a fifth-order sigma-delta modulator previous filter techniques.

[0012] 图4为本发明的实施例说明使用分时结构的积分三角电路的示意图。 Embodiment [0012] FIG. 4 is a schematic diagram illustrating the present invention using the sigma-delta circuit configuration of a time-sharing embodiment.

[0013] 图5为图4的积分器的示意图。 [0013] FIG. 5 is a schematic diagram of the integrator of FIG.

[0014] 图6为图4的积分器的另一示意图。 [0014] FIG. 6 is a schematic diagram of another integrator of FIG. 4.

[0015] 图7为本发明另一实施例说明使用分时结构的积分三角电路的示意图。 [0015] FIG. 7 illustrates a schematic view of the use of sigma-delta circuit configuration of a time-sharing according to another embodiment of the present invention.

[0016] 图8为说明使用分时结构积分三角电路的示意图。 [0016] FIG. 8 is a schematic time-sharing configuration sigma-delta circuit will be described.

[0017] 图9为一音频处理结构的示意图。 [0017] FIG. 9 is a schematic diagram of a configuration of an audio processing.

[0018] 图10为本发明说明于一积分三角电路中使用分时结构来处理音频的流程的示意图。 [0018] FIG 10 a schematic view of the present invention will be described using the time-sharing in a sigma-delta circuit configuration to handle the flow of audio.

[0019] 主要元件符号说明 [0019] Main reference numerals DESCRIPTION

[0020] 10 一阶积分三角调制器 [0020] 10 a first order sigma-delta modulator

[0021] 12、321、322、45、46、52、62、75 加法器[0022] 13、332、42 积分器 [0021] 12,321,322,45,46,52,62,75 adder [0022] 13,332,42 integrator

[0023] 14、34、84 量化器 [0023] 14,34,84 quantizer

[0024] 16数模转换器 [0024] DAC 16

[0025] 18滤波器 [0025] 18 filter

[0026] Inl输入信号 [0026] Inl input signal

[0027] 20 二阶积分三角调制器 [0027] 20 second order sigma-delta modulator

[0028] 22第二加法器 [0028] The second adder 22

[0029] Se误差信号 [0029] Se error signal

Outl输出信号 Output signals Outl

23第二积分器 23 second integrator

Sfb反馈信号 Feedback signal Sfb

[0030] Si积分信号 [0030] Si integrated signal

[0031] &第二运算信号 [0031] The second operation signal &

[0032] 30五阶积分三角调制器 [0032] 30 fifth-order sigma-delta modulator

[0033] PEl第一积分三角处理单元 [0033] PEl a first delta-sigma processing unit

[0034] PE2第二积分三角处理单元 [0034] PE2 second delta-sigma processing unit

[0035] PE3第三积分三角处理单元 [0035] PE3 third sigma-delta processing unit

[0036] PE4第四积分三角处理单元 [0036] PE4 fourth integrator triangle processing unit

[0037] PE5第五积分三角处理单元 [0037] PE5 fifth sigma-delta processing unit

[0038] a(2),b(2),g(l),c(2), [0038] a (2), b (2), g (l), c (2),

[0039] 431、432、433、434、73 乘法器 [0039] 431,432,433,434,73 multiplier

[0040] 37、54、64、76 延迟器 [0040] 37,54,64,76 retarder

[0041] 40、70积分三角电路41系数产生单元 [0041] The sigma-delta circuit 41 40,70 coefficient generating unit

[0042] 44、74积分三角处理单元 [0042] The delta-sigma processing unit 44, 74

[0043] 47存储单元 [0043] The storage unit 47

[0044] MUXl第一多路转换器MUX2第二多路转换器 [0044] MUXl a first multiplexer of the second multiplexer MUX2

[0045] MUX3第三多路转换器[0046] a[1] -a[n]、c [1] -C [n]、g[1] -g[n]、a、c、g 系数 [0045] MUX3 third multiplexer [0046] a [1] -a [n], c [1] -C [n], g [1] -g [n], a, c, g coefficient

[0047] 411、413、415 控制端 [0047] 411,413,415 control terminal

[0048] 412、414、416 输出端 [0048] 412, 414, an output terminal

[0049] STl状态信号 CNTl计数信号 [0049] STl count signal state signal CNTl

[0050] X、y、 [0050] X, y,

[0051] addsub_res、wen、wptr、rptr、dfram、d2ram 参数 [0051] addsub_res, wen, wptr, rptr, dfram, d2ram parameters

[0052] 522、5¾ 输入端 [0052] 522,5¾ input

[0053] 622第一输入端 6¾第二输入端 [0053] The first input terminal 622 second input terminal 6¾

[0054] MUX11-MUX66 多路转换器 [0054] MUX11-MUX66 multiplexer

[0055] AA,虚线 [0055] AA, dashed line

[0056] t时间轴 [0056] t time axis

[0057] CFl 系数 [0057] CFl coefficient

[0058] ADCl模数转换器 [0058] ADCl ADC

[0059] I2S标准数字语音格式 [0059] I2S digital audio format standard

[0060] 92取样率转换器 94音频处理单元[0061] 95积分三角调制器 [0060] The sample rate converter 92 audio processing unit 94 [0061] 95 sigma-delta modulator

[0062] 97低通滤波器 [0062] The low-pass filter 97

[0063] 80 流程 [0063] Process 80

96功率放大器98扬声器802-810 步骤 The power amplifier 98 loudspeaker 96 steps 802-810

具体实施方式 detailed description

[0064] 请参考图4。 [0064] Please refer to FIG 4. 图4为本发明一实施例使用分时结构的积分三角电路40的示意图。 FIG 4 is a schematic diagram using an integrating circuit sharing the triangular configuration of an embodiment 40 of the present invention. 积分三角电路40包含一系数产生单元41、一积分三角处理单元44以及一存储单元47。 Integrator circuit 40 comprises a triangular coefficient generating unit 41, a processing unit 44, and a delta-sigma a memory unit 47. 系数产生单元41用来产生积分三角运算的系数a、c、g,其包含第一多路转换器MUX1、第二多路转换器MUX2以及第三多路转换器MUX3。 Coefficient generating unit 41 for generating a sigma-delta calculation coefficient a, c, g, comprising a first multiplexer MUX1, a second multiplexer MUX2 and a third multiplexer MUX3. 第一多路转换器MUXl包含η个输入端、一控制端411以及一输出端412。 A first multiplexer MUXl contains η inputs, a control terminal 411 and an output terminal 412. 该η个输入端用来接收η个系数a[l]-a[n],控制端411用来接收一状态信号ST1,输出端412用来根据状态信号STl由η个系数a[l]-a[n]中选择一系数a输出。 The input terminal for receiving η η coefficients a [l] -a [n], a control terminal 411 for receiving a state signal ST1, an output terminal 412 is used by the status signal STl from the η coefficients a [l] - a [n] to select the output of a coefficient a. 第二多路转换器MUX2包含η个输入端、一控制端413以及一输出端414。 A second multiplexer MUX2 comprises η inputs, a control terminal 413 and an output terminal 414. 该η个输入端用来接收η个系数c [1] -C [η],控制端413用来接收状态信号ST1,输出端414用来根据状态信号STl由η个系数c [1]-C [η]中选择一系数c输出。 The [eta] [eta] input terminal for receiving the coefficients c [1] -C [η], a control terminal 413 for receiving the state signal ST1, an output terminal 414 is used by the status signal STl [eta] by the coefficients c [1] -C [[eta]] in a selected output coefficients c. 第三多路转换器MUX3包含η 个输入端、一控制端415以及一输出端416。 A third multiplexer MUX3 contains η inputs, a control terminal 415 and an output terminal 416. 该η个输入端用来接收η个系数g[1] _g[η],控制端415用来接收状态信号STl,输出端416用来根据状态信号STl由η个系数g[l]_g[n] 中选择一系数g输出。 The [eta] [eta] input terminal for receiving the coefficients g [1] _g [η], a control terminal 415 for receiving the status signal STl, according to the status output terminal 416 to signal STl g [eta] by the coefficients [l] _g [n ] selects a coefficient g output. 积分三角处理单元44用来根据系数产生单元41所产生的积分三角运算的系数a、c、g,执行积分三角运算。 Triangular integration processing unit 44 for generating a delta-sigma calculation unit 41 generates the coefficients a, c, g, integration is performed in accordance with trigonometric coefficients. 积分三角处理单元44为一般的积分三角处理单元, 通常至少包含一乘法器、一加法器及一积分器。 Integration processing unit 44 is generally triangular delta-sigma processing unit typically includes at least one multiplier, an adder and an integrator. 如图4所示,积分三角处理单元44包含四乘法器431、432、433、434,两加法器45、46及一积分器42,其中,乘法器431、432、433、434 的系数分别为由系数产生单元41所产生的系数a、a、g、c。 4, the sigma-delta processing unit 44 comprises four multipliers 431,432,433,434, two adders 45, 46 and an integrator 42, wherein the multiplier coefficients were 431,432,433,434 coefficients generated by the coefficient generating unit 41 a, a, g, c. 输出信号Out可表示为以下的式子: Output signal Out may be expressed as the following equation:

[0065] Outl = [ / [aX Gnl-y)_gXx]] Xe。 [0065] Outl = [/ [aX Gnl-y) _gXx]] Xe.

[0066] 若需执行五阶积分三角运算,则令η等于5,于每一阶积分三角运算中,导入不同的系数a、c、g进行积分三角运算,即可完成五阶积分三角运算。 [0066] For the implementation of the fifth-order sigma-delta operation, so that η is equal to 5, to each order sigma-delta operation, the introduction of the different coefficients a, c, g integrating trigonometry, to complete the fifth-order sigma-delta calculation. 存储单元47用来存储积分三角处理单元44的积分三角运算结果。 The storage unit 47 for storing delta-sigma sigma-delta calculation processing unit 44 of the result. 积分三角电路40通过系数产生单元41、积分三角处理单元44及存储单元47,执行多阶的积分三角运算。 Sigma-delta circuit 40 by the coefficient generating unit 41, a delta-sigma processing unit 44 and a storage unit 47, performs multi-order delta-sigma calculation. 其中,存储单元47为一随机存取存 Wherein the storage unit 47 is a random access memory

[0067] 请参考图5。 [0067] Please refer to FIG 5. 图5为图4的积分器42的示意图。 FIG 5 is a schematic diagram of the integrator 42 of FIG. 4. 积分器42可由一个加法器52及一个延迟器M来组成,并形成一反馈回路。 Integrator 42 by an adder 52 and a delay M in the composition, and forming a feedback loop. 加法器52包含两输入端522、524,分别用来接收一输入信号Inl及前一个输出信号的值,将输入信号Inl及前一个输出信号的值进行相加后,以产生一第二运算信号&,第二运算信号&再由延迟器M来延迟一个时钟脉冲以产生最后的输出信号Outl。 An adder 52 comprises two input terminals 522, 524, respectively, for receiving an input signal value and the previous output Inl signal, the input value and the previous output signal Inl signals are summed to generate a second operation signal &, then the second operation signal by the delay & M a delayed clock pulse to produce the final output signal Outl.

[0068] 请参考图6。 [0068] Please refer to FIG 6. 图6为图4的积分器42的另一示意图。 6 is another schematic of the integrator 42 of FIG. 4. 积分器42可由一个加法器62及一个延迟器64来组成,并形成一反馈回路。 Integrator 42 by an adder 62 and a delay 64 to constitute and form a feedback loop. 加法器62包含一第一输入端622,用来接收一输入信号hl,及一第二输入端624,耦接于延迟器64的输出端,用来接收经过延迟一个时钟脉冲后的前一个输出信号的值,将输入信号Inl与经过延迟一个时钟脉冲后的前一个输出信号的值进行相加,以产生最后的输出信号Outl。 The adder 62 comprises a first input terminal 622 for receiving an input signal HL, and a second input terminal 624 coupled to the output of the delay 64, for receiving via a front output delayed by one clock pulse after value of the signal, the input signal Inl and after adding the value for the previous output signal delayed by one clock pulse later, to produce the final output signal Outl.

[0069] 由图5与图6可知,积分器的结构可视为一加法器以及一延迟器。 [0069] apparent from Figures 5 and 6, the structure of the integrator can be regarded as an adder and a delay. 因此图4的积 Thus the product of FIG. 4

储器(Random AccessMemory, RAM)。 Reservoir (Random AccessMemory, RAM). 分三角处理单元44可进一步简化成一个加法器及一个乘法器,再搭配多个多路转换器及多个延迟器,以执行不同阶的运算。 Triangular sub-processing unit 44 may be further simplified to a multiplier and an adder, and then with a plurality of multiplexers and a plurality of delays, to perform the operation of different orders. 如此一来,可以减少更多的加法器及乘法器,进一步节省更多的硬件面积。 Thus, the adder can be reduced more and a multiplier, a further saving more hardware area.

[0070] 请参考图7。 [0070] Please refer to FIG 7. 图7为本发明另一实施例使用分时结构的积分三角电路70的示意图。 Figure 7 a schematic view of another embodiment of the sigma-delta circuit 70 using a time-sharing configuration of the present invention. 积分三角电路70包含一系数产生单元41、一积分三角处理单元74以及一存储单元47。 Sigma-delta circuit 70 comprises a coefficient generating unit 41, a processing unit 74, and a delta-sigma a memory unit 47. 系数产生单元41用来产生积分三角运算的系数a、c、g。 Coefficient generating unit 41 for generating a sigma-delta calculation coefficient a, c, g. 系数产生单元41包含第一多路转换器MUX1、第二多路转换器MUX2以及第三多路转换器MUX3。 Coefficient generating unit 41 comprises a first multiplexer MUX1, a second multiplexer MUX2 and a third multiplexer MUX3. 其中第一多路转换器MUX1、第二多路转换器MUX2以及第三多路转换器MUX3用来产生积分三角运算的系数a、c、g,其工作原理与图4的实施例相同,于此不再详加叙述。 Wherein a first multiplexer of MUX1, a second multiplexer MUX2 and a third multiplexer MUX3 for generating a sigma-delta calculation coefficients a, Example c, g, and its working principle is the same as FIG. 4, in It will not be described in detail. 积分三角处理单元74用来根据系数产生单元41所产生的积分三角运算的系数a、c、g,执行积分三角运算。 Triangular integration processing unit 74 for generating a delta-sigma calculation unit 41 generates the coefficients a, c, g, integration is performed in accordance with trigonometric coefficients. 积分三角处理单元74为简化后的积分三角处理单元,其包含一乘法器73、一加法器75、四个延迟器76、六个多路转换器MUX11-MUX66以及一量化器84。 After the integration processing unit 74 is a simplified triangular delta-sigma processing unit comprising a multiplier 73, an adder 75, a delay 76 four six multiplexers MUX11-MUX66 and a quantizer 84. 存储单元47用来存储积分三角处理单元74的积分三角运算结果,于本实施例中,可用来存储多个参数addsub_res、wen、wptr、rptr、dfram、d2ram。 The storage unit 47 for storing delta-sigma sigma-delta calculation result processing unit 74, in this embodiment, can be used to store a plurality of parameters addsub_res, wen, wptr, rptr, dfram, d2ram. 由于积分器的结构可视为一加法器以及一延迟器,积分三角处理单元74在虚线AA'的左半部分通过多个多路转换器MUX11-MUX44来选择由哪一个参数来进行加法运算。 Since the structure of the integrator can be regarded as an adder and a delay unit, a delta-sigma processing unit 74 in the broken line AA 'in the left half by a plurality of multiplexers MUX11-MUX44 to be selected by the adder which parameter. 积分三角处理单元74在虚线AA'的右半部分则是先通过一多路转换器MUX55来选择系数产生单元41 所产生的系数a、c、g,通过另一个多路转换器MUX66来选择由哪一个参数进入乘法器73以进行乘法运算。 Sigma-Delta processing unit 74 in the broken line AA 'in the right half is first selected coefficient generating unit 41 generates a coefficient via a multiplexer MUX55, c, g, is selected by the other multiplexer MUX66 which parameter to the multiplier 73 for multiplication. 图中的延迟器76用来延迟一个时钟脉冲。 FIG delay 76 for delaying a clock pulse. 量化器84用来对积分三角运算结果进行量化。 Quantizer 84 is used to quantify the results of the Sigma-Delta operation. 积分三角处理单元74通过多个多路转换器MUX的选择可以节省乘法器73 及加法器75的个数。 Triangular integration processing unit 74 can save the number of multipliers 73 and an adder 75 through a plurality of multiplexers MUX selection. 积分三角电路70通过系数产生单元41、积分三角处理单元74及存储单元47,执行多阶的积分三角运算。 Sigma-delta circuit 70 by the coefficient generating unit 41, a delta-sigma processing unit 74 and a storage unit 47, performs multi-order delta-sigma calculation. 其中,延迟器76为一D型触发器,存储单元47为一随机读取存储器。 Wherein the retarder is a D-type flip-flop 76, the storage unit 47 is a random access memory.

[0071] 请参考图8。 [0071] Please refer to FIG 8. 图8为说明使用分时结构于积分三角电路的示意图。 FIG 8 is a schematic diagram of time-sharing configuration in sigma-delta circuit. 于时间轴上t 上,共分为五个阶段1、2、3、4、5,分别由五个积分三角处理单元PE1-PE5来执行积分三角运算,可由状态信号STl来选择目前状态阶段,由计数信号CNTl来选择每一阶段中欲进行的运算(如加法运算、乘法运算)。 The upper time axis t, 1,2,3,4,5 divided into five stages, each calculation performed by the delta-sigma sigma-delta five processing units PE1-PE5, by the state signal to select current state STl stage, selecting a count signal CNTl operation in each stage to be carried out (e.g., adding, multiplication). 通过系数产生单元41,可于不同的状态阶段产生不同的系数,举例而言,于第一阶段产生系数a(l)、c (1)、g(l),以此类推,于第五阶段产生系数a(5)、c (5)、g(5)。 The coefficient generating unit 41, in different states may have different stages of coefficients, for example, to produce a coefficient a (l), c (1), g (l), and so on in a first stage, the fifth stage generating coefficients a (5), c (5), g (5). 因此通过系数产生单元41以及状态信号ST1,通过此种分时结构, 只需要一个积分三角处理单元74来执行不同阶段的积分三角运算。 Thus generating unit 41 and a status signal ST1 by a factor, by sharing this structure, only a delta-sigma processing unit 74 performs various stages of sigma-delta calculation. 再通过多个多路转换器MUX11-MUX66与计数信号CNTl的使用,可以进一步节省电路中乘法器与加法器的个数, 只需要一个乘法器以及一个加法器来执行不同加法运算或乘法运算,即可完成积分三角运笪弁。 Then MUX11-MUX66 CNTl using the count signal, and may further save the number of multipliers and an adder circuit via a plurality of multiplexers, requires only a multiplier and an adder to perform an addition or multiplication different, integral to complete the triangle shipped Da Bian.

[0072] 请参考图9。 [0072] Please refer to FIG 9. 图9为一音频处理结构90的示意图。 9 is a schematic diagram of an audio processing structure 90. 音频处理结构90包含一模数转换器ADC1、一取样率转换器92、一音频处理单元94、一积分三角调制器95、一功率放大器96、一低通滤波器97以及一扬声器98。 The audio processing structure 90 comprises a analog to digital converter ADC1, a sample rate converter 92, an audio processing unit 94, a sigma-delta modulator 95, a power amplifier 96, a low pass filter 97 and a speaker 98. 模数转换器ADCl用来将信号转换成数字格式,如标准数字语音格式I2Santer-ICSoimd)。 ADCl digital converter for converting the signal into digital format, such as the standard digital audio format I2Santer-ICSoimd). 标准数字语音格式1¾的信号先经过取样率转换器92进行取样率的转换或者重新取样,再经过音频处理单元94处理,的后再经由积分三角调制器95进行积分三角运算。 Standard digital voice signal format 1¾ first pass through the sampling rate converter 92 converts the sampling rate or resampling, an audio processing unit 94 and then through the process, and then integrating the trigonometric via sigma-delta modulator 95. 其中,积分三角调制器95可为图4中的积分三角电路40或图7中的积分三角电路70,利用分时结构来减少加法器及乘法器的使用个数。 Wherein the sigma-delta modulator 95 may be in the sigma-delta circuit 40 of FIG. 4 or FIG. 7 sigma-delta circuit 70 by time sharing structure to reduce the number of adders and multipliers used. 经过积分三角调制器95的后的信号,再送至功率放大器96,功率放大器96可为一D类放大器或者一AB 类放大器。 After the sigma-delta signal modulator 95, and then sent to amplifier 96, amplifier 96 may be a Class D amplifier or a Class AB amplifier. 最后信号送至扬声器98播放,扬声器98为一喇叭。 Finally playback signal to the speaker 98, the speaker 98 is a speaker. 低通滤波器97耦接于功率放大器96与扬声器98之间,用来过滤噪声。 Low-pass filter 97 is coupled between the power amplifier 96 and the speaker 98, to filter noise.

[0073] 请参考图10。 [0073] Please refer to FIG 10. 图10为本发明说明于一积分三角电路中使用分时结构来处理音频的流程80的示意图。 FIG 10 illustrate the present invention using schematic time-sharing structure 80 to the audio processing flow in a sigma-delta circuit. 流程80可表示为以下的步骤: 80 may be expressed as the following process steps:

[0074] 步骤802 :产生积分三角运算的系数。 [0074] Step 802: generating a delta-sigma factor calculation.

[0075] 步骤804 :根据所产生的积分三角运算的系数,执行积分三角运算。 [0075] Step 804: The delta-sigma factor generated by operation of the integration is performed trigonometric.

[0076] 步骤806 :存储积分三角运算结果。 [0076] Step 806: storing the integration result of the operation cam.

[0077] 步骤808 :重复步骤802-808。 [0077] Step 808: Repeat steps 802-808.

[0078] 步骤810 :对积分三角运算结果进行量化。 [0078] Step 810: the integral trigonometry to quantify the results.

[0079] 于步骤802中,可通过一多路转换器的运用,根据目前的阶数及欲执行的运算步骤,从多个系数中选择一系数输出。 [0079] In step 802, by using a multiplex converter, according to the current order and the operation step to be executed, selected from a plurality of coefficient output coefficients. 于步骤804中,根据所产生的积分三角运算的系数,执行积分三角运算。 In step 804, based on the coefficients generated by the Sigma-Delta operation, integration is performed trigonometric. 于步骤806中,将积分三角运算结果存储于一存储器中。 In step 806, the sigma-delta calculation result is stored in a memory. 于步骤808中, 由于需执行η阶的积分三角运算,因此需重复产生每一阶积分三角运算所需的系数以执行每一阶所需的积分三角运算。 In step 808, since the need to perform η order sigma-delta calculation, thus generating the desired coefficient repeat each order sigma-delta operation to perform the desired operation of each sigma-delta stage. 于步骤810中,当完成所有的积分三角运算后,对最后的运算结果进行量化,完成一次完整的信号流程。 In step 810, after the completion of all integration trigonometry, on the final result of the operation to quantify, to complete a full signal flow. 其中,积分三角运算的系数的产生由一状态信号STl来控制,积分三角运算执行的阶数及欲执行的运算步骤则是由状态信号STl及计数信号CNTl来控制。 Wherein generating trigonometric coefficients of integration is controlled by a signal state STl, and the order of operation steps to be performed in the delta-sigma operations performed is controlled by the state signal and the count signal STl CNTl.

[0080] 上述的实施例仅用来说明本发明的使用分时结构的积分三角电路及其相关方法, 并不局限本发明的范畴。 [0080] The above-described embodiments are merely illustrative of sigma-delta circuit and associated methods of using time-division structure of the present invention is not limited to the scope of the invention. 文中所提到的延迟器76并不局限于D型触发器,亦可为其他型式的延迟器。 Mentioned herein is not limited to the delay D flip-flop 76, it may also be other types of delays. 存储单元47亦不局限于一随机读取存储器,亦可使用其他的存储装置。 Nor limited to the memory unit 47 a random access memory, other storage means may also be used. 系数产生单元41所包含的多路转换器的个数相对应于积分三角运算的系数个数,并不局限于实施例所述的三个多路转换器。 The number of coefficients to produce the number of coefficients multiplexer unit 41 included in the integration operation corresponding to the triangle, the embodiment is not limited to three multiplexor embodiment. 文中所提到的积分三角电路40与积分三角电路70皆是使用分时结构的积分三角电路,唯积分三角电路70通过多个多路转换器MUX11-MUX66的使用, 来节省更多的加法器及乘法器,但不局限于本发明的实施例,可以有更多的变化,皆属于本发明的范畴。 Sigma-delta circuit 40 mentioned in the text are all the integrating circuits using the triangular cam 70 integral configuration sharing the circuit, the only sigma-delta circuit 70 by a plurality of multiplexers MUX11-MUX66 used to save additional adder and a multiplier, but are not limited to the embodiment of the present invention, there may be more changes belong to the scope of the invention.

[0081] 由上可知,本发明提供一使用分时结构的积分三角电路。 [0081] From the above, the present invention provides the use of a delta-sigma circuit sharing configuration. 于积分三角电路40与积分三角电路70中,通过系数产生单元41产生不同的系数,可于不同的阶数及欲执行的运算步骤产生所需的系数,由状态信号STl及计数信号CNTl来控制目前的阶数及欲执行的运算步骤,可以依序执行多阶的积分三角运算。 The integrating circuit 40 and the triangular cam integrating circuit 70, the coefficient generating unit 41 generates different coefficients may be different in order to be executed and the step of calculating the coefficients to produce the desired, controlled by the state signal and the count signal STl CNTl the current order of the steps and operations to be executed, can be performed sequentially multi-order delta-sigma operations. 且通过多个多路转换器MUX11-MUX66的使用,可以节省更多的加法器及乘法器。 And by using a plurality of multiplexers MUX11-MUX66 can save more multipliers and adders. 如此一来,可以省略更多的积分三角运算单元以及节省更多的加法器及乘法器等元件,避免硬件面积及成本的浪费。 Thus, more points can be omitted and trigonometric operations unit to save more components such as adders and multipliers, to avoid wasting hardware size and cost. 此外,操作频率仍控制在合理的范围内,如一般的音频取样率44. ΙΚΗζ,若总共有五阶积分三角运算,每一阶积分三角运算包含五级欲执行的运算步骤,则操作频率为1ΚΧ5Χ5)Ηζ,仍可以在FPGA上实现。 In addition, the operating frequency remains within reasonable range, such as general audio sample rate 44. ΙΚΗζ, if the total fifth-order sigma-delta operation, each stage comprising calculating trigonometric integral five steps to be executed, the operation frequency is 1ΚΧ5Χ5) Ηζ, can still be implemented on the FPGA.

[0082] 以上所述仅为本发明的优选实施例,凡依本发明权利要求所进行的等效变化与修改,皆应属本发明的涵盖范围。 [0082] The above are only preferred embodiments of the present invention, all equivalent modifications and variations under this invention as claimed in claim performed, also belong to the scope of the present invention.

Claims (16)

  1. 1. 一种使用分时结构的积分三角电路,包含有: 一系数产生单元,用来产生积分三角运算的系数;一积分三角处理单元,用来根据该系数产生单元所产生的积分三角运算的系数,执行积分三角运算;以及一存储单元,用来存储该积分三角处理单元的积分三角运算结果; 其中,该积分三角电路用来通过该系数产生单元、该积分三角处理单元及该存储单元, 执行多阶的积分三角运算,其中该积分三角处理单元包含:一加法器,该加法器具有一第一输入端、一第二输入端及一输出端,该第一输入端用来接收一输入信号,该第二输入端用来接收一输出信号,该加法器用来对该输入信号及该输出信号进行加法运算以产生一运算信号;以及一积分器,具有一输入端耦接于该加法器的该输出端,用来接收该运算信号,及一输出端耦接于该加法器的该第二输入端 A time-sharing configuration of the delta-sigma circuit, comprising: a coefficient generating means for generating a trigonometric integral coefficient; a delta-sigma processing unit for generating a sigma-delta calculation means based on the generated coefficients coefficients, performs integration trigonometric; and a memory unit for storing the integration result of the integrator triangle trigonometric processing unit; wherein the delta-sigma circuit means for generating the coefficient by which the integration processing unit and the triangular storage unit, performing multi-order delta-sigma operation, wherein the delta-sigma processing unit comprises: an adder, the adder having a first input terminal, a second input terminal and an output terminal, the first input terminal for receiving an input signal , the second input terminal for receiving an output signal of the adder to the input signal and the output signal of the adding operation to generate a signal; and an integrator, having an input coupled to the adder the output terminal, for receiving the operation signal, the second input terminal and an output terminal coupled to the adder 该积分器用来对该运算信号进行积分以产生该输出信号,其中该积分三角处理单元还包含一第一多路转换器,该第一多路转换器包含: 一第一输入端,耦接于该加法器的该输出端,用来接收该加法器的运算结果; 一第二输入端,耦接于该存储单元,用来接收该积分三角处理单元前一个的积分三角运算结果;二控制端,分别用来接收一状态信号与一计数信号;以及一输出端,用来根据该二控制端所接收的该状态信号与该计数信号选择输出该加法器的运算结果或者该积分三角处理单元前一个的积分三角运算结果。 The integrator for integrating the operation signal to generate the output signal, wherein the delta-sigma processing unit further comprises a first multiplexer, the first multiplexer comprises: a first input terminal coupled to the the output of the adder, for receiving the operation result of the adder; a second input terminal coupled to the storage means for receiving the delta-sigma sigma-delta calculation result of a preprocessing unit; two control terminal , respectively, for receiving a status signal and a count signal; and an output for the status signal before the two control terminal received the count signal selects the output of the adder or the result of calculation processing unit according to the Sigma-Delta a delta-sigma result of the operation.
  2. 2.如权利要求1所述的积分三角电路,其中该系数产生单元还包含多个第二多路转换器,其中每一个第二多路转换器包含:多个输入端,用来接收多个系数; 一控制端,用来接收该状态信号;以及一输出端,用来根据该状态信号由该多个系数中选择一系数输出。 2. The sigma-delta circuit according to claim 1, wherein the coefficient generating unit further comprises a plurality of second multiplexers, wherein each of the second multiplexer comprises: a plurality of input terminals for receiving a plurality of coefficient; a control terminal for receiving the status signal; and an output terminal, for selecting a coefficient output by the plurality of coefficients according to the state signal.
  3. 3.如权利要求1所述的积分三角电路,其中该积分器包含:一第二加法器,具有一第一输入端、一第二输入端及一输出端,该第一输入端用来接收该运算信号,该第二输入端用来接收该输出信号,该第二加法器用来对该运算信号及该输出信号进行加法运算以产生一第二运算信号;以及一延迟器,具有一输入端耦接于该第二加法器的该输出端,用来接收该第二运算信号, 及一输出端,耦接于该第二加法器的该第二输入端,该延迟器用来将该第二运算信号延迟一个时钟脉冲,以产生该输出信号。 3. The sigma-delta circuit according to claim 1, wherein the integrator comprises: a second adder having a first input terminal, a second input terminal and an output terminal, a first input terminal for receiving the the operation signal, the second input terminal for receiving the output signal of the second adder for adding to the operation signal and the output signal to generate a second operational signal; and a delay device having an input terminal the output terminal coupled to the second adder, for receiving the second operation signal, and an output terminal coupled to the second input terminal of the second adder, the delay for the second calculating a delayed clock signal to generate the output signal.
  4. 4.如权利要求3所述的积分三角电路,其中该延迟器为一 D型触发器,用来闩锁该第二运算信号并于下一个时钟脉冲输出该输出信号。 4. The sigma-delta circuit according to claim 3, wherein the retarder is a D type flip-flop for latching the second signal and outputting operation of the output signal at a clock pulse.
  5. 5.如权利要求1所述的积分三角电路,其中该积分三角处理单元还包含一量化器,耦接于该积分器的该输出端,该量化器用来对该输出信号进行量化。 5. The integrating circuit according to a triangular claim 1, wherein the delta-sigma quantizer further comprises a processing unit, coupled to the output terminal of the integrator, the quantizer is used to quantize the output signal.
  6. 6.如权利要求1所述的积分三角电路,其中该积分三角处理单元还包含一第三多路转换器,耦接于该系数产生单元的输出端,该第三多路转换器用来根据该状态信号与该计数信号由多个系数中选择一系数输出。 6. The sigma-delta circuit according to claim 1, wherein the delta-sigma processing unit further comprises a third multiplexer, coupled to the output of the coefficient generating means, the third multiplexer according to the status signal and the count signal by a selected plurality of coefficients in a coefficient output.
  7. 7.如权利要求6所述的积分三角电路,其中该积分三角处理单元还包含一乘法器,该乘法器包含:一第一输入端,耦接于该第三多路转换器的输出端,用来接收该第三多路转换器所输出的系数;一第二输入端,耦接于该第一多路转换器,用来接收该加法器的运算结果或者该积分三角处理单元前一个的积分三角运算结果;以及一输出端;其中,该乘法器用来对该第一多路转换器所输出的系数以及该加法器的运算结果或者该积分三角处理单元前一个的积分三角运算结果进行乘法运算,以产生积分三角运算结果ο 7. The sigma-delta circuit according to claim 6, wherein the delta-sigma processing unit further comprises a multiplier, the multiplier comprising: a first input terminal coupled to the output terminal of the third multiplexer, coefficients for receiving the third multiplexer MUX output; before a second input terminal coupled to the first multiplexer, for receiving the operation result of the adder or the integration of a triangular processing unit sigma-delta calculation result; and an output terminal; wherein the calculation result to the multiplier coefficient of the first multi-path converter and the output of the adder of the integrator triangle or a delta-sigma calculation result by multiplying the preprocessing unit operation, to generate a delta-sigma result of the operation ο
  8. 8.如权利要求1所述的积分三角电路,其中该存储单元为一存储器。 The sigma-delta circuit as claimed in claim 1, wherein the memory cell is a memory.
  9. 9.如权利要求1所述的积分三角电路,其中该存储单元为一随机读取存储器。 9. The sigma-delta circuit according to claim 1, wherein the memory means is a random access memory.
  10. 10. 一种于一积分三角电路中使用分时结构来处理音频的方法,该方法包含: 产生积分三角运算的系数;根据所产生的积分三角运算的系数,执行积分三角运算;以及存储积分三角运算结果; 其中通过上述步骤,执行多阶的积分三角运算, 其中根据所产生的积分三角运算的系数,执行积分三角运算包含: 接收一输入信号及一输出信号,对该输入信号及该输出信号进行加法运算以产生一运算信号;以及对该运算信号进行积分以产生该输出信号,其中该根据所产生的积分三角运算的系数,执行积分三角运算,还包含: 接收该加法运算的运算结果; 接收前一个的积分三角运算结果; 接收一状态信号与一计数信号;以及根据所接收的该状态信号与该计数信号选择输出该加法运算的运算结果或者前一个的积分三角运算结果。 10. A method for processing an audio time-sharing configuration in a sigma-delta circuit, the method comprising: generating a sigma-delta calculation coefficients; coefficient according to the integral calculation of the generated triangle, trigonometric integration is performed; and storing delta-sigma computation result; wherein the above steps, the implementation of multi-order delta-sigma calculation, wherein the delta-sigma factor calculation according to the generated integration is performed trigonometric operations comprising: receiving an input signal and an output signal, the input signal and the output signal for adding operation to generate a signal; and integrating the operation signal to generate the output signal, wherein the delta-sigma factor based on the generated operation, integration is performed trigonometric, further comprising: receiving a calculation result of the addition operation; before receiving a trigonometric integration result; receiving a status signal and a count signal; and selecting the count signal based on the received status signal output of the operational result of the addition or the integration of a front triangle calculation result.
  11. 11.如权利要求10所述的方法,其还包含: 接收多个系数;接收该状态信号;以及根据该状态信号由该多个系数中选择一系数输出。 11. The method according to claim 10, further comprising: receiving a plurality of coefficients; receiving the status signal; and a coefficient selected by outputting the state signal according to the plurality of coefficients.
  12. 12.如权利要求10所述的方法,其中对该运算信号进行积分以产生该输出信号包含: 对该运算信号及该输出信号进行加法运算以产生一第二运算信号;以及将该第二运算信号延迟一个时钟脉冲,以产生该输出信号。 And the second operational; operation for adding the signal and the output signal to generate a second operation signal: 12. The method according to claim 10, wherein the operation signal is integrated to generate the output signal comprises a delayed clock pulse signal, to generate the output signal.
  13. 13.如权利要求12所述的方法,其中延迟一个时钟脉冲指闩锁该第二运算信号并于下一个时钟脉冲输出该输出信号。 13. The method of claim 12, wherein the means delayed by one clock pulse of the latch signal and outputs the second operation of the output signal at a clock pulse.
  14. 14.如权利要求10所述的方法,其还包含: 对该输出信号进行量化。 14. The method according to claim 10, further comprising: quantizing the output signal.
  15. 15.如权利要求10所述的方法,其中根据所产生的积分三角运算的系数,执行积分三角运算,还包含根据该状态信号与该计数信号由多个系数中选择一系数输出。 15. The method according to claim 10, wherein the delta-sigma factor generated according to the operation of the integration is performed trigonometric, further comprising a plurality of coefficients in a coefficient output based on the selected state signal and the counting signal.
  16. 16.如权利要求15所述的方法,其中该根据所产生的积分三角运算的系数,执行积分三角运算,还包含:接收根据该状态信号与该计数信号选择输出的系数; 接收该加法运算的运算结果或者前一个的积分三角运算结果;以及对根据该状态信号与该计数信号选择输出的系数以及该加法运算的运算结果或者前一个的积分三角运算结果进行乘法运算,以产生积分三角运算结果。 16. The method according to claim 15, wherein the delta-sigma factor generated according to the operation of the integration is performed trigonometric, further comprising: receiving a selection signal outputted from the count signal coefficient according to the state; receiving the summation of calculation result or sigma-delta calculation results of the previous one; and multiplication based on the calculation result of the state signal coefficient count signal selects the output and the adder or the delta-sigma calculation result previous one, to produce a sigma-delta calculation result .
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Publication number Priority date Publication date Assignee Title
EP0531604A1 (en) 1991-06-28 1993-03-17 ALCATEL BELL Naamloze Vennootschap Digital sigma-delta modulator
CN1150507A (en) 1994-06-07 1997-05-21 芬西泰克元件公司 Oversampled high-order modulator
US6396428B1 (en) 2001-06-04 2002-05-28 Raytheon Company Continuous time bandpass delta sigma modulator ADC architecture with feedforward signal compensation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0531604A1 (en) 1991-06-28 1993-03-17 ALCATEL BELL Naamloze Vennootschap Digital sigma-delta modulator
CN1150507A (en) 1994-06-07 1997-05-21 芬西泰克元件公司 Oversampled high-order modulator
US6396428B1 (en) 2001-06-04 2002-05-28 Raytheon Company Continuous time bandpass delta sigma modulator ADC architecture with feedforward signal compensation

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