JP3513117B2 - Non-volatile semiconductor memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage layer
A memory cell having a MOS transistor structure having a gate
Electrically rewritable nonvolatile semiconductor configured using the same
(E^TwoPROM), especially E^TwoEEPROM copy
Non-volatile semiconductor memory with several chips integrated on the same substrate
About the card. [0002] 2. Description of the Related Art^TwoIn the field of PROMs, charge storage layers (eg
MOS transistor with floating gate) and control gate
Memory cells having a data structure are widely known. This E^TwoPR
The OM memory cell array has row and column lines that intersect each other.
And a memory cell is arranged at each intersection point of. Actual
In the above pattern, the drain of two memory cells is common
The column occupied area is connected to the column line here
Is as small as possible. But still,
Contact with column line for each common drain of two memory cells
Contact area, and this contact area increases the cell occupation area.
Occupy a critical part. As a promising solution to this problem, the present applicant
Is the NAND cell configuration E^TwoProposing PROM
(Japanese Patent Application No. 62-233944). This NAND cell
Integrates a memory cell with a floating gate and a control gate into a
Direct connection with multiple sources and drains
Is done. NAND cells are arranged in a matrix.
The drain on the end is connected to the bit line, and the
The control gate is connected to a word line. This NAND cell
Data erase and write operations on floating gates and drains
It utilizes the tunneling of electrons between the layers or substrates. The erasing / writing operation will be described specifically.
Data is erased by applying about 20 V to the word lines of all memory cells.
An “H” level potential is applied, and an “L” level potential is applied to the bit line.
For example, 0V is applied. This allows all memory cells to be
Electrons from the substrate to the floating gate
Erased state where the threshold value has moved in the positive direction due to more implantation
(For example, a threshold value of 2 V). This is a batch erase
You. [0005] Data writing is performed by using bits of NAND cells.
From the memory cell farthest from the memory cell line. This and
At this time, for example, an “H” level potential of 23 V is applied to the bit line.
And the word line connected to the selected memory cell is set to 0.
V is applied, and the 23V “H” level is applied to the unselected word lines.
Is applied. Memory cells that have already been written
Is set to 0V. This allows
The “H” level potential of the gate line is the drain of the selected memory cell.
To the floating gate.
Threshold is shifted to negative direction due to release of electrons to drain
Data writing in state "1" (for example, threshold value -2V)
Done. At this time, the bit line side of the selected memory cell
In a memory cell, no electric field is applied between the control gate and the substrate,
Keep the erased state. In the case of "0" write, an intermediate power is applied to the bit line.
For example, 11.5V is applied. At this time,
Memory mode on the bit line side of the memory
However, these have not been written yet,
Also, since the electric field is weak, there is no possibility of excessive erasure. data
For reading, select 0V to the selected word line, and to other word lines
For example, by applying 5 V and detecting the presence or absence of a current,
U. If "1", current flows; if "0", current flows
Absent. The E of such a NAND cell configuration^TwoPRO
M represents a plurality of memory cells constituting a NAND cell.
It is only necessary to provide one contact part with the bit line
Conventional general E^TwoCell occupation area is smaller than PROM
It has the advantage of being smaller, but on the other hand, the NAND configuration
, The cell current at the time of reading is small.
There is a problem that it takes time. This is especially true for NA
Large when the number of memory cells constituting the ND cell is increased.
Is a problem. The conventional floppy (registered trademark)
This disk^TwoWhen trying to replace with PROM
First, the data read time must be reduced.
At the same time, it is also required to shorten the data write time.
You. [0008] As described above, conventionally,
E using a volatile semiconductor memory cell^TwoPROM uses this
How fast data writing and reading when large scale
Is an important solution. The present invention has been made in view of the above circumstances.
Therefore, the purpose is to use nonvolatile memory cells.
Data when usedWriteCan be performed at high speed and
Non-volatile that can achieve sufficient speedup even in the case of large scale
An object of the present invention is to provide a volatile semiconductor memory card. [0010] [MEANS FOR SOLVING THE PROBLEMS]
The present invention employs the following configuration. [0011] [0012] [0013] [0014] [0015] [0016] [0017] [0018] [0019] [0020] [0021]That is, the present inventionThe first having the first erasing unit
One nonvolatile semiconductor memory array and the first erase unit.
Second nonvolatile half having a second erase unit smaller than
Interface with conductor memory array, outside and front
Controlling the first and second nonvolatile semiconductor memory arrays;
Semiconductor memory car provided with a control circuit for
Wherein the control circuit includes the first nonvolatile semiconductor device.
Body memory arrayOn the interfaceEntered user
UserFile data equivalent to the file contents of the data
TaAnd write the2Nonvolatile semiconductor memory array
ToManagement data for managing the file databook
Is characterized by [0022] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described according to the form. FIG. 1 is a block diagram of one embodiment of E^TwoThe whole PROM
FIG. 3 is a block diagram showing a configuration. 11 is E^TwoPROM array
12 is a sense amplifier, 13 is a row decoder, 1
4 is a row address buffer, 15 is a column decoder, and 17 is a data decoder.
Data buffer, and 18 is a data out buffer.
You. Row decoder 15, data in buffer 17 and data
Input data and output
A shift register 16 for temporarily storing data is provided.
Have been. These circuits are integrated on one chip substrate
Is formed. FIG. 2 is a diagram showing the E of FIG.^TwoPROM array 11
It is an equivalent circuit diagram. In this embodiment, four memory cells
Le M₁~ M_FourAre directly connected to form a NAND cell.
Therefore, such NAND cells are arranged in a matrix.
You. The drain of the NAND cell is connected to the first selection MOS transistor.
To the bit line BL via the transistor S1n (n = 1 to 512)
Connected and the source is the second selection MOS transistor S2n
(N = 1 to 512). Each memory cell
Control gate is connected to the word line WL crossing the bit line BL.
Connected. FIG. 3 is a plan view showing one NAND cell.
FIGS. 4 (a) and 4 (b) are sectional views taken along the lines AA 'and BB'.
It is. p^-Separated by the element isolation insulating film 2 of the silicon substrate 1
In the area defined, four memory cells and two
Are formed. Each memory cell
Is to form a first gate insulating film 3 made of a thermal oxide film on a substrate 1.
Floating gate 4 (4
₁~ 4₈) Is formed, and a second gate insulating film 5 is formed thereon.
Through the control gate 6 (6
₁~ 6₈) Is formed. Of each memory cell
The control gates 6 are connected to word lines WL (WL₁~ W
L₈). N serving as the source and drain of the memory cell⁺
The mold layer 9 has four memories shared by adjacent ones.
Cells are connected in series. And in this embodiment,
Select transistor S on drain side and source side₁, S_ThreeBut
They are connected to form one NAND cell. Select transistor S₁, S_ThreeGate electrode of
4₉, 6₉And 4_Ten, 6_TenIs the floating gate of the memory cell
And first and second layer polycrystalline silicon forming a control gate.
The electrode 4 is obtained by simultaneously patterning₉And 6
₉Between and electrode 4_TenAnd 6_TenBetween word line directions
Contact at intervals. The whole is covered with the CVD insulating film 7
The selection transistor S for the memory cell₁Dre
N⁺Bit line BL that contacts the mold layer
All the Al wirings 8 are provided. Between the floating gate 4 and the substrate 1 in each memory cell
Coupling capacity C₁Is the connection between the floating gate 4 and the control gate 6.
Total capacity C_TwoIt is set smaller than. Concrete shape
To describe the dimensions, the floating gate 4 and the control gate 6
Are both 1 μm in pattern width and therefore the channel of the memory cell
The length is 1 μm, and the floating gate 4 is as shown in FIG.
1 μm each on both sides of the field area
I have. The first gate insulating film 3 is a 20 nm thermal oxide film.
The second gate insulating film 5 is a 35 nm thermal oxide film.
You. Such a NAND cell has a structure as shown in FIG.
Bit line contacts and source diffusion layers
It is arranged repeatedly while being folded in the direction of the line. FIG.
Memory cell M₁~ M₈Focused on the NAND cell consisting of
Timing to explain erase and write operations
FIG. First, a memory cell constituting a NAND cell
M₁~ M_FourAll at once. For this reason this implementation
In the state, the selection transistor S₁Gate electrode SG₁To
Giving an “H” level (for example, a boosted potential Vpp = 20 V),
Select transistor S_TwoGate electrode SG_TwoAlso "H" level
(For example, Vcc = 5V), and all of the NAND cells
Keep the drain and source of the memory cell at 0V,
WL₁~ WL_Four"H" level (for example, Vpp = 20V)
give. As a result, the memory cell M₁~ M_FourControl game
Electric field between the gate and the source, drain and substrate
Electrons are injected into the floating gate by the tunnel effect.
You. Memory cell M₁~ M_FourGives a square threshold
In the “0” state. Thus, the word line WL
₁~ WL_FourAll NAND cells along are erased collectively
You. Next, data is written to the NAND cell.
U. Write data to the memory farthest from the bit line BL.
Cell M_FourPerform in order from This means that when writing,
Memory cells on the bit line side of the memory are in erase mode
That's why. First, the memory cell M_FourWriting to
As shown, the selection transistor S₁Gate SG₁and
Word line WL₁~ WL_ThreeVoltage Vpp + Vth (memory
"H" level (e.g., the threshold value of the erased state of the cell)
For example, 23 V). Selected memory cell M_FourControl game
Word line WL connected to_FourAnd selection transistor S_Twoof
Gate electrode SG_TwoIs "L" level. At this time,
When the “H” level is applied to the scan line BL,
Jista S₁And memory cell M₁~ M_ThreeThrough the channel
Is the memory cell M_FourOf the memory cell
Le M_FourThen, a high electric field is applied between the control gate and the substrate. As a result, the electrons of the floating gate have a tunnel effect.
Is released to the substrate, and the threshold moves in the negative direction.
Thus, for example, the state becomes "1" at the threshold value -2V. This and
Memory cell M₁~ M_ThreeNow the electric field between the control gate and the substrate
And keep the erased state. When writing “0”, the bit
An intermediate potential (for example, 10 V) is applied to the scanning line BL. Next, the memory cell M_ThreeMove on to writing. That is
Select gate SG₁, SG_TwoRemains at “H” level
Also, the word line WL_ThreeAt the “L” level. At this time
When "H" level is applied to the bit line BL, the memory cell
M_Three"1" is written. And so on
Cell M_Two, M₁Write to. In the above, E of the embodiment^TwoPROM
The configuration and operation of the constituent basic NAND cells have been described. Next
A memory array using such a NAND cell and its
The operation of the overall configuration of Fig. 1 including the peripheral circuits
I will tell. In this embodiment, E^TwoPROM array 11
, The number of bit lines is 512, and the shift register 16
Has a capacity four times the number of bit lines. FIG. 6 shows this E^TwoPROM page mode
To explain data erase and write operations by
FIG. Chip enable signal / CE is
It becomes “L” level and E^TwoPROM chip is active
Become / OE is an output enable signal.
When this is at "H" level, it is the write mode. / WE
This is a write enable signal, which is
The address is fetched when the signal becomes "L" level. address
Refers to one block of the memory array shown in FIG.
Set. SIC is a serial input counter
And when this changes from "L" level to "H" level
Capture input data. R / B is a Ready / Busy signal.
During writing, this becomes “L” level and writing to outside
Let them know you are Serial input card
Counter SIC “H” level → “L” level → “H” level
One cycle of the bell cycle (in this embodiment, note
(4 times the number of bit lines in the re-array 512)
Thus, the data for one page is stored in the shift register 16.
It is taken in at high speed. Temporarily stored in shift register 16
Data transferred to the bit line of the memory array 11 at the same time
Is written to the memory cell specified by the address.
It is. Therefore, according to this embodiment, the page mode
Time required to write 512 × 4 bit data
Is 1 μsec to take in one piece of external data
Time to capture 512 × 4 data (= 1 μsec
× 512 × 4) + erase time (10 msec) + write
The interval (10 msec) ≒ 22 msec. By the way,
No shift register 16 and no page mode
When writing data with the same number of bits in
And erasing time are both 10 msec, 512 × 2
0 msec ≒ 41 sec. Thus this embodiment
According to the above, about 1850 times high-speed writing becomes possible.
You. FIG. 7 is a timing chart for explaining the read operation.
FIG. Chip enable / CE is “H” level
The address is fetched when it goes to "L" level from the bell
You. E at once when writing^TwoData written to PROM
The serial data must be read in the same order as entered when writing.
The output counter SOC changes from "L" level to "H".
It is output one by one when the level is reached. R / B is a memo
Shift the 512 × 4 data from the recell
To the "L" level for the transfer to the
Inform. Many bits of data are stored in the shift register 16
At the same time, they are captured in parallel and read out serially.
Therefore, compared to the case without a shift register,
, High-speed data reading is performed. FIGS. 14A and 14B show shift register 1
6 and a flip-flop F used for the same.
F (FF₁, FF_Two,...). Flip flip
The FF is a p-channel MOS transistor Q₁And n
Channel MOS transistor Q_TwoIs on and p-channel
MOS transistor Q_ThreeAnd n-channel MOS transistor
TA Q_FourWorks as a flip-flop when the
In the opposite state, it is a two-stage inverter train. FIG. 15 shows the data input of this shift register.
Timing diagram showing the data input operation from the
is there. φ and / φ are serial input counter signals
A clock signal generated from the SIC inside the chip,
For example, when φ is at “L” level and / φ is at “H” level
First flip of shift register from data-in buffer
Flop FF₁The data is transferred to Next, φ becomes “H”
Level, / φ is "L" level, flip-flop
FF₁Is the flip-flop FF_TwoTransferred to
You. Data is transferred serially in the same manner.
You. FIG. 16 shows data from the shift register.
Timing diagram showing data transfer operation to out buffer
It is. The clocks φ and / φ in this case are serial
Created inside the chip from output counter signal SOC
It is. Thus, according to this embodiment, E^TwoPR
By incorporating a shift register in the OM,
Writing and reading can be performed at high speed. FIG. 8 is a diagram showing E of another embodiment of the present invention.^TwoPR
It is a block diagram which shows OM. This embodiment is a
Magnetic recording media such as
E^TwoIt is assumed to be replaced with PROM, and NAN
A first E for recording the first type of information composed of D cells
^TwoUsing a PROM array 19 and a conventional memory cell configuration
A second E for recording the second type of information;^TwoPROM array
27 are integrally formed on the same substrate. The first E^TwoThe configuration of the PROM array 19 is
This is the same as the embodiment. This first E^TwoPROM array
A sense amplifier 20 for detecting an output and a row
Decoder 23, row address buffer 22, column decoder 2
3 and the like, and input / output data as in the previous embodiment.
A shift register 24 for temporarily storing data.
You. Second E^TwoAround the PROM array 27,
Amplifier 28, column address buffer 31, row decoder 29
Etc. are arranged. 25 is a data-in buffer and 26 is a data-in buffer.
Data out buffer. FIG. 9 shows the E thus configured.^TwoPRO
M for explaining data erase and write operations in M
It is a timing diagram. Chip enable signal / CE
This E at the time of “L” level^TwoPROM is active
You. / OE is an output enable signal, which is
When the signal is at "H" level, the writing mode is set. / DIRE is
Directory memory enable signal, which is
The second E at the time of “L” level ^TwoActivate PROM array 27
Access. When / DIRE is at "L" level, the write
Enable / WE changes from “H” level to “L” level
Address from the “L” level to the “H” level.
Captures input data when Second E^TwoPROM
The array 27 is erased and written one byte at a time.
When / DIRE is at “H” level, the first E^TwoPRO
The M array 19 is accessed. The operation at this time is
This is the same as in the embodiment. FIG. 10 is a diagram illustrating a read operation.
FIG. When / DIRE is at “L” level,
E of 2^TwoPROM array 27 is accessed and / CE is
When going from “H” level to “L” level, or
The read operation is performed when the data changes. Output data is 1 byte.
It is read out at a time. / DIRE is at “H” level
The first E^TwoThe PROM array 19 is accessed.
The first E at this time^TwoThe operation of the PROM array 19 is
This is the same as described in the embodiment. E according to this embodiment^TwoPROM, for example
Can be used to store computer software.
Erasing / writing and reading operations byte by byte
The second E to do^TwoThe PROM array 27 stores file information
In the memory area (directory / memory area) that stores
Yes, for example, by storing the contents shown in FIG.
You. First E for batch erase / write / read^TwoPRO
The M array 19 is a memory area for storing file contents.
(Data area), and in this embodiment, one sector is 2
It is 56 bytes. Thus, E according to this embodiment^TwoPROM
If you replace the floppy disk,
Disk drive unit, disk drive interface
, Etc., are unnecessary, resulting in higher speed, lighter and smaller size, and power saving.
Is achieved. FIGS. 12 (a) and 12 (b) show the present invention in an LSI method.
FIG. 2 is a perspective view and a plan view of an embodiment applied to a moly card.
You. Reference numeral 32 denotes E described in the embodiment of FIG.^TwoPROM switch
And here E^TwoEquipped with PROM chip 32
It is listed. These E^TwoFor PROM chip 32
Thus, E shown in the embodiment of FIG.^TwoPROM array 27
E as corresponding directory memory area^TwoPRO
One M chip 33 is mounted.
Control LSI that functions as an interface between
The chip 34 is mounted. 35 is a connection terminal. Figure
Reference numeral 13 denotes a system configuration of the LSI memory card. Thus, according to the present embodiment, high speed and small size
A lightweight, power-saving memory card can be obtained. [0054] As described in detail above, according to the present invention,
Data writing and data writing using volatile memory cells
Data can be read at high speed and the scale becomes large.
In this case, the speed can be sufficiently increased. Also, multiple memory
The chip is used as a memory area for storing file contents.
A memo that manages file information using another memory chip
The disk drive device and disk
Without the need for a screen drive interface, etc.
Used as a substitute for floppy disk
Speed, light weight, and low power consumption
Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an E ² PROM according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing a memory array configuration of the E ² PROM of FIG. 1; FIG. 3 is a plan view showing one NAND cell of the E ² PROM of FIG. 1; FIG. 4 is a sectional view taken along line AA ′ and BB ′ of FIG. 3; FIG. 5 is a timing chart for explaining an erase operation and a write operation of a NAND cell. FIG. 6 is a timing chart for explaining an erase / write operation of the E ² PROM of the embodiment. FIG. 7 is a timing chart for explaining a read operation of the E ² PROM of the embodiment. FIG. 8 is a block diagram showing an E ² PROM according to another embodiment. FIG. 9 is a timing chart for explaining an erase / write operation of the E ² PROM of FIG. 8; FIG. 10 is a timing chart for explaining a read operation of the E ² PORO of FIG. 8; FIG. 11 is a diagram showing a configuration example of a directory memory area. FIG. 12 is a perspective view and a plan view showing a memory card according to still another embodiment of the present invention. FIG. 13 is a system configuration diagram of the memory card in FIG. 12; FIG. 14 is a diagram showing a specific configuration example of a shift register used in the present invention and its components. FIG. 15 is a timing chart for explaining a data input operation to the shift register of FIG. 14; FIG. 16 is a timing chart for explaining a data output operation to the shift register in FIG. 14; DESCRIPTION OF REFERENCE NUMERALS 1 semiconductor substrate 2 element isolation insulating films 3 and 5 gate insulating film 4 floating gate 6 control gate 7 CVD insulating film 8 bit line 9 n ⁺ type layer 11 NAND cell type Memory cell array 12 sense amplifier 13 row decoder 14 row address buffer 15 column decoder 16 shift register 17 data in buffer 18 data out buffer 19 first E ² PROM array 20 sense amplifier 21 row decoder 22 row address buffer 23 column decoder 24 shift register 25 data in buffer 26 data out buffer 27 second E ² PROM array 28 sense amplifier 29 row decoder 30 column decoder 31 column address buffer

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuo Ito 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside of Toshiba Research Institute, Inc. (72) Hideko Ohira 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Address: Toshiba Research Institute, Inc. (72) Inventor: Fujio Masuoka 1st, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (56) References JP-A-62-226391 (JP, A) JP-A-61-227300 (JP, A) JP-A-61-283097 (JP, A) JP-A-61-216520 (JP, A) JP-A-51-48943 (JP, A) JP-A-61-54585 (JP, A) JP-A-63-73348 (JP, A) JP-A-63-200399 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06K 19/07 G11C 16/02

Claims (1)

(57) A first nonvolatile semiconductor memory array having a first erase unit and a second nonvolatile semiconductor memory having a second erase unit smaller than the first erase unit. Interface between the non-volatile semiconductor memory array and the outside and the first and second
And a control circuit for controlling the non-volatile semiconductor memory array, wherein the control circuit controls the user data input to the interface to the first non-volatile semiconductor memory array .
Writes the file data corresponding to the out file contents, the said second non-volatile semiconductor memory array file
A nonvolatile semiconductor memory card for writing management data for managing file data .