JP3508962B2 - Semiconductor sensor with built-in amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor sensor with a built-in amplifier circuit, and more particularly to reducing variations in its output characteristics.

[0002]

2. Description of the Related Art As a conventional semiconductor strain sensor used for detecting pressure or acceleration, a semiconductor sensor with a built-in amplifier circuit in which a signal amplifier is integrated on a chip has been put into practical use. Taking a semiconductor pressure sensor as an example, four strain gauge (diffusion) resistors formed in the diaphragm part at the center of the chip are bridge-connected to form a signal conversion part, which is individually output from a pair of output ends thereof. The signal voltage is linearly voltage-amplified by the signal amplifier, that is, the sense amplifier, respectively,
The subtraction unit forms a difference voltage between the amplified signal voltages and outputs the difference voltage. Generally, an operational amplifier type linear amplifier circuit is often used as the both-signal amplifier.

Further, in this type of sensor, the basic problem is to reduce variations in DC offset and detection sensitivity. Therefore, trim resistors are built in the signal conversion section and adjusted to reduce them. Is normal. Although it is theoretically possible to perform this for each chip after dicing the chips from the wafer as the adjustment of the trim resistance,
Actually, from the viewpoint of productivity, it is performed on a wafer-by-wafer basis by applying a high voltage obtained by irradiating a scanning laser beam to the trim resistor on the wafer.

[0004]

However, by adjusting the trim resistance on the wafer as described above, DC on the wafer is adjusted.
Even if variations in offset and detection sensitivity are reduced, the amount of fluctuations in DC offset and detection sensitivity (hereinafter referred to as output characteristics) is increased by fixing the diced chip and the pedestal joined thereto to the package. There was a troublesome problem.

As a result of various experiments, the inventors of the present invention have found that the main cause of the variation in the output characteristics after the dicing process is that after the strain gauge is formed on the semiconductor wafer and before the trimming. Process, for example, damage to the wafer by plasma particles in the process of forming a diaphragm or bending beam by etching from the backside of the wafer, thermal effects in the process of anodic bonding the wafer to a pedestal with a different coefficient of thermal expansion, soldering of the pedestal It has been found that the cause is damage caused by X-rays or ultraviolet rays to the back surface of the diaphragm or the like in the step of depositing the metallized layer on the surface by vacuum deposition or sputtering.

The thermal effect will be described more specifically. Since the wafer and the pedestal bonded at a high temperature in the anodic bonding have different coefficients of thermal expansion, residual stress is generated between them in the subsequent normal temperature operation. Occurs, which affects the characteristics of the signal amplification unit throughout the wafer. Further, since a plurality of insulating films and metal wirings having different thermal expansion coefficients are arranged in the integrated circuit region which constitutes the signal amplifying unit on the chip, the signal amplifying unit is constructed after the above anodic bonding is completed. Residual stress occurs in the integrated circuit area. This residual stress is released and relaxed by the heat in the chip fixing step, but the degree of this relaxation varies from chip to chip, and the output characteristics fluctuate accordingly. Further, it is conceivable that a residual stress may be newly generated in the signal amplification section due to the same reason as described above due to the heat in the chip fixing step.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor sensor with a built-in amplifier circuit in which variations in output characteristics are small.

[0008]

The first structure of the present invention is as follows.
Signal converter a difference to output a pair of signal voltage corresponding to a predetermined physical quantity, a pair of signal amplifier for amplifying the two signal voltages separately, and the differential voltage of the amplified signal voltage output from the two signal amplifier a semiconductor chip integrated into the surface of the subtraction unit for outputting, is thermally bonded to the back surface of the semiconductor chip,
In the amplifier circuit built-semiconductor sensor including a pedestal having different thermal expansion coefficients from that of the semiconductor chip, the semiconductor
The body chip is composed of the entire peripheral part of the semiconductor chip.
Formed in a square shape having a support part that is joined to the pedestal
The pair of signal amplifiers are connected to the chip of the semiconductor chip.
A line connecting the center point and the midpoint of the side of the semiconductor chip,
Alternatively, the point at the center of the semiconductor chip and the semiconductor
Formed in line symmetry with the line connecting the tip of the chip as the reference line.
Are separated into a pair of axisymmetric regions having substantially equal residual stresses.
It is an amplification circuit embedded semiconductor pressure sensor, characterized in that formed on.

As described above, when a joining member such as a stem or a circuit board is fixed to the diced chip by ordinary thermal joining (for example, soldering), the signal amplifying portion of the pedestal's anodic joining described above is fixed. The residual stress is relaxed or newly generated by the heat at the time of this thermal bonding, and the output characteristics of the signal amplifying unit fluctuate. The pair of signal amplifiers are arranged at different positions on the chip, and the stress relaxation state varies depending on the position on the chip. The stress relaxation causes variations in the output characteristics of the pair of signal amplification units.

If the residual stress at the end face (side) of the chip, which is the free end, is 0, the above-mentioned residual stress tends to increase monotonically from each side toward the chip center point. Such a distribution of iso-stress lines typically appears when it is considered that an insulating film or a metal film having a different coefficient of thermal expansion exists on the entire main surface of the silicon chip, but it is almost the same in an actual chip. . Therefore, a chip that is square or rectangular has two pairs of sides that are at right angles to each other,
The residual stresses at the same distance from the parallel sides should be almost equal. In other words, the residual stress states at the two symmetrical positions should be almost equal.

In the present specification, being at a symmetrical position with respect to the center of the chip means that the line is symmetrical with respect to the line connecting the center point of the chip and the midpoint of the side of the chip, and the center point of the chip. It refers to the case of line symmetry with respect to the line connecting the apex of the chip and the case of rotational symmetry with respect to the center point of the chip. Therefore, by arranging the pair of signal amplifiers at symmetrical positions, it is possible to reduce the difference in stress fluctuation between the signal amplifiers and thereby reduce the fluctuations in the output characteristics of both signals.

The term "a pair of signal amplifiers arranged symmetrically with respect to each other" as defined in this configuration means that the space on the chip where one of the signal amplifiers is formed (the signal amplifier section arrangement region) is With respect to the space on the chip on which the other signal amplifying portion is formed, in the case of line symmetry, when it is temporarily folded and overlapped with the reference line, and in the case of rotational symmetry, when it is rotated 180 degrees about the reference point, It means a state in which they are substantially overlapped (80% or more in area), and the remaining portion is also continuously arranged in the overlapped portion. In addition, the space (a region where the signal amplification unit is provided) refers to a region that includes all circuit elements (transistors, resistors, capacitors) and internal wiring of the signal amplification unit and is surrounded by a boundary line that connects their outer edges. .

In a preferred embodiment, the semiconductor chip has a joining member which is thermally joined to the semiconductor chip . This makes it possible to compensate for variations in output characteristics due to a heat treatment process (for example, soldering) after dicing, which cannot be remedied by adjusting the trim resistance of the wafer.

According to a second structure of the present invention, in addition to the above-mentioned first structure, the both signal amplifying sections are arranged in line symmetrical positions and within a range of half or less of the distance from the center line to the side. Is characterized by. According to this configuration, both signal amplifiers are arranged in line-symmetrical positions, and variations in output characteristics due to residual stress due to thermal history acting on both signal amplifiers can be suppressed, and both are close to each other. The surface variation of the impurity concentration of the semiconductor substrate is also reduced, and the output characteristic variation is further suppressed.

According to a third structure of the present invention, in addition to the above-mentioned first structure, the signal conversion section is composed of a resistance bridge circuit including a strain gauge arranged on a diaphragm region or a beam region in the chip. Is characterized by. If a diaphragm region that bends due to pressure or a beam region that bends due to acceleration is formed on the semiconductor substrate, the rigidity of the semiconductor substrate decreases and deformation due to residual stress in the chip increases, so arrange both signal amplification parts in symmetrical positions. The effect of reducing the variation in the output characteristics becomes even more remarkable.

A fourth structure of the present invention is the above-mentioned first to third structures.
In any one of the above configurations, the first-stage amplification circuits of the both signal amplification units are further arranged at the symmetrical positions. Since the variations in the output characteristics (DC offset and sensitivity (amplification factor)) of the first-stage amplifier circuit occupy almost the main part of the variations in the output characteristics of the signal amplifier section, it is the most important to reduce the variations in the output characteristics of the first-stage amplifier circuit. By setting the first-stage amplifier circuit in a symmetrical position, it is possible to remarkably improve the effect of reducing variations in output characteristics.

In a fifth configuration of the present invention, in addition to the fourth configuration, from the two-dimensional barycentric position of the first circuit element arranged in one of the first-stage amplifier circuits to the side of the semiconductor chip, the semiconductor the distance measured at right angles to the side d1, from being disposed on the other of the first-stage amplifier in the circuit two-dimensional center of gravity of the second circuit element comprising said circuit element pair becomes the sides and in line symmetry If the distance measured to the side of the chip at right angles to the side is d2, the difference between the two distances Δd = (d1
-D2) is the average of both distances dm = (d1 + d2) / 2 1
It is characterized by being less than 5%, preferably less than 10%.

According to this structure, not only the spaces of both the first-stage amplifier circuits are line-symmetrically overlapped, but the centers of gravity (two-dimensional barycentric positions) of the spaces forming the circuit elements forming the first-stage amplifier circuit are individually line-symmetrical. Therefore, the variation in output characteristics can be further reduced. A sixth configuration of the present invention is characterized in that, in the fifth configuration, the two-dimensional center-of-gravity positions of the transistors and resistors of one of the first-stage amplification circuits and the first-stage amplification circuits satisfy one of the distance conditions. There is.

According to this structure, all of the transistors and resistors forming the first-stage amplifier circuit are line-symmetrical, so that it is possible to further reduce variations in output characteristics .

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The preferred embodiments of the present invention will be described with reference to the following examples.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor pressure sensor to which the present invention is applied will be described below with reference to FIG. A square silicon chip 2 is bonded onto the block-shaped base 1. The silicon chip 2 has a rectangular frame-shaped supporting portion 20 whose back main surface is joined to the pedestal 1, and the supporting portion 20 is constituted by the entire peripheral portion of the silicon chip 2. A thinned diaphragm portion 21 is formed in the central portion of the silicon chip 2, a strain gauge 3 is formed in the diaphragm portion 21, and an amplifier circuit portion 4 is formed in the support portion 20. Two
Reference numeral 2 is an aluminum wiring, 23 is a silicon oxide film, and 24 is a SiO ₂ system or SiN system or a protective film in which both are laminated.

When the pressure introduced through the pressure introducing hole 10 formed in the pedestal 1 is changed, the diaphragm portion 21 is distorted and the resistance value of the strain gauge 3 is changed. The signal is inputted to the signal amplifying unit and subtracting unit 4 in the invention, and the amplifying unit 4 amplifies it and outputs it to the outside. A main circuit integrated on the silicon chip 2 will be described with reference to FIG.

The four strain gauges 3 form a bridge circuit (a signal converter in the present invention). In this bridge circuit, 31 and 32 are resistors for laser trimming, and 33 is a resistor that limits a current to the trim resistor 32. One of both input ends of the bridge circuit is grounded, and the other is fed from the constant voltage circuit 35 through the current limiting resistor 34. The signal voltages V1 and V2 output from the pair of output terminals of the bridge circuit are individually voltage-amplified by the amplifiers (signal amplification units) 41 and 42 of the amplification unit 4 to obtain the amplified voltage V.
1 ', V2', and the difference voltage ΔV = (V1'-V2 ') between the two by the subtraction circuit (subtraction unit in the present invention) 43.
Is calculated and output.

FIG. 3 shows the first stage amplifier circuit 4 of the amplifiers 41 and 42.
An example of 10 is illustrated. This first-stage amplifier circuit 410 is an ordinary bipolar differential amplifier, and has base resistors rb, r.
The signal voltage V1 and the reference voltage Vref are input to the bases of the transistors T and T ′ through b ′, and the amplified voltage V1 ′ is output from the collector of the transistor T. rc, r
c'is a collector resistance, Te is a transistor for limiting the emitter current, and re is its emitter resistance.

FIG. 4 shows a schematic plan view of the silicon chip 2. The diaphragm portion 21 is formed at the center of the chip, and four strain gauges 3 are formed on the diaphragm portion 21. 4a is a space (area) where the amplifier 41 is formed, and 4b is a space (area) where the amplifier 42 is formed.
Is. Both areas 4 a and 4 b are parallel to the center point of the chip 2
It is formed in mirror symmetry with a line symmetry reference line L connecting the midpoint of the side as a reference line, and when the chip is folded along the line symmetry reference line L, both regions 4a and 4b overlap by 90% or more.
In addition, the transistors T ′, T, and T in both the regions 4a and 4b are
Te and the resistors rb, rb ′, re, rc, and rc ′ are also arranged in line symmetry positions as much as possible.

FIG. 5 shows the first-stage amplifier circuit 410 of the amplifier 41.
4A shows a region 410a in which is formed and a part of a region 410b in which the first-stage amplifier circuit 410 of the amplifier 42 is formed. 41
Reference numerals 1a and 411b respectively denote regions where the transistor T is formed, and their two-dimensional barycentric positions g1 and g2 are arranged at a distance d1 and d2 from one side 11 of the silicon chip 2. Further, the two-dimensional barycentric positions g1 and g2 are separated by a distance d1 ′ from two sides orthogonal to the side 11 of the silicon chip 2,
It is arranged to be separated by d2 '. Naturally, in this embodiment, the distances d1 and d2 are matched, and the distances d1 ′ and d2 ′ are matched.

Similarly, the distances d1 and d2 and the distances d1 'and d2' of the transistor Te and the resistances rb, rb ', re, rc, rc' shown in FIG. 3 are made equal to each other as much as possible. By doing so, the distances from the entire sides of the pair of regions, which are mirror images of each other, become equal, and the states of residual stress in these regions become equal, so that the amplifiers 41, 42, especially their first-stage amplifier circuits, are made. Four
It is possible to obtain the effect that the output characteristics of 10 match.

(Experimental Results) FIG. 6 shows that in the silicon chip 2 shown in FIG. 4, when the two-dimensional barycenter position of the region 4a of the amplifier 41 is G1 and the two-dimensional barycenter position of the region 4b of the amplifier 42 is G2, The distance from G1 to side 11 is D1,
If the distance from G1 to side 12 is D1 ', the distance from G2 to side 11 is D2, and the distance from G2 to side 13 is D2', D1 = D2 = about 0.42 mm, D1 '= D
2 '= about 0.85 mm, the thermal fluctuation amount V1'. Of the offset voltage of the operational amplifiers 41 and 42 in the no-pressure application state when the temperature is raised to the soldering temperature (about 300 ° C.). V2 'is measured. Number of samples n is 2
0, one side of the chip 2 was about 0.42 mm, and the area of the diaphragm portion 21 was about 0.71 mm ² . The silicon chip 2 is bonded to the pedestal 1 by anodic bonding as described later,
The base 1 is assumed to be fixed to the metal stem by soldering.

FIG. 8 is a comparative example, in which D1 is set with respect to the two-dimensional barycenter position G1 of the region 4a 'in which the amplifier 41 is formed.
mm, D1 ' mm and area 4
The extending direction of a ′ is 45 degrees with respect to the side 12, and the other conditions are the same. The output characteristics of the sensor (example product) of FIG. 6 are shown in FIG. 7, and the output characteristics of the sensor of FIG. 8 (comparative example product) are shown in FIG.

The variation in output characteristics, in this case, the DC offset voltage V1'-V2 'could be reduced to 1/4 or less. (Modification) A modification will be described with reference to FIG. In this example, the line symmetry reference line L ′ is the chip center point 16 and the vertex 17
It is a straight line that connects with. Even in this case, the same effect as described above can be obtained.

(Description of Manufacturing Process of Silicon Chip 2) An example of the manufacturing process of the silicon chip 2 will be described below with reference to FIGS. A silicon wafer 100 having a plane orientation (110) or (100) in which an N-type layer is epitaxially grown on an N-type semiconductor substrate or a P-type semiconductor substrate is prepared, and heat-treated (800 to 1100 ° C., O ₂ or wet O _2). Oxidation) and SiO of 5000-10000Å
_{2 The} film 1000 is formed (FIG. 11A).

Next, a resist pattern 1100 having an opening for a lead-out resistance portion is formed, and the oxide film 1000 is selectively removed by wet etching using an HF-based solution or dry etching using CF ₄ gas. Two
Then, a P-type region of 00 is formed (FIG. 11B). Next, a resist pattern 1200 having openings on and around the diaphragm is formed, and the oxide film 1000 is selectively removed by wet etching or dry etching as shown in FIG. 11C.

Next, after removing the resist pattern 1200, wet oxidation or dry oxidation (800 to 1100) is performed.
℃, O ₂ or wet O ₂ oxidation) 500-200
A 0Å SiO ₂ film 400a is formed. After that, a resist pattern 130 opened on the gate resistance planned region.
0 is formed, boron is ion-implanted, and the strain gauge 3 is formed (FIG. 11D).

[0034] Thereafter, a resist pattern 1300 is removed, heat treatment at in POCl ₃ (900~1000 ℃, ₃
0-60 minutes) to diffuse phosphorus into the SiO ₂ film 400a to form a PSG film 400b. Through the above steps, the first protective film 400 made of an oxide film having a two-layer structure and excellent in environmental resistance is formed on the diaphragm (FIG. 11E).

Next, a resist pattern having an open contact portion is formed, and the first protective film 400 is selectively removed by wet or dry etching to form a contact hole. Then, the resist is removed and an aluminum film 500 is deposited on the entire surface to obtain the structure shown in FIG. Next, a resist pattern 1400 that covers the wiring portion and the diaphragm region is formed, wet etching (mixed solution of nitric acid and phosphoric acid) is performed to pattern the aluminum film 500 (FIG. 12B), and after removing the resist, The second protective film 600 is deposited (FIG. 12C).

Next, a resist pattern 1500 having an opening in the pad area is formed, and the second protective film 600 is selectively removed. (FIG.12 (d)). In addition to the above steps, the strain gauge 3 is manufactured by a normal semiconductor integrated circuit manufacturing process.
Processes for forming circuit parts other than the above are performed. After that, the diaphragm portion 1 is formed by well-known wet etching.
After forming a (FIG. 13A), the silicon chip 2 and the pedestal 1 are anodically bonded, and a half cut is performed to prevent characteristic variation due to dicing, and the dicing of the wafer 100 and the half dicing of the pedestal 1 are performed. Perform (FIG. 13B).

Next, after the adjustment of each element is completed by laser trimming of the wafer 100, it is cut into each chip.
Next, the chip is soldered to a stem (not shown) at a temperature of about 300 ° C., and then a metal cover is seal-welded to the stem (not shown) to complete the process. The amplifiers 41 and 42 described above are usually linear amplifier circuits using operational amplifiers, but it is needless to say that other amplifier circuits may be used. The subtraction circuit 43 is simply the amplified signal voltage V
It is preferable to use an inverting circuit for inverting 2'and an adding circuit by an operational amplifier for adding the output voltage thereof to the amplified signal voltage V1 ', but it is also possible to use a subtracting circuit using a differential amplifier circuit. .

(Modification) In the above embodiment, the shape of the space (semiconductor region) forming each circuit element and the center of gravity are line-symmetrical, but the shape of each metal wiring in the space (semiconductor region) is also the same. With line symmetry, variations in residual stress due to the difference in thermal expansion coefficient between the metal wiring and the insulating film or semiconductor adjacent thereto can be reduced. However, it is difficult to form the metal wiring itself in a perfect mirror image relationship due to the routing. In this case, it is effective to dispose a dummy metal wiring having no function at the same position as the counterpart metal wiring.

Further, the present invention can be applied to all semiconductor sensor with a built-in amplifier circuit of the type which outputs a difference between a pair of signal voltages, regardless of the pressure sensor.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor pressure sensor with a built-in amplifier circuit of the present invention.

FIG. 2 is a block circuit diagram of the sensor of FIG.

FIG. 3 is a diagram showing a first-stage amplifier circuit of amplifiers 41 and 42 in FIG.

4 is a chip plan view of the sensor of FIG. 1. FIG.

5 is a partially enlarged plan view of FIG.

FIG. 6 is a plan view of a prototype chip used in the sensor of this embodiment.

7 is a characteristic diagram showing variations in output characteristics of the chip of FIG.

FIG. 8 is a plan view of a conventional chip as a comparative example.

9 is a characteristic diagram showing variations in output characteristics of the chip of FIG.

FIG. 10 is a plan view of a chip of a sensor according to a modification.

FIG. 11 is a process chart sequentially showing the first half chip manufacturing process of the method for manufacturing a semiconductor pressure sensor according to the first embodiment of the present invention.

FIG. 12 is a process diagram sequentially showing the latter half of the chip manufacturing process following the process of FIG. 11;

FIG. 13 is a process diagram showing an assembly process that follows the process of FIG. 12;

[Explanation of symbols]

3 is a strain gauge (signal conversion unit), 41 and 42 are amplifiers (signal amplification units), 43 is a subtraction circuit (subtraction unit), 2 is a semiconductor chip, 1 is a pedestal (bonding member), and 410 is a first-stage amplification circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Showa, 1-1, Kariya city, Aichi prefecture, Nihon Denso Co., Ltd. Incorporated (56) Reference JP 59-217375 (JP, A) JP 3-270263 (JP, A) JP 63-98143 (JP, A) JP 2-220477 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01L 27/00 G01L 9/04 101 H01L 29/84

Claims (6)

(57) [Claims] 1. A signal converter that difference to output a pair of signal voltage corresponding to a predetermined physical quantity, a pair of signal amplifier for amplifying the two signal voltages separately, and amplified output from the two signal amplifier a semiconductor chip subtraction unit for outputting a difference voltage of the signal voltage is integrated on the surface, it is thermally bonded to the back surface of the semiconductor chip, the semiconductor chip
And a pedestal having a coefficient of thermal expansion different from that of the semiconductor chip.
A square shape having a supporting portion that is configured to be joined to the pedestal
And the pair of signal amplification units are formed in the chip of the semiconductor chip.
A line connecting the center point and the midpoint of the side of the semiconductor chip, or
Is a point at the center of the semiconductor chip and the semiconductor chip.
Is formed symmetrically with the line connecting the top of the
Individually in a pair of axisymmetric regions with approximately equal residual stress
A semiconductor pressure sensor with a built-in amplifier circuit characterized by being formed . 2. A semiconductor sensor with a built-in amplifier circuit according to claim 1, wherein both of the signal amplifying portions are arranged in line symmetry positions and within a range not more than half the distance from the center line to the side. Wherein the signal conversion unit is an amplifier circuit built-semiconductor sensor according to claim 1 Symbol placing a resistor bridge circuit including the diaphragm region or strain gauges disposed on the beam region in the semiconductor chip. Wherein said amplifier circuit built-semiconductor sensor according to any one of claims 1 to 3 first stage amplifier circuit for both signal amplifier is disposed in the symmetrical position. 5. A distance measured from the two-dimensional center of gravity of a first circuit element arranged in one of the first-stage amplifier circuits to a side of the semiconductor chip at a right angle to the side is d1, and the other one of the first-stage amplification circuits. The distance measured from the two-dimensional center of gravity of the second circuit element, which is arranged in the circuit to form a pair with the circuit element, to the side of the semiconductor chip, which is in line symmetry with the side, at a right angle to the side is d2. The difference between the two distances Δd = (d1
-D2) is the average of both distances dm = (d1 + d2) / 2 1
The amplifier circuit built-in type semiconductor sensor according to claim 4 , wherein the amount is less than 5%. 6. A semiconductor sensor with a built-in amplifier circuit according to claim 5, wherein the two-dimensional barycentric positions of the respective transistors and resistors of the first-stage amplifier circuits satisfy the distance condition.