JP3507646B2 - Signal transmission / reception circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmitting / receiving circuit device, and more particularly to an L having a bus for transmitting / receiving data signals.
It is suitable for SI.

[0002]

2. Description of the Related Art The power consumption P of a CMOS circuit is αi (0
≦ i ≦ n, the same applies to the range of the value of “i” hereinafter): switching probability of each signal line, CLi: load capacity of each signal line, α: switching probability of the entire bus, CL: load capacity of the entire bus, VS Where: signal amplitude, VDD: power supply voltage, fCLK: clock frequency, N: number of bus wirings, given by the following equation.

[0003]

[Equation 1] here,

[0004]

[Equation 2] Is.

FIG. 10 is a block diagram of a conventional signal transmitting / receiving circuit device having a bus for transmitting / receiving signals.

This signal transmission / reception circuit device generally has a combination circuit 101 and a tri-state buffer 102 on the transmission side.
, A bus 103, a buffer 104 on the receiving side, and a combinational circuit 105, and the bus 103 is composed of N bus lines.

Power consumption in the bus of the conventional signal transmitting / receiving circuit device as shown in FIG. 10 is expressed by the equation (1), and in this case, VS in the equation (1) is equal to VDD. The bus has the second largest load capacity after the clock and consumes a large amount of power. Therefore, the low power consumption of the bus greatly affects the low power consumption of the entire LSI.

VS which is one of the parameters of the equation (1),
That is, reducing the amplitude of the signal transmitted by the bus is very effective in reducing the power consumption of the bus. The amplitude of the signal transmitted by the bus can be reduced by using a pass transistor circuit and a sense amplifier.

[0009]

However, since the sense amplifier normally operates by a differential signal, when a small amplitude signal is used as a signal transmitted by the bus, a complementary signal is required, and the width of the bus is two. It doubles and increases the occupied area.

FIG. 11 is a block diagram when a differential small amplitude signal is used in a conventional signal transmitting / receiving circuit device having a bus for transmitting / receiving a signal.

This signal transmission / reception circuit device generally includes a combination circuit 111 on the transmission side and a small-amplitude differential signal generation circuit 112.
, A bus 113, a sense amplifier 114 on the receiving side, and a combinational circuit 115.

In this case, since the relationship between VS and VDD in the equation (1) is VS << VDD, the power P "BUS consumed by the bus is P" BUS = 2 × α × CL × VS × VDD × It becomes fCLK, which is greatly reduced.

However, the number of wires of the bus is 2N in order to transmit the differential signal, and the area occupied by the bus is shown in FIG.
It is twice as much as the case of. In order to reduce the area occupied by the bus, a method of transmitting data with a single signal line and receiving it with an inverter etc. without using complementary signals is also conceivable.
Since the resistance to noise is significantly deteriorated and it is easily affected by charge coupling, there is a problem in practical use from the viewpoint of reliability.

The present invention has been made in view of the above problems, and an object thereof is to suppress an increase in the occupied area of a bus and to reduce the switching probability of a circuit while ensuring a certain reliability. It is an object of the present invention to provide a signal transmitting / receiving circuit device having a configuration capable of achieving low power consumption in a bus.

[0015]

According to the signal transmitting / receiving circuit device of the present invention, a small-amplitude differential signal is used as a signal transmitted by a bus, and data signals are grouped into data signals of 2 bits or more, One of the grouped data signals is transmitted / received as a small-amplitude differential signal, and the other data signal is transmitted / received by a signal indicating the relationship with the one data signal. It is possible to reduce power consumption in the bus while suppressing an increase in area and ensuring a certain level of reliability. In addition, by converting the relationship between one data signal and another data signal and transmitting / receiving the signal, the switching probability of the circuit can be reduced and the power consumption can be reduced. Specifically, for example, one of the grouped data signals of 2 bits or more is transmitted / received by a differential small-amplitude signal, and a signal line or a small-amplitude differential signal newly prepared in relation to other data signals. Of the pre-charge potential or the relative potential of the small amplitude differential signal with respect to the reference potential, or the time division signal using the small amplitude differential signal is transmitted and received, and this configuration suppresses an increase in the occupied area of the bus. At the same time, it is possible to reduce the power consumption of the bus while ensuring a certain level of reliability.

Among the data signals whose codes are extended in the data bus inside the arithmetic processing unit, an arbitrary 1-bit data signal is transmitted / received as a small-amplitude differential signal for a portion in which a plurality of data signals have a predetermined relationship. , The remaining bit data signal is transmitted and received in relation to the 1-bit data, and with this configuration, in the relation signal that needs to be transmitted and received with the signal having the maximum amplitude, the code of the data to be transferred is Even if it changes, the signal potential does not change significantly, and low power consumption can be achieved.

It seems that the data bus / address bus inside the arithmetic processing unit will follow an increasing trend in the next few years, but the entire bus width is not always used.
In many cases, only a part is used, and in that case, a stuffing for filling a 0 or 1 data signal is performed in an unused part (often in 4 or 8 or 16 bit units). By transmitting and receiving the relationship between the small-amplitude differential signal of an arbitrary data signal and the remaining data signal in the signal transmitting / receiving circuit device according to the present invention to such a portion, the data signal The potential of the signal line for transmitting the relation between them is hardly changed, and low power consumption can be achieved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a signal transmitting / receiving circuit device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a signal transmitting / receiving circuit device according to a first embodiment of the present invention. Specifically,
It is the figure which showed the structure in the case of transmitting / receiving either one of the grouped 2-bit data by a differential small amplitude signal, and transmitting / receiving by the newly prepared signal line with respect to the other data.

The signal transmission / reception circuit device according to the first embodiment of the present invention shows the relationship between the data signal D2i (0≤i≤n, the range of the value of "i" is the same below) and D2i + 1. EX-NOR (Exclusive-NO) that generates the relation signal Relation2i
R) circuit 11i and data signal D based on data signal D2i
a small-amplitude differential signal generation circuit 12i that generates ata2i and / Data2i (the symbol "/" indicates logical inversion. The same applies below), a relational signal line Relation2i that transmits a relational signal Relation2i, and a data signal. Data signal lines Data2i and / Data2i for transmitting Data2i and / Data2i, and data signal Da
It comprises a sense amplifier 13i for detecting ta2i and / Data2i, and a multiplexer 14i for restoring the data signal D2i + 1 based on D2i and / D2i restored by the sense amplifier and the relation signal Relation2i.

In the signal transmitting / receiving circuit device according to the first embodiment of the present invention, the data signals D0 and D1 are transmitted via the bus as follows.

First, the data signals Data0 and / Data0 are generated based on the data signal D0 through the small amplitude differential signal generation circuit, and the data signals Data0 and / Data0 are generated as the small amplitude differential signals and the data signal line Data0 of the bus. And output to / Data0. The data signals Data0 and / Data0 from the data signal lines Data0 and / Data0 of the bus are received and amplified by the sense amplifier to restore the data signal D0. that time,
The data signal / D0 which is the inverted signal of the data signal D0 is also restored.

On the other hand, the relationship between the data signal D0 and the data signal D1 is discriminated by the EX-NOR (Exclusive-NOR) circuit, and the result is output to the related signal line Relation0 as the related signal Relation0. Relation signal Relation0
Is a signal that is fully swung by a normal signal line. Data signals D0 and / D0 restored by the sense amplifier
Is input to the multiplexer, and either the data signal D0 or / D0 is selected by the relation signal Relation0, and the data signal D1 is determined.

The data signals D2i and D2i + 1 are likewise transmitted via the bus. That is, first, the data signals Data2i and / Data2i are generated based on the data signal D2i via the small-amplitude differential signal generation circuit, and the data signals Data2i and / Data2i are generated as the small-amplitude differential signals, and the data signal lines Data2i and Data2i of the bus are generated. It is output to / Data2i. Data signals Data2i and / Da from the data signal lines Data2i and / Data2i of the bus
ta2i is received and amplified by the sense amplifier, and the data signal D2i is restored. At that time, the data signal / D2i which is the inverted signal of the data signal D2i is also restored.

On the other hand, the data signal D2i and the data signal D2i + 1
Is determined by an EX-NOR (Exclusive-NOR) circuit, and the result is output to the relation signal line Relation2i as the relation signal Relation2i. Relation signal Relation2i
Is a signal that is fully swung by a normal signal line. Data signals D2i and / D2i restored by the sense amplifier
Is input to the multiplexer, and either the data signal D2i or / D2i is selected by the relation signal Relation2i to determine the data signal D2i + 1.

FIG. 2 is a block diagram of a signal transmitting / receiving circuit device according to the first embodiment of the present invention.
It is represented in a form corresponding to.

The signal transmission / reception circuit device according to the first embodiment of the present invention generally includes a combination circuit 21i on the transmission side, a small amplitude differential signal generation circuit and a signal relation determination circuit 22i,
Data signal lines Datai and / Datai and related signal lines Relati
It comprises a bus 25 consisting of on i, a receiving side sense amplifier and a related signal restoring circuit 23i, and a combination circuit 24i.

In the case of the signal transmitting / receiving circuit device according to the first embodiment of the present invention, the bus is (N / 2) × 2 = N data signal lines Data2i and / Data2i and N / 2 related signals. Since it is composed of the line Relation2i and is composed of a total of 1.5N wirings, the occupied area is 1.5 times that of the conventional configuration shown in FIG. However, as shown below, power consumption on the bus is reduced.

In the case of the conventional configuration shown in FIG. 10, the power P'BUS consumed by the bus is VS in the above equation (1).
= VDD, P'BUS = α × CL × VDD × VDD × fCLK. On the other hand, in the case of the signal transmission / reception circuit device according to the first embodiment of the present invention, the data signal lines Data2i and / or
The power consumed by Data2i is

[0030]

[Equation 3] And the power consumed by the relational signal line Relation2i is

[0031]

[Equation 4] Is. Therefore, in the case of the signal transmission / reception circuit device according to the first embodiment of the present invention, the power PBUS1 consumed by the bus
Is PBUS1 = α × CL × VS × VDD × fCLK + (1/2) × α × CL × VDD × VDD × fCLK = α × CL × VDD × fCLK × {(1/2) × VDD + VS}. Here, VS << VDD, so (1/2) × VDD
+ VS <VDD Therefore, PBUS1 <P'BUS, and the power consumption on the bus is reduced.

FIG. 3 is a circuit configuration diagram of a signal transmitting / receiving circuit device according to a second embodiment of the present invention.
A diagram showing a configuration in which one of grouped 2-bit data is transmitted / received by a differential small-amplitude signal, and the relationship with the other is transmitted / received by using precharge potentials of two different small-amplitude differential signals. Is.

The signal transmission / reception circuit device according to the second embodiment of the present invention is based on an EX-NOR (Exclusive-NOR) circuit 31i for discriminating the relationship between the data signals D2i and D2i + 1 and the data signal D2i. A small-amplitude differential signal generation circuit that generates the data signals Data2i and / Data2i and a precharge potential conversion circuit 32i that determines the precharge potential thereof, and a data signal line Da that transmits the data signals Data2i and Data2i + 1.
ta-2i and Data2i + 1, sense amplifier 33i that detects data signals Data2i and / Data2i, and EX-N that is a relationship between data signals D2i and D2i + 1 by amplifying data signal Data2i
A buffer 34i for restoring the OR logic signal and data signals D2i and / D2i and E restored by the sense amplifier.
And a multiplexer 35i for restoring the data signal D2i + 1 based on the X-NOR logic signal.

Vequal and Vdifferent are given as precharge potentials of the small amplitude differential signal, and VSS <Vdifferen
The relationship of t <(1/2) × VDD <Vequal <VDD is established.

In the signal transmitting / receiving circuit device according to the second embodiment of the present invention, the data signals D0 and D1 are transmitted via the bus as follows.

First, based on the data signal D0, the data signals Data0 and / Data0 are generated through the small-amplitude differential signal generation circuit, and the EX-NOR (Exclusive-NOR) circuit generates the data signals D0 and D1. The relationship is determined,
Data signal Data that becomes a small amplitude differential signal based on the result
The precharge level of 0 and / Data0 is determined.

FIG. 4 shows a data signal Data0 that is determined based on the relationship between the data signal D0 and the data signal D1 in the signal transmitting / receiving circuit device according to the second embodiment of the present invention.
5 is a graph showing the precharge level of / Data0. In the case of the second embodiment of the present invention, the data signal D0
And the data signal D1 are equal, the small-amplitude differential signal is V
When the data signal D0 and the data signal D1 are precharged to the equal potential, the small-amplitude differential signal is Vdiff.
Precharged to erent potential. When the data signal D0 and the data signal D1 are equal or different, when the data signal D0 = 0, Data0 <
/ Data0, Data0 when data signal D0 = 1> / Data0
Therefore, the data signals Data0 and / Data0 are output to the data signal lines Data0 and / Data0 of the bus as small-amplitude differential signals.

The data signals Data0 and / Data0 from the data signal lines Data0 and / Data0 of the bus are received and amplified by the sense amplifier to restore the data signal D0. At that time, the data signal / D0 which is the inverted signal of the data signal D0
Is also restored. For the precharge potential of the small-amplitude differential signal, VSS <Vdifferent <(1/2) × VDD <Vequal
Since the relationship of <VDD is established, the EX-NOR logic signal which is the relationship between the data signals Data0 and / Data0 can be restored by amplifying the data signal Data0 by the buffer. Using this EX-NOR logic signal, the data signal D1
Is restored.

FIG. 5 is a circuit configuration diagram of a signal transmitting / receiving circuit device according to a third embodiment of the present invention. Specifically,
A configuration is shown in which one of the grouped 2-bit data is transmitted / received by a differential small-amplitude signal, and the relation with the other is transmitted / received depending on whether the small-amplitude differential signal is higher or lower than the reference potential. It is a figure.

The signal transmission / reception circuit device according to the third embodiment of the present invention is based on an EX-NOR (Exclusive-NOR) circuit 51i for discriminating the relationship between the data signals D2i and D2i + 1 and the data signal D2i. A small-amplitude differential signal generation circuit 52i for generating the data signals Data2i and / Data2i, and a data signal D
Data signal lines Data2i and / Data2i for transmitting ata2i and / Data2i, a sense amplifier for detecting data signals Data2i and / Data2i, and a potential determination circuit 53i for detecting a potential for comparing with a reference potential Vref, and restoration by a sense amplifier Data signals D2i and / D2i and reference potential V
and a multiplexer 54i for restoring the data signal D2i + 1 from the result of comparison with ref.

In the signal transmitting / receiving circuit device according to the third embodiment of the present invention, the data signals D0 and D1 are transmitted via the bus as follows.

First, the data signals Data0 and / Data0 are generated based on the data signal D0 through the small amplitude differential signal generation circuit. Generation of a small-amplitude differential signal composed of the data signals Data0 and / Data0 is performed as follows.

FIG. 6 is a graph showing the relationship between the small-amplitude differential signal composed of the data signal lines Data0 and / Data0 and the reference potential in the signal transmission / reception circuit device according to the third embodiment of the present invention. . The data signal lines Data0 and / Data0 are precharged to the reference potential Vref, and when the data signal D0 and the data signal D1 are equal, the small amplitude differential signal is Vre.
The small-amplitude differential signal is generated on the high potential side of f, and when the data signal D0 and the data signal D1 are different, the small-amplitude differential signal is generated on the low potential side of Vref. The EX-NOR (Exclusive-NOR) circuit determines the relationship between the data signal D0 and the data signal D1, and the data signal D0 = 0 regardless of whether the data signal D0 and the data signal D1 are equal or different.
Data0 </ Data0 when, and when data signal D0 = 1
Due to the relationship of Data0> / Data0, the data signals Data0 and / Data0 are output to the data signal lines Data0 and / Data0 of the bus as small amplitude differential signals.

The data signals Data0 and / Data0 from the data signal lines Data0 and / Data0 of the bus are received and amplified by the sense amplifier to restore the data signal D0. At that time, the data signal / D0 which is the inverted signal of the data signal D0
Is also restored. The small-amplitude differential signal is restored by the sense amplifier, and the small-amplitude differential signal is restored to the reference potential V.
Whether the high-potential side or the low-potential side of ref is a small amplitude differential signal is detected, and the detection result and the data signal Data0
And / Data0 restores the data signal D1.

FIG. 7 is a block diagram of a signal transmitting / receiving circuit device according to the second or third embodiment of the present invention.
Alternatively, FIG. 5 is shown in a form corresponding to FIG. 10.

The signal transmission / reception circuit device according to the second or third embodiment of the present invention is roughly a combination circuit 71 on the transmission side.
i, a small-amplitude differential signal generation circuit and signal determination circuit and precharge potential conversion circuit 72i, a bus 75 including data signal lines Datai and / Datai, and a reception side sense amplifier and precharge potential determination circuit and signal restoration circuit 73i
And a combinational circuit 74i.

In the case of the signal transmitting / receiving circuit device according to the second or third embodiment of the present invention, the bus is (N / 2) × 2 =
Since it is composed of N data signal lines Data2i and / Data2i, the occupied area is one time that of the conventional configuration shown in FIG. On the other hand, as shown below, power consumption in the bus is reduced. For power consumption PBUS2 in the second or third embodiment of the present invention, the following equation approximately holds.

[0048]

[Equation 5] Here, since VS << VDD, PBUS2 <P'BUS, and the power consumption on the bus is reduced.

FIG. 8 is a circuit configuration diagram of a signal transmission / reception circuit device according to a fourth embodiment of the present invention. Specifically,
The differential small-amplitude signal is time-divided into the first half and the latter half of each cycle, and either one of the grouped 2-bit data is transmitted / received as the differential small-amplitude signal in the first half of each cycle, and the relationship with the other is It is the figure which showed the structure at the time of transmitting / receiving by the differential small amplitude signal of the latter half of each period.

The signal transmitting / receiving circuit device according to the fourth embodiment of the present invention includes an EX-NOR (Exclusive-NOR) circuit 81i for discriminating the relationship between the data signals D2i and D2i + 1, and the data signals D2i and EX. A selector 82i to which the output of the NOR circuit 81i and the clock signal CLK are input, and data signals Data0 and / Data0 based on the output of the selector 82i
A small-amplitude differential signal generation circuit 83i for generating the data signal, data signal lines Data0 and / Data0 for transmitting the data signals Data0 and / Data0, and data signals Data0 and / Data0 are detected and amplified to obtain a logic signal corresponding to Data0. And a latch 85i that restores the data signal D2i based on the logic signal output from the sense amplifier 84i.
And the data signals D2i and / D generated from the output of the latch
2i and a selector 86i for restoring the data signal D2i + 1 from the data signals Data0 and / Data0.

In the signal transmitting / receiving circuit device according to the fourth embodiment of the present invention, the data signals D0 and D1 are transmitted via the bus as follows.

First, the output of the EX-NOR (Exclusive-NOR) circuit which receives the data signals D0 and D1 and the data signal D0 are input to the selector. The output of this selector is selected by the clock signal CLK. The EX-NOR circuit receives the data signal D0 in the first half of each cycle of the clock signal CLK and the data signals D0 and D1 in the second half of each cycle of the clock signal CLK. Each calculation result is output.

FIG. 9 is a graph showing the output signals of the first half and the second half of each cycle of the clock signal CLK in the signal transmitting / receiving circuit device according to the fourth embodiment of the present invention.
Data signal D0 in the first half of each cycle of clock signal CLK
Is Data0> / Data0 when D0 = 1 and when D0 = 0
Clock signal CL is output in the relation of Data0 </ Data0
The operation result of the EX-NOR circuit which inputs the data signals D0 and D1 in the latter half of each cycle of K is Data0> / Data0 when D0 and D1 are equal, and Data0 </ Data0 when D0 and D1 are different. Is output in relation to. The output of the selector selected by the clock signal CLK is the data signal of the small amplitude differential signal through the small amplitude differential signal generation circuit.
Data0 and / Data0 as bus data signal line Data0
And output to / Data0.

The data signals Data0 and / Data0 from the data signal lines Data0 and / Data0 of the bus are received and amplified by the sense amplifier, and the logic signal corresponding to Data0 is output as the data signal D0. That is, Data0> / Da
If ta0, D0 = 1; if Data0 </ Data0, D0
0 = 0 is output. The output of the sense amplifier becomes the data signal D0 in the first half of each cycle of the clock signal CLK,
In the latter half, the EX-NOR logical result of the data signals D0 and D1 is obtained.

The data signal D0 in the first half of each cycle of the clock signal CLK is latched by the latch, and this data signal D0 becomes the data signal D0 as it is. The role of the latch is to hold the value of the data signal D0 even in the latter half of each cycle of the clock signal CLK. Data signals D0 and / D0 are generated from the data signal D0 which is the output of the latch and are input to the selector.

The output from the sense amplifier in the latter half of each cycle of the clock signal CLK shows the relationship between the data signals D0 and D1. Therefore, by inputting this signal to the selector, either of the data signals D0 and / D0 is detected. Is selected and the data signal D1 is restored.

In the case of the signal transmission / reception circuit device according to the fourth embodiment of the present invention, the bus is (N / 2) as in the case of the signal transmission / reception circuit device according to the second or third embodiment.
Since × 2 = N data signal lines Data2i and / Data2i are formed, the occupied area of the bus is equivalent to that of the conventional configuration shown in FIG. 10, but the power consumption of the bus is reduced.

In each of the embodiments described above, one of two continuous (bit) data signals is transmitted and received as a small amplitude differential signal, and the other data signal is related to the one data signal. Although the case of transmitting and receiving as a signal has been described, three or more (bit) data signals are grouped into one group (bit) of each group.
May be transmitted and received as a small-amplitude differential signal, and the remaining data signals may be transmitted and received as a relational signal with the one (bit) data signal.

The plurality of data signals to be grouped need not necessarily be continuous data signals.

For example, when transmitting data on a 32-bit wide bus, four 8-bit data are the 0th to 7th data, the 8th to 15th data, and the 16th data. If packed with the 23rd to the 23rd data and the 24th to the 31st data respectively, the 0th, 8th, 16th, and 24th data are grouped into Group the 9th, 9th, 17th, and 25th data,
Similarly, grouping may be performed below, and any one of the data in each group may be transmitted / received as a small-amplitude differential signal, and the remaining data may be transmitted / received as a relational signal with the one data. .

Similarly, when transmitting data through a 64-bit wide bus, eight 8-bit data are the 0th to 7th data, the 8th to 15th data, and the 8th data. 16th to 23rd data, 24th to 31st data, 32nd to 39th data, 40th to 47th data, 48th to 55th data Data up to
If each of the 56th to 63rd data is packed, the 0th, 8th, 16th,
The 24th, 32nd, 40th, 48th, 56th data are grouped into 1st, 9th, 17th, 25th, 33rd, 41st, and Group the 49th and 57th data,
Similarly, grouping may be performed below, and any one of the data in each group may be transmitted / received as a small-amplitude differential signal, and the remaining data may be transmitted / received as a relational signal with the one data. .

[0062]

According to the signal transmission / reception circuit device of the present invention, data signals of 2 bits or more are grouped and any one of the data signals of each group is transmitted / received as a differential small amplitude signal. , A signal line that newly prepares the relationship between the one data signal and another data signal, or the precharge potential of the small-amplitude differential signal, or the relative potential of the small-amplitude differential signal with respect to the reference potential, or the small-amplitude difference. Since it is decided to transmit and receive by time-division signals using dynamic signals, it is possible to achieve low power consumption in the bus by using a small amplitude differential signal as the signal transmitted by the bus, and the bus width is the same as the conventional one. To 1.5 times the width, and because a differential signal is used, a certain degree of reliability can be ensured.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a signal transmission / reception circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a signal transmission / reception circuit device according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a signal transmission / reception circuit device according to a second embodiment of the present invention.

FIG. 4 is a graph showing precharge levels of data signals Data0 and / Data0 determined based on a relationship between data signal D0 and data signal D1 in the signal transmitting / receiving circuit device according to the second embodiment of the present invention. .

FIG. 5 is a circuit configuration diagram of a signal transmission / reception circuit device according to a third embodiment of the present invention.

FIG. 6 is a graph showing a relationship between a small-amplitude differential signal composed of data signal lines Data0 and / Data0 and a reference potential in the signal transmission / reception circuit device according to the third embodiment of the present invention.

FIG. 7 is a block diagram of a signal transmission / reception circuit device according to a second or third embodiment of the invention.

FIG. 8 is a circuit configuration diagram of a signal transmission / reception circuit device according to a fourth embodiment of the present invention.

FIG. 9 is a graph showing output signals in the first half and the second half of each cycle of the clock signal CLK in the signal transmission / reception circuit device according to the fourth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional signal transmitting / receiving circuit device having a bus for transmitting and receiving signals.

FIG. 11 is a block diagram when a differential small-amplitude signal is used in a conventional signal transmitting / receiving circuit device having a bus for transmitting / receiving a signal.

[Explanation of symbols]

11, 31, 51, 81 EX-NOR circuit 14, 35, 54 Multiplexer 12, 52, 83, 112 Small amplitude differential signal generation circuit 13, 33, 84, 114 Sense amplifier 21, 71, 101, 111 Transmit side Combination circuit 22 Small-amplitude differential signal generation circuit and signal relation determination circuit 23 Reception side sense amplifier and related signal restoration circuit 24, 74, 105, 115 Reception-side combination circuit 32 Small-amplitude differential signal generation circuit and precharge Potential conversion circuit 34 buffer 53 sense amplifier and potential determination circuit 72 small-amplitude differential signal generation circuit and signal determination circuit and precharge potential conversion circuit 73 reception side sense amplifier and precharge potential determination circuit and signal restoration circuits 82, 86 selector 85 latch 102 tri-state buffer 23, 73, 103, 113 bus 1 4 buffer

Continuation of the front page (56) References JP 9-8862 (JP, A) JP 7-74787 (JP, A) JP 6-152608 (JP, A) Toshihiro Terazawa, Akihiko Chiba, Yoshinori Watanabe , Hiroyuki Hara, Koji Matsuda, Two-dimensional IDCT macrocell using a two-time clock accumulator, 1996 IEICE Electronics Society Conference Proceedings 2, Japan, The Institute of Electronics, Information and Communication Engineers, 1996 8 30th, 170 Takami Shimazawa, Hiroyuki Hara, 13 others, 200 MHz image compression / expansion macrocell using sense amplifier-flip-flop, IEICE technical report, Japan, The Institute of Electronics, Information and Communication Engineers, 1994 4 21st, Vol. 94 No. 16, p57-64 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/40 310 G06F 3/00 WPI (DIALOG)

Claims (7)

(57) [Claims] 1. A signal transmitting / receiving circuit device having a signal line for transmitting / receiving a data signal, wherein the data signal to be transmitted / received is grouped into data signals of 2 bits or more, and any one of the grouped data signals is grouped. And a circuit for transmitting and receiving the data signal of the bit as a small amplitude differential signal, and transmitting and receiving the data signal of the remaining bits of each group as a relational signal indicating a relationship with the data signal transmitted and received as the small amplitude differential signal And a circuit for controlling the signal transmission / reception circuit device. 2. A signal transmission / reception circuit device having a signal line for transmitting / receiving a data signal, wherein the data signal to be transmitted / received is grouped for each data signal of 2 bits or more, and any one of the grouped data signals A circuit for converting a 1-bit data signal into a small amplitude differential signal, a signal line for transmitting the converted small amplitude differential signal, and the 1-bit data signal converted into the small amplitude differential signal And a circuit for respectively discriminating the relation between the 1-bit data signal and other data signals of the respective groups, a signal line for transmitting the result of discriminating the relation as a relational signal, and the transmitted small amplitude difference. A circuit for amplifying a motion signal, and a circuit other than the 1-bit data signal transmitted by the small amplitude differential signal using the transmitted related signal Signal transmitter apparatus characterized by comprising a circuit for generating a data signal. 3. A signal transmission / reception circuit device having a signal line for transmitting / receiving a data signal, wherein the data signal to be transmitted / received is grouped for each data signal of 2 bits or more, and any one of the grouped data signals A circuit for converting a 1-bit data signal into a small-amplitude differential signal, and the 1-bit data signal converted into the small-amplitude differential signal and other data of each group to which the 1-bit data signal belongs A circuit for discriminating the relationship with the signal, a circuit for sequentially precharging the small-amplitude differential signal to one of two different potentials according to the result of discriminating the relationship, and the converted small-amplitude difference. A signal line for transmitting a motion signal, a circuit for amplifying the transmitted small-amplitude differential signal, and a preamplifier to which the potential of the small-amplitude differential signal is applied. A circuit for sequentially determining whether or not the data has been transferred and transmitted, and a circuit for generating the other data signal other than the 1-bit data signal transferred by the small-amplitude differential signal according to the result of the determination of the potential. A signal transmitting / receiving circuit device characterized by being provided. 4. A signal transmission / reception circuit device having a signal line for transmitting / receiving a data signal, wherein the data signal to be transmitted / received is grouped for each data signal of 2 bits or more, and any one of the grouped data signals. A circuit for converting a 1-bit data signal into a small-amplitude differential signal, and the 1-bit data signal converted into the small-amplitude differential signal and other data of each group to which the 1-bit data signal belongs A circuit for discriminating the relationship with each of the signals, precharging the small-amplitude differential signal to a predetermined reference potential, and depending on the result of discriminating the relationship, respectively, a higher potential side or a lower potential side than the predetermined reference potential. A circuit for sequentially generating the small-amplitude differential signal, a signal line for transmitting the converted small-amplitude differential signal, and the transmitted small-amplitude A circuit that amplifies the dynamic signal, a circuit that determines whether the potential of the small-amplitude differential signal is higher or lower than the predetermined reference potential, and a circuit that amplifies the small-amplitude differential signal according to the determination result of the potential. And a circuit for generating the other data signal other than the transmitted 1-bit data signal. 5. A signal transmission / reception circuit device having a signal line for transmitting / receiving a data signal, wherein the data signal to be transmitted / received is grouped for each data signal of 2 bits or more, and any one of the grouped data signals. Or 1-bit data signal and 1
A circuit that respectively determines the relationship between the bit data signal and other data signals of each group, and time division of each cycle of the clock signal into the same number as the number of the plurality of bits, and the 1-bit data signal and the A circuit for sequentially outputting a result of discriminating the relationship, a circuit for converting the output 1-bit data signal and a result of discriminating the relationship into a small amplitude differential signal, and the converted small signal A signal line for transmitting an amplitude differential signal, a circuit for amplifying the transmitted small amplitude differential signal, a circuit for holding the amplified small amplitude differential signal, and the transmitted 1-bit data signal And a circuit for generating the other data signal other than the 1-bit data signal based on the result of discriminating each of the relations and the relation. . 6. The signal transmitting / receiving circuit device according to claim 1, wherein the grouping performed for each of the data signals of 2 bits or more is performed for each of continuous 2 bit data signals. A signal transmitting / receiving circuit device characterized by: 7. The signal transmission / reception circuit device according to claim 1, wherein the grouping performed for each of the data signals of 2 bits or more determines a predetermined one of the data signals to be transmitted / received. A signal transmission / reception circuit device, characterized in that the signal transmission / reception circuit device is carried out in combination.