JP3506965B2 - Vertical transistor fabrication process - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a fabrication process for vertical transistors.

[0002]

BACKGROUND OF THE INVENTION In integrated circuits, device density tends to be higher in order to increase the number of devices per unit area. Device density is increased by making individual devices smaller and placing them closer together. Device dimensions (called geometry or design rules) are decreasing from 0.25 μm to 0.18 μm, and even smaller. It is also desirable to reduce the distance between devices with the same size.

Currently, most MOS (metal-oxide-
Semiconductor) transistors have a flat shape. In planar MOS devices, the direction of current flow is parallel to the substrate surface. While it is necessary to reduce the size of these devices in order to increase device density, it is becoming increasingly difficult to make these small devices. In particular, lithography becomes extremely difficult when the device dimensions are smaller than the wavelength of the radiation used to image the pattern in the radiation sensitive material.

According to Takato H et al., "Gate Surrounding Transistor (S
Impact of GT "IEE TRANSACTIONS ON ELECTRON DEVICE ( IEEE)
Transactionson Electron
Devices ) Volume 38 (3), 573-577 (1)
The vertical device configuration described in 991) proposes a device configuration that uses more space. A schematic of the device is shown in FIG. Device 10 is source 1
5, the length of the channel 25 with the drain 20 and the channel 25 is the substrate 30 on which the device is formed.
Perpendicular to the surface of. This device is called a vertical transistor because the length of the channel is perpendicular to the substrate surface. Gate 35 surrounds channel 25.

Vertical MOSFETs (metal-oxide-semiconductor field effect transistors) are
Although more densely packed, the vertical transistor process is not straightforward. Therefore, vertical MOSFE
A process that makes the fabrication of T easier and more efficient is desired.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a vertical MOSFET fabrication process. In this process, a first layer of electrically insulating material such as silicon nitride (SiO ₃ N ₄ ) is formed on a semiconductor substrate. Examples of suitable semiconductor substrates include silicon substrates and silicon on insulating substrates (SOI). The surface region of the silicon substrate is heavily doped (ie, the dopant concentration is 1
× 10 ¹⁹ atoms / cm ^{3 or more} ). The first layer of insulating material has a thickness in the range of about 25 nm to about 250 nm. The thickness of the first layer is selected such that the gate-source capacitance (Cgs) between the gate and the source or drain (depending on whether the source or drain is formed on the substrate) is sufficiently low. It According to this idea, thicknesses in the higher part of the range mentioned above are preferred. The thickness of the first layer is also such that the series resistance of the source / drain extensions is sufficiently low and due to outdiffusion from the heavily doped region of the substrate:
The source / drain extensions are chosen to be easily formed. Based on these considerations, the thickness within the lower portion of the above range is preferred. One of ordinary skill in the art can select an appropriate thickness based on the above considerations, as well as other considerations that apply to particular embodiments.

A second layer of material is formed on the first layer of material. However, the material of the second layer (eg, silicon dioxide (SiO ₂ )) has a significantly different etch resistance for the selected etchant than the insulating material of the first layer. Specifically, for the selected etchant, the etch rate of the material of the second layer is much higher than the etch rate of the insulating material of the first layer. if,
Advantageously, the etch rate of the second layer of material in the selected etchant is at least about 10 times the etch rate of the first layer of material. For a selected etchant, the etch rate of the material of the second layer is at least 10 times faster than the etch rate of the semiconductor material in which the channel of the device is formed, crystalline silicon being an example of such a semiconductor material. Is. Advantageously, the etching rate of the material of the second layer is at least 100 times faster than the etching rate of the semiconductor material.

The thickness of the second layer of material is selected to define the physical gate length of the device. That is what this second layer sacrifices, ie it is removed,
This is because the device gate is formed in the space defined by this layer. Defining the gate length in this manner allows for much better gate length control than can be obtained using conventional lithographic techniques.

A third layer of material is formed on the second layer. The material selected for the third layer is an electrically insulating material. It is advantageous if the insulating material in the third layer has a lower etch rate in the selected etchant than the material of the second layer. Advantageously, the ratio of the etching rate of the material in the second layer to the etching rate of the material in the third material layer in the selected etchant is at least 1:10. For ease of processing, it is advantageous if the material of the first layer is the same as the material of the third layer.

Next, windows or trenches (hereinafter simply referred to as windows) are etched through the three-layer structure down to the heavily doped surface of the silicon substrate. The size of the window is determined by the dimensional constraints for the particular device and the limitations of the lithographic techniques used to form the window. The window is formed using conventional lithographic techniques. Specifically, by forming a layer of energy definable material, a mask is formed on the three-layer structure to introduce an image of the pattern into the energy definable material layer. The pattern is then developed and the only portion of the tri-layer structure exposed through the mask is the portion that corresponds to the desired window or groove size and location. The windows are then etched into the tri-layer structure. After the window is etched, the portion of the mask that remains on the substrate surface is removed using conventional means well known to those skilled in the art.

Next, the window is filled with a semiconductor material. The semiconductor material is crystalline, polycrystalline or amorphous, but typically the semiconductor material is a crystalline material such as silicon, silicon-germanium or silicon-germanium-carbon. The crystalline semiconductor material is either doped or undoped.
Techniques for forming crystalline semiconductor material within windows are well known to those skilled in the art. For example, in one technique, crystalline material is epitaxially formed within a window or trench. In another embodiment, an amorphous layer of semiconductor material is formed on the substrate, but all but the semiconductor material deposited in the window and a small plug on the top in the window is removed. The amorphous semiconductor material is then annealed (solid phase epitaxy) in order to crystallize the material.

The device channel and device source and drain extensions are formed in a semiconductor (eg, silicon) plug formed in the window. Therefore, the silicon plug is doped in some areas. Various methods for doping the silicon plug are considered suitable.
In one embodiment, the doped silicon plug is formed in-situ during growth, by implantation after the plug is formed, or another suitable method. Opposite into the plug from one or more adjacent layers of material (ie, layers of material in which a window full of crystalline semiconductor is formed) to form source and drain extensions. Shaped dopants can be driven away. This technique is known as solid phase diffusion. In solid phase diffusion, a doped oxide (eg silicon dioxide) is used as the dopant source. The silicon dioxide is doped with the desired dopant (eg arsenic, phosphorus, boron). At elevated temperatures, the dopants are driven out of the doped oxide into the adjacent crystalline semiconductor material. This technique is advantageous because the doped region is defined by the interface between the plug and the layer of material used as the dopant source. This technique allows the formation of self-aligned source / drain extensions (ie, source and drain extension regions aligned with the gate).

Those skilled in the art are familiar with the manner in which dopants are introduced at the same time as the material layer is formed through chemical vapor deposition, and such techniques will not be discussed in detail here. Generally, the dopant is introduced into the atmosphere at a suitable point during the deposition of the material so that the dopant is present at the desired location in the silicon plug and in the desired concentration. In another embodiment, after the channel is formed,
Alternatively, after diffusing from the heavily doped substrate into the bottom of the plug, the dopant is injected into the channel.

After the doped silicon (or other semiconductor) plug is formed, a fourth layer of material is formed on the substrate. The layer of material has an etch resistance in the selected etching means that matches the etch resistance of the first and third layers of material. From a process perspective, it is advantageous that this layer of material is the same as the third material layer.

Another etch mask is formed on the substrate using conventional lithographic techniques. The etching mask is patterned such that portions of the fourth material layer on the silicon plug and portions of the fourth material layer adjacent to the plug are not exposed through the mask. The resulting mask structure is then anisotropically etched down to the second material layer. As a result of the etching, a second portion below the unmasked portion of the structure is exposed. The resulting structure is then isotropically etched. As a result of the etching and the difference in etching rate between the second material layer and the first and third material layers, the second material layer is completely removed,
Third layer adjacent to the top on the material layer and the silicon plug of
/ The part of the fourth material layer remains. As a result of this etching,
The portion of the silicon plug corresponding to the thickness of the second layer is exposed. The exposed portion of the silicon plug defines the gate length of the device being formed.

The substrate is then placed on the exposed portion of the silicon plug under conditions where a layer of thermal oxide is grown. The thermal oxide layer is then removed using conventional means such as wet etching (such as aqueous hydrofluoric acid) or anhydrous hydrofluoric acid. This sacrificial oxidation is done to repair the sidewall defects. After the thermal oxide layer is removed, a layer of gate dielectric (eg, silicon dioxide or other suitable high dielectric constant material) is formed on the exposed portion of the silicon plug. Other suitable gate dielectric materials include silicon dioxide, silicon nitride, silicon oxynitride and metal oxides (eg,
Tantalum pentoxide, titanium oxide and aluminum oxide). The thickness of the gate dielectric is about 1 nm to about 20 nm. The thickness selected depends on the dielectric constant of the dielectric material.

In one embodiment, a silicon dioxide gate dielectric layer is formed by heating the substrate to a temperature in the range of about 700 ° C. to about 1100 ° C. in an atmosphere containing oxygen. Both furnace oxidation and rapid thermal oxidation are considered suitable. Other means such as chemical vapor deposition, jet vapor deposition or atomic layer deposition are also considered suitable for forming the gate dielectric. The conditions for forming a desired thickness of gate dielectric are well known to those skilled in the art.

The gate electrode is then formed by depositing a well-matched layer of a suitable gate material (eg, in-situ doped amorphous silicon) on the substrate. The layer is patterned and then recrystallized to form the gate. The gate morphology is largely a design choice. However, the gate surrounds a portion of the silicon plug with the gate oxide formed above.

[0019]

DETAILED DESCRIPTION The present invention relates to a fabrication process for vertical transistors. In the process, multiple layers of material are formed on the surface of a silicon substrate in which the source or drain regions are formed. The multiple layers have different etch resistances in the selected etching means. One of the layers in the multi-layer structure is a sacrificial layer used to define the physical gate length of the device. Specifically, the thickness and location of the sacrificial layer determines the thickness and location of the gate of the vertical transistor.

2A-2J for one embodiment of the present invention.
Will be described with reference to. Referring to FIG. 2A, heavily doped source region 105 is formed in silicon substrate 100. In this example, the source region of the device is formed in the silicon substrate and the drain region is formed on top of the subsequently formed vertical channel. In another embodiment, the drain region is formed in the substrate and the source region is formed on top of the subsequently formed vertical channel. For an embodiment where the source region is formed in the substrate,
Described here. From this description, those skilled in the art will be able to easily form a device in which the drain region is formed in the silicon substrate and the source region is formed on top of the vertical channel that is subsequently formed.

The heavily doped source region, the concentration of dopant therein and the type of dopant (ie n-type or p-type).
Shape) are all design choices. The dopant is phosphorus (P), arsenic (As), antimony (Sb) or boron (B), and the dopant concentration is about 1 × 10 ¹⁹ atoms / c.
In the range of m ^{3 to} about 5 × 10 ²⁰ atoms / cm ³ , highly doped source regions 105 where the depth of the region in the substrate is less than about 200 nm is considered suitable.

Referring to FIG. 2B, three layers of material 11
0, 115 and 120 are formed on the heavily doped source region 105 in the silicon substrate 100. The first layer 110 of material is electrically insulating, such as Si ₃ N ₄ . Material layer 110 electrically isolates deep source region 105 from the top gate electrode (155 in FIG. 2J). Thus, the material layer 110 is made of a material suitable for this purpose and has a thickness. About 25nm to about 250nm
A thickness in the range of is considered suitable for the material layer 110.

The second layer of material 115 is the first layer of material 11
Formed on 0. However, the material of the second layer 115 has a significantly different etch resistance for the selected etchant than the insulating material of the first layer 110. Specifically, for the selected etchant, the etch rate of the material of second layer 115 is much higher than the etch rate of the insulating material of first layer 110. Advantageously, for the selected etchant, the etch rate of the material of second layer 115 is significantly higher than the etch rate of the semiconductor material in which the device channel is formed (ie, 130 in FIG. 2D). . Crystalline silicon is an example of a suitable semiconductor plug material.

The thickness of the second layer 115 of material defines the physical gate length of the device. This is this second layer 115
Is sacrificed, that is, it is removed and the gate of the device is formed in the space defined by this layer. When the sacrificial second layer 115 is removed, a gate oxide (150 in FIG. 2H) is formed over the gate channel.

A third layer 120 of material is formed on the second layer 115. The material selected for the third layer 120 is an electrically insulating material. It would be advantageous if the insulating material in the third layer 120 had a lower etch rate than the material of the second layer 115 in the selected etchant.
If in the selected etchant, layer 1 of the third material
Advantageously, the ratio of the etching rate of the material in the second layer 115 to the etching rate of the material in 20 is at least about 1:10.

Referring now to FIG. 2C, the window or groove 125
An opening (for convenience, the window or groove is hereinafter simply referred to as the window) through the three layers 110, 115 and 120,
The heavily doped surface 105 of the silicon substrate 100 is also etched. The cross-sectional thickness of the window (horizontal dimension in the cross-section) is determined by the dimensional limitations for the particular device and the lithographic technique constraints used to form the window. The length of the groove (longitudinal as well as perpendicular to the horizontal dimension in the cross section) is primarily a design choice. For a given horizontal dimension of the cross section, the current through the conductor formed in the opening will increase with increasing groove length. The windows are formed using conventional lithographic techniques.

Referring to FIG. 2D, the window 125 is then filled with a single crystal semiconductor material such as silicon 130. Other examples of crystalline semiconductor materials include silicon-germanium and silicon-germanium-carbon. The crystalline semiconductor material is either doped or undoped. Techniques for forming crystalline semiconductor material within windows are well known to those skilled in the art. For example, the crystalline material is formed epitaxially within the window 125. In another example, an amorphous layer of semiconductor material is deposited on the surface of the substrate and the window 125 is used.
All but the semiconductor material 130 deposited therein and the small plug 131 at the top of the window 125 are removed. The amorphous semiconductor material is then annealed to recrystallize the material.

The semiconductor (eg, silicon) plug formed in window 125 becomes the channel for the device. Thus, the silicon plug 130 is doped to form a channel (also not shown) with source and drain extensions (not shown). One type (ie, n-type or p-type) of dopant is used to form the silicon plug 1 to form the source and drain extensions.
Introduced into 30 and oppositely shaped dopants are introduced into the plug to form a channel. Various methods of doping the silicon plug are considered suitable.
Doping at the same time that the silicon plug is formed or implanting the dopant after the silicon plug is formed is considered to be a suitable means.

Dopants can be driven into the single crystal silicon plug 130 by using layers 110 and 120 as a dopant source for the source and drain extensions. This technique is known as solid phase diffusion,
In that case an oxide (eg silicon dioxide) is used as the dopant source. Silicon dioxide is doped with the desired dopants (eg arsenic, phosphorus, boron). At elevated temperatures, the dopants are driven from the doped oxide into the adjacent undoped (or lightly doped opposite forms of dopant) crystalline semiconductor material. This technique is advantageous because the doped region is defined by the interface between the silicon plug 130 and the layers 110 and 120 of the material used as the dopant source.
This technique allows the formation of self-aligned source / drain extensions (ie, source / drain extensions are aligned with the gate). An example of a solid state diffusion technique is Ono, M., et al., “Sub 50 nm gate length N-MOSFET with 10 nm phosphorus source and drain junctions”.
IEDM 93 , 119-122
Page (1993) and Saito M (Saito, M)
Et al., "SPDD D-MOSFET structure suitable for 0.1 and sub-0.1 micron channel length and its electrical characteristics", IEDM 92,897-.
900 (1992). These are hereby incorporated by reference.

Those skilled in the art are familiar with the manner in which dopants are introduced at the same time that a layer of material is formed through chemical vapor deposition, and such techniques are not described in detail here. Generally, the dopant is introduced into the atmosphere at a suitable point during the deposition of the material so that the dopant is present at the desired location in the silicon plug and in the desired concentration.
In another embodiment, the dopant is implanted into the channel after it has been formed and diffused from the heavily doped substrate into the bottom of the plug to form the source / drain extension regions. Ion implantation is a suitable means of forming source / drain extension regions on top of the plug.

After the window 125 is filled with monocrystalline silicon 130 and the silicon 130 is doped in the desired manner, a fourth layer 135 of insulating material is shown in FIG. 2E.
It is formed on a substrate. Layer 135 is a material that is etch resistant in the selected etching means that matches the etch resistance of layers 110 and 120. Based on process considerations, layer 135 is advantageously the same material as the underlying layer 120. The silicon plug 130 is doped,
Once the dopant is distributed in the plug 130 in the desired manner, the substrate is not placed under conditions that significantly affect the distribution of the dopant in the silicon plug 130. Therefore, after this step, the substrate is not exposed to temperatures above 1100 ° C. After this point in the process, it is advantageous if the substrate is not exposed to temperatures above 1000 ° C. In some embodiments, after this point in the process, the substrate is not exposed to temperatures above 900 ° C. for extended periods (eg, minutes or longer). However, the substrate can be rapidly thermal annealed at temperatures up to about 1000 ° C. without adversely affecting the distribution of dopants in the silicon plug 130.

Another etch mask (not shown) is formed on the multilayer structure using conventional lithographic techniques. The etching mask is patterned such that the portion of the fourth material layer over the silicon-filled window and the portion of the fourth material layer adjacent the window are not exposed through the mask. The structure with the etching mask formed on it is then anisotropically etched using conventional dry etching means. In the dry etching process, the etching rates of the layers 110, 115, 120 and 135 are almost the same, and the layer 115 is similar to the layers 110, 120 and
It has an etching rate lower than 35. The structure resulting from this etching step is shown in FIG. 2F. As a result of this etching, the portions of layers 135 and 120 exposed through the mask are completely removed. Further, a part of the thickness of the portion of the layer 115 which is not covered with the mask is etched away.

Next, the substrate is wet-etched or dry-etched. The etch rate of layer 115 in this way is significantly faster than the etch rate of layers 110, 120 and 135. As shown in FIG. 2G, the selectivity of the etch in the wet etch means does not remove the major portion of layer 110 and the remaining portions of layers 120 and 135, but sacrificial layers between layers 110 and 120. Is
Completely removed. The top 14 of the silicon plug 130
The portions of layers 120 and 135 above it that are adjacent to 0 remain. As a result of this etching, the portion of the silicon plug 130 that corresponds to the thickness of layer 115 is exposed. Plug 1
The exposed surface 145 of 30 becomes the physical gate length of the device being formed.

The substrate is then heated in an oxygen containing atmosphere to grow a layer of thermal oxide (not shown) on the exposed surface of the crystalline silicon plug 130. The thin layer of thermal oxide is wet etched (eg,
It is removed using conventional means such as aqueous hydrofluoric acid). As a result of the formation and removal of sacrificial thermal oxides,
The surface of the silicon plug 130 is smooth, and some sidewall defects are removed. The specific conditions used to form and remove the sacrificial oxide are selected as needed to adjust the width of the silicon plug to the desired dimensions.

After the thermal oxide layer has been removed, a layer 150 of gate dielectric (eg, silicon dioxide, silicon oxynitride, silicon nitride or metal oxide).
Are formed on the exposed portion of the silicon plug 130. The thickness of the gate dielectric is about 1 nm to about 20 n.
m. In one embodiment, the silicon dioxide layer is formed by heating the substrate in an oxygen containing atmosphere to a temperature in the range of about 700 ° C to about 1100 ° C. Other means of forming the gate dielectric such as chemical vapor deposition, jet vapor deposition and atomic layer deposition are also considered suitable. The conditions for forming a desired thickness of gate dielectric are well known to those skilled in the art.

Referring to FIG. 21, the gate electrode is then formed by depositing a suitable layer 155 of a suitable gate material (eg, in-situ doped amorphous silicon). The amorphous silicon is then recrystallized using conditions that do not significantly affect the distribution of dopants in the silicon plug. Other examples of suitable gate materials include polycrystalline silicon, silicon-germanium and silicon-germanium-carbon. Metals and metal-containing compounds that have suitable close resistivities and are compatible with gate dielectric materials and semiconductor processes are also considered suitable gate materials. Advantageously, the gate material has a work function sufficiently close to the center of the forbidden band of the semiconductor plug material.
Examples of such metals include titanium, titanium nitride, tungsten, tungsten silicide, tantalum, tantalum nitride and molybdenum. Suitable means for forming the layer of gate material include chemical vapor deposition, electroplating and combinations thereof.

Referring to FIG. 2J, layer 155 is gate 1
Patterned to form 55. The gate morphology is largely a design choice. However, the gate is a gate oxide formed on it that surrounds a portion of the silicon plug.

Another embodiment will be described with reference to FIGS. 3A-3P. Referring to FIG. 3A, heavily doped source region 205 is formed in silicon substrate 200. One example of a suitable substrate 200 is a boron-doped silicon substrate. The concentration of boron dopant is about 2 ×
It is 10 ¹⁵ atoms / cm ³ . The deep source region, the concentration of dopant therein and the form of the dopant (ie n-type or p-type) are all by design choice. The dopant is antimony or arsenic, and the peak dopant concentration is 1 × 1.
The n ⁺ deep source region 205 having a depth of the doped region in the substrate of 0 ¹⁹ atoms / cm ³ or more and smaller than about 200 nm is
Considered appropriate.

Referring to FIG. 3B, five layers of material 21
0, 211, 215, 216 and 220 are formed on the deep source region 205 in the silicon substrate 200.
The first layer of material 210 is an electrically insulating material. Material layer 210 electrically isolates deep source region 205 from what will ultimately be the top gate electrode (265 in FIG. 3P). Therefore, the material layer 210 is made of a material suitable for this purpose and has a thickness. Examples of suitable materials include doped silicon oxide. In some embodiments, the first layer is also used as the dopant source. The dopant source is the vertical channel of the subsequently formed device (see FIG. 3).
It is used to dope C). One example of a silicon oxide doping source is PSG (phosphorus silicate glass, or phosphorus doped silicon oxide). Those skilled in the art are aware of suitable means (eg plasma enhanced chemical vapor deposition (CVD)) for forming a layer of PSG on a substrate. Suitable thickness is from about 25 nm to about 250 n
It is within the range of m.

On top of the first layer of material 210, the second layer of material 2
11 is formed. The second layer is intended as an etch stop. As known to those skilled in the art, the etch stop is designed to prevent etching from proceeding to the underlying layer or layers. Those skilled in the art will know that the choice of etch stop layer will depend on the specific etching means used to etch the overlying layer. In the process of the present invention, the upper layer is PSG and undoped silicon oxide (eg, silicon oxide is formed from tetraethylene orthosilicate (TEOS)).
And an etch stop material that effectively stops the etchant for such a material from penetrating into the underlying layers,
To be selected. Silicon nitride, Si ₃ N _4, is considered a suitable etch stop material. The thickness of the etch stop layer is highly dependent on the resistance of the etch stop material to the selected etchant (ie, to be an effective etch stop, within the time required to perform the etch, the etch stop layer is Cannot penetrate).

On top of the second layer of material 211, a third layer of material 2
15 is formed. However, the insulating material of the third layer 215 has a significantly different etching resistance for the selected etchant than the insulating material of the etch stop layer 211. Specifically, the etching rate of the insulating material of the third layer 215 is much higher than the etching rate of the insulating material of the etch stop layer 211 for the selected etchant.

The thickness of the third layer of material 215 is selected to correspond to the gate length of the device. Third to be sacrificed
A gate oxide (250 in FIG. 3M) is formed over what will become the channel 260 (FIG. 3P) of the device when layer 215 of FIG.

A fourth layer 216 of material is formed on the third layer 215. The fourth layer of material 216 has the same function as layer 211. Thus, the ideas governing the choice of material and thickness for layer 211 dominate the choice of material and thickness for layer 216.

A fifth layer 2 of insulating material is provided on the fourth layer 216.
20 is formed. It is advantageous if the insulating material in the fifth layer 220 has the same etch rate as the insulating material of the first layer 210 in the selected etchant. From the standpoint of facilitating the process, it is advantageous for the material of the first layer 210 to be the same as the material of the fifth layer 220.

Referring to FIG. 3C, five layers 210, 2
A window 225 is formed through 11, 215, 216 and 220 to the heavily doped region 205 in the silicon substrate 200. The window diameter is determined by the dimensional constraints of the particular device and the lithographic techniques used to form the window. The window is formed using conventional lithographic techniques. The window 225 is then chemically cleaned (eg, R to clean the silicon at the bottom of the window).
CA or piranha clean). After this cleaning step, a small portion of layers 210 and 220 adjacent window 225 is removed. The result of this etching is shown in FIG. 3D.

Referring to FIG. 3E, the window 225 is then filled with crystalline semiconductor material (eg, silicon) 230. Techniques for forming polycrystalline silicon in windows are well known to those skilled in the art. In one embodiment, amorphous silicon is deposited over the entire substrate surface, removing all but the silicon 230 deposited in the window and a small portion 231 at the top of the window. Next, the amorphous semiconductor is recrystallized by annealing the substrate.

The crystalline semiconductor plug 230 formed in the window 225 becomes a channel (260 in FIG. 3P) of the device. Therefore, the crystalline semiconductor plug 230 is doped. The dopant for the channel region 260 is the plug 23.
It is advantageous if 0 is introduced at the same time as it is formed. However, implanting the dopant is also considered appropriate.

After the window 225 is filled with the crystalline semiconductor 230 and the semiconductor 230 is doped in the desired manner, a sixth layer of material 235 is formed on the substrate, as shown in FIG. 3F. Layer 235 is the material that makes the self-aligned top contact (drain contact 235 in Figure 3G). One example of a suitable material is doped polycrystalline silicon. The selected dopant is a silicon channel (260 in FIG. 3P).
Is the opposite form of the dopant used to dope. The concentration of the dopant is about 10 ²⁰ atoms / cm ³
Greater than

As shown in FIG. 3F, layer 236 of material.
Are deposited on layer 235. This material is patterned so that the remaining portion overlies the crystalline semiconductor plug 230 and the area adjacent thereto (FIG. 3G). Layer 236
Material is selected to have an etch rate in the etchant selected to remove layer 215 that is significantly lower than the etch rate of the material of layer 215. In this regard, the material selected from layer 236 is the same as layers 211 and 21.
It is advantageous if it is the same as the material of 6. One example of a suitable material is silicon nitride. Silicon nitride layer 2
36 is formed on layer 235 using the techniques previously described.

As shown in FIG. 3G, conventional lithographic techniques are used to leave only the portion of the layer above or adjacent to the silicon-filled window,
Layer 23 (using one or more dry etch steps)
6, 235 and 220 are patterned. Layer 22
The remaining portions of 0, 235 and 236 form the drain of the device. As shown in FIG. 3H, layer 2 of material
40 is then deposited. The material of layer 240 is the same as the material of layer 215 in the etchant selected to remove layer 215.
Is selected to have an etch rate significantly lower than that of the material. One example of a suitable material for layer 240 is silicon nitride. The thickness of layer 240 is layer 2
The remaining portions of 35 and 220 are selected to be protected from contact with subsequent etchants. Layer 240 is then etched using an anisotropic etchant such as a dry plasma etch. As shown in FIG. 3I, the layer 240 remaining after the anisotropic etch.
Is the part adjacent to the layers 220 and 235. As a result of this etching, layer 215 is exposed.

The substrate is then wet-etched (eg hydrofluoric acid in water) or isotropic dry-etched (eg anhydrous hydrofluoric acid), thereby removing the exposed remaining portion of layer 215. . As shown in FIG. 3J, the remaining portion of layer 210 is still covered by layer 211, and layers 220 and 235 are enclosed by the remaining portion of layers 216, 236 and 240. As a result, the remaining portions of layers 210, 220 and 235 remain separated so that they do not come into contact with subsequent etching means.

Referring to FIG. 3K, a sacrificial silicon dioxide layer 245 is grown on the exposed surface of the silicon plug 230. A sacrificial silicon oxide thickness on the order of less than about 10 nm is considered suitable.
The sacrificial silicon oxide 245 is then removed using conventional isotropic etching (eg, hydrofluoric acid in water) (FIG. 3L). As a result of the sacrificial oxide formation and removal, the surface of the silicon plug 230 is smooth and some sidewall defects are removed. Layer 211 prevents wet etching means from contacting layer 210. As a result of this etching, the portion of silicon plug 230 that corresponds to the deposited thickness of layer 215 is exposed. Plug 23
The exposed portion of 0 defines the physical gate length of the device being formed.

The substrate is then placed under conditions that form a layer 250 of gate dielectric over the exposed portion of silicon plug 230. The resulting structure is shown in Figure 3M. The thickness of the gate dielectric 250 is about 1 nm to about 2 nm.
It is 0 nm. An example of a suitable thickness is 6 nm. If the semiconductor plug is silicon, the silicon dioxide gate dielectric layer is formed by heating the substrate in an oxygen containing atmosphere to a temperature in the range of about 700 ° C to about 1100 ° C. Other means of forming the gate dielectric (eg, chemical vapor deposition, jet vapor deposition or atomic layer deposition) are also considered suitable. The conditions for forming a desired thickness of gate dielectric are well known to those skilled in the art.

Referring to FIG. 3N, the gate electrode is formed by then depositing a layer 255 of a suitable gate material of sufficient conformity (eg, a layer of doped amorphous silicon into which the dopant is co-introduced). It The amorphous silicon is then subsequently recrystallized to form polycrystalline silicon. The dopant concentration is sufficient so that the resistivity of layer 255 is low enough. Figure 3
Referring to 0, layer 255 is patterned to form gate 265 of the device. The form of the gate is
Mainly a design choice. However, the gate surrounds a portion of the silicon plug 230 with the gate oxide 250 formed above.

Referring to FIG. 3P, the dopants are driven from the dopant source layers 210 and 220 into the crystalline semiconductor plug 230 by solid phase diffusion, forming source 232 and drain 233 extensions. The advantage of this technique is that the source and drain extensions (and thus the channel of the device) are aligned with what will become the gate of the device. For the dopant source layers 210 and 220, the dopant concentration in the portion of the crystalline semiconductor plug 230 doped by solid state diffusion is typically at least about 1 ×.
At 10 ¹⁹ / cm ³ , a dopant concentration of about 5 × 10 ¹⁹ / cm ³ is considered advantageous. This solid phase diffusion technique results in very shallow source and drain extensions. Sauce 23
The distance that the 2 and drain 233 extensions penetrate into the plug 230 is preferably less than half the width of the plug. By limiting the penetration of the dopants in this manner, significant overlap of the doped regions with opposite sides of the plug 230 is avoided. Also, the distance that the source 232 and drain 233 extensions extend below the device gate is preferably limited to less than one fifth of the gate length. The dopant has a shape that is opposite to the shape of the dopant in the channel region 260 of the plug 230.

In another embodiment (not shown), the top portion 231 of the silicon plug 230 (FIG. 3E).
Is polished so that the top of silicon plug 230 is flush with the top of layer 220. Means such as chemical mechanical polishing are considered suitable. By polishing the top portion of the silicon plug 230 in this manner, the diffusion of dopants from layer 235 into the silicon plug 230 to form the top source / drain contact can be better controlled.

In yet another embodiment, a thin layer of undoped silicon dioxide (eg about 25 nm thick) is
Formed on layer 205. Referring to FIG. 3E, this layer (not shown) is a highly doped dopant source layer 2
10 through the layer 205 downwards and upwards, serving as a barrier to solid-state phosphorus dopant diffusion into the formed silicon plug 230.

The above examples have been given to show specific examples of processes using the present invention. One of ordinary skill in the art will recognize that there are many process steps, materials and means useful in practicing the present invention. The invention is not intended to be limited to the embodiments, except in accordance with the scope of the appended claims.

[Brief description of drawings]

FIG. 1 is a schematic side view of a vertical transistor.

FIG. 2A is a diagram showing the process steps of an embodiment of the present invention.

FIG. 2B is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2C is a diagram showing the process steps of an embodiment of the present invention.

FIG. 2D is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2E is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2F is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2G is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2H is a diagram showing the process steps of one embodiment of the present invention.

FIG. 2I illustrates the process steps of one embodiment of the present invention.

FIG. 2J is a diagram showing the process steps of one embodiment of the present invention.

FIG. 3A is a diagram showing process steps of a second embodiment of the present invention.

FIG. 3B is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3C is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3D is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3E is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3F is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3G is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3H is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3I is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3J is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3K is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3L is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3M is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3N is a diagram showing the process steps of the second embodiment of the present invention.

FIG. 3O is a diagram showing process steps according to the second embodiment of the present invention.

FIG. 3P is a diagram showing the process steps of the second embodiment of the present invention.

[Explanation of symbols]

10 devices 15 Source 20 drain 25 channels 30 substrates 35 gate 100 silicon substrate 105 Source region, surface 110 layers, material layer, first layer 115th layer, 2nd layer 120th layer, 3rd layer 125 grooves, windows 130 Semiconductor material, Silicon 131 plug 135 layers 140 top 145 surface 150 layers 155 Gate electrode, layer, gate 200 substrates 205 source region, heavily doped region 210 layers, first layer, dopant source layer 211 layers, second layer, etch stop layer 215th layer, 3rd layer 216 layers 220 layers 225 windows 230 Semiconductor materials, silicon, plugs, semiconductors 231 part 232 Source 233 drain 235 layer, drain contact 236 layers 240 layers 245 Silicon dioxide layer 250 gate oxide 255 layers 260 channels, channel region 265 Gate electrode, gate

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Donald Paul Monroe United States 07901 New Jersey, Summit, Winchip Road 35 (56) Reference JP-A-5-326952 (JP, A) JP-A-5-267678 ( JP, A) JP 5-183158 (JP, A) JP 5-90597 (JP, A) JP 4-192368 (JP, A) JP 2-186676 (JP, A) JP JP-A 1-228162 (JP, A) JP 62-45058 (JP, A) JP 61-269377 (JP, A) JP 57-109367 (JP, A) JP 5612563 (JP, B2) JP 5324673 (JP, B2) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/78 653 H01L 29/786 H01L 21/336

Claims (24)

(57) [Claims] 1. A step of forming a first device region (105) selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate (100) by doping an impurity into the semiconductor substrate. A step of forming at least three layers (110, 115, 120) having a configuration in which a second layer is sandwiched between a first layer and a third layer on a first device region in a semiconductor substrate. And the etching rate of the second layer is at least 10 times faster than the etching rates of the first and third layers in a given etchant, and the material of the second layer is selected so that the second layer is selectively etched. The window being formed in at least three layers, whereby the window (1
25) terminating in a first device region (105) formed in a semiconductor substrate; filling a window (125) with a semiconductor material (130), whereby at least three layers (110, 115, 120). ) In which a semiconductor plug is formed, the plug having first and second ends, the first end being the first device region (105).
Contacting the second end of the silicon plug (140) with impurities to form a second device region selected from the group consisting of a source region and a drain region. One of the two device regions is a source region and the other is a drain region; removing a portion of the third layer (120), thereby causing the second layer () below the removed portion of the third layer (120). 115) step of exposing; second by etching using the predetermined etchant
The layer (125) is removed, whereby the semiconductor plug (1
30) exposing a portion of; a step of forming a layer of dielectric material on the exposed portion of the semiconductor plug; a step of forming a gate in contact with the layer of dielectric material and forming a gate of the vertical transistor. Fabrication process. 2. The process of claim 1, wherein the etchant is selected from the group consisting of isotropic wet etchant and isotropic dry etchant. 3. The process of claim 1 wherein the semiconductor plug is a doped semiconductor plug and the dopant is selected from the group consisting of n-type dopants and p-type dopants. 4. The process of claim 3 wherein the doped semiconductor plug is formed by depositing a semiconductor material in the window and simultaneously introducing a dopant into the semiconductor material. 5. The process of claim 3, wherein the doped semiconductor plug is formed by depositing a semiconductor material in the window and then implanting a dopant therein. 6. The semiconductor material is a crystalline semiconductor material and is selected from the group consisting of silicon, silicon-germanium and silicon-germanium-carbon.
The described process. 7. The process of claim 2 wherein the first and third layers are made of electrically insulating material. 8. The process of claim 7, wherein the electrically insulating material is selected from silicon nitride, silicon dioxide and doped silicon dioxide. 9. The process of claim 1 further comprising the step of forming an etch stop layer on the first layer, the second layer or both the first layer and the second layer. 10. The process of claim 1, further comprising forming a diffusion barrier layer over the first device region before at least three layers are formed thereover. 11. The electrically insulative material is doped silicon dioxide which is a dopant source for the source and drain extensions, and the process further forms source and drain extensions in the semiconductor plug. To
The process of claim 8 including the step of doping the semiconductor plug with dopants from the first and third layers. 12. The dopant form in the doped silicon dioxide is selected from the group consisting of n-type and p-type, and the dopant is in a form opposite to that of the dopant in the semiconductor plug. process. 13. On the exposed portion of the semiconductor plug,
The process of claim 1 further comprising forming a layer of thermal oxide, removing the layer of thermal oxide, and then forming a layer of dielectric material on the exposed portion of the semiconductor plug. 14. The process of claim 1, wherein the substrate is selected from the group consisting of a silicon substrate and silicon on an insulating substrate. 15. The process of claim 1, wherein the layer of insulating material is formed on the semiconductor plug by heating the substrate to a temperature in the range of about 700 ° C. to about 1100 ° C. in an atmosphere containing oxygen. . 16. The process of claim 1, wherein the layer of dielectric material is formed on the semiconductor plug by chemical vapor deposition. 17. The process of claim 1, wherein the layer of dielectric material is formed on the semiconductor plug by atomic layer deposition. 18. The process of claim 1, wherein the layer of dielectric material is formed on the semiconductor plug by jet vapor deposition. 19. The process of claim 1, wherein the layer of dielectric material formed on the semiconductor plug is selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride and metal oxide. 20. The process of claim 19, wherein the layer of dielectric material formed on the semiconductor plug has a thickness of about 1 nm to about 20 nm. 21. The process of claim 1, wherein the etch rate of the second layer is at least 10 times faster than the etch rate of the semiconductor plug in a given etchant. 22. The gate is doped polycrystalline silicon, doped amorphous silicon, doped polycrystalline silicon-germanium, doped amorphous silicon-germanium, doped polycrystalline silicon-germanium-carbon, doped. The process of claim 1 wherein the material is selected from the group consisting of amorphous silicon-germanium-carbon, metals and compounds containing metals. 23. The process of claim 22, wherein the gate material is formed on the substrate by chemical vapor deposition, electroplating or a combination thereof. 24. The process of claim 23, wherein the metal and the metal-containing compound are selected from the group consisting of titanium, titanium nitride, tungsten, tungsten silicide, tantalum, tantalum nitride and molybdenum.