JP3503690B2 - Motor speed control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric motor speed control device for controlling the rotational speed of an electric motor so as to keep it at a set value.

[0002]

2. Description of the Related Art As a speed control device for controlling the rotation speed of an electric motor so as to keep it at a set value, a device employing PLL control is used. FIG. 5 schematically shows the configuration of a conventional electric motor control device that employs PLL control. In FIG. 5, 1 is a DC motor to be controlled and 2 is a rotation whose frequency is proportional to the rotational speed of the electric motor 1. A rotation detector such as a rotary encoder that outputs a detection pulse Pn, 3 is a reference pulse generator that generates a reference pulse Ps of a frequency that gives a set rotation speed of an electric motor, and 4 is a reference pulse Ps and a rotation detection pulse Pn as inputs. A PLL control circuit (IC) 5 that outputs the phase error signal Vd is a motor drive circuit that receives the phase error signal Vd as an input and supplies a drive current to the motor 1 so that the phase error becomes zero.

The PLL control circuit 4 calculates the phase error between the reference pulse Ps and the rotation detection pulse Pn at the falling edge or the rising edge of the pulse, and outputs a DC voltage corresponding to the calculated phase error as the phase error signal. Output as Vd. In the illustrated example, the frequency of the rotation detection pulse Pn is lower than the frequency of the reference pulse Ps, and the rotation detection pulse Pn
When the phase of n is delayed from the phase of the reference pulse Ps, the voltage value of the phase error signal Vd becomes large, the frequency of the rotation detection pulse Pn is higher than the frequency of the reference pulse Ps, and the phase of the rotation detection pulse Pn is When the phase of the reference pulse Ps is advanced, the voltage value of the phase error signal Vd becomes small.

The PLL control circuit 4 is also provided with a start / stop / command input terminal 4a, and a start / stop command signal is given to this start / stop command input terminal from a command circuit (not shown).

In the electric motor drive circuit 5, a collector is connected to a non-ground side terminal of an armature of the electric motor, and an emitter is connected to a positive side output terminal E + of a DC power source (not shown) whose negative side output terminal is grounded. It has a PNP transistor TR1 as an element and an operational amplifier OP1 which amplifies the phase error signal Vd and supplies it to the transistor TR1.

Positive phase input terminal of operational amplifier OP1 and ground
A constant DC voltage Vo is applied between them and the negative phase input terminal
The phase error signal Vd is applied between the ground and the resistor R2.
Has been. Inverting input terminal and output terminal of operational amplifier OP1
A resistor R3 and a capacitor C1 are connected in series betweencircuit
And a resistor R4 are connected in parallel.

A flywheel diode D1 is connected to both ends of the armature of the electric motor 1 with its anode facing the ground side.

In the speed control device shown in FIG. 5, the reference pulse generator 3 uses an oscillator having a high stability such as a crystal oscillator as a signal source, and the set rotation speed Ns of the electric motor 1 is set.
A reference pulse Ps having a reference frequency fs giving [rpm] is generated. The reference frequency fs is, for example, fs = (Ns / 60) where K is a constant determined by the configuration of the PLL control circuit 4 and n is the number of pulses Pn output from the rotation detector 2 while the electric motor 1 makes one rotation. It is given by × n × K.

When the electric motor 1 rotates, the rotation detector 2 causes the rotation detection pulse Pn having a frequency proportional to the rotation speed of the electric motor.
To occur. The PLL control circuit 4 detects the phase error of both pulses at the rising edge or the falling edge of the reference pulse Ps and the rotation detection pulse Pn, and outputs a voltage signal giving the phase error as the phase error signal Vd. . The phase error signal rises at the falling edge of the reference pulse Ps and falls at the falling edge of the rotation detection pulse Pn, but a phase error detection pulse is generated and the phase difference detection pulse is integrated. Can be obtained by

The phase error signal Vd is amplified by the operational amplifier OP1 and then supplied to the transistor TR1. The transistor TR1 increases the drive current of the electric motor 1 to increase its rotational speed when the rotational speed of the electric motor 1 is lower than the set speed and the phase of the rotation detection pulse is behind the phase of the reference pulse. When the rotation speed of the electric motor 1 is higher than the set speed and the phase of the rotation detection pulse is a lead phase with respect to the phase of the reference pulse, the driving current of the electric motor 1 is decreased to decrease the rotation speed. The drive current of the electric motor 1 is controlled according to the phase error signal. As a result, the phase and frequency of the rotation detection pulse are controlled to match the phase and frequency of the reference pulse, and the rotation speed of the electric motor is maintained at the set rotation speed.

[0011]

In the conventional motor speed control device as shown in FIG. 5, when the reference pulse Ps is not given to the PLL control circuit 4 or an inappropriate reference pulse is given, the phase There is a problem that the error signal is fixed to a certain value or its size becomes abnormal, the operation of the electric motor becomes unstable, and the electric motor runs out of control. If the operation of the motor becomes unstable or the motor goes out of control, the load may not operate normally or may be damaged.Therefore, it is necessary to prevent such a situation from occurring. preferable.

An object of the present invention is to provide an electric motor speed control device capable of preventing the operation of the electric motor from becoming unstable or abnormal due to an abnormal reference pulse.

[0013]

According to the present invention, there is provided a rotation detector for outputting a rotation detection pulse whose frequency is proportional to the rotation speed of an electric motor, and a reference pulse for generating a reference pulse having a frequency giving a set rotation speed of the electric motor. A generator, a PLL control circuit that calculates a phase error between a reference pulse and a rotation detection pulse, and outputs a phase error signal corresponding to the calculated phase error, and a motor drive that gives a drive current to the motor according to the phase error signal And a circuit to control the phase and frequency of the rotation detection pulse so as to match the phase and frequency of the reference pulse, thereby maintaining the rotation speed of the motor at the set rotation speed.

According to the present invention, the reference pulse judging section for judging whether the reference pulse is normal, and the driving of the electric motor by the electric motor drive circuit when the reference pulse judging section judges that the reference pulse is normal. And a protection circuit for prohibiting the drive of the electric motor by the electric motor drive circuit when the reference pulse judgment unit judges that the reference pulse is not normal.

The reference pulse determining unit determines that the reference pulse is normal when the deviation between the actual frequency of the reference pulse and the normal reference frequency that gives the set rotation speed of the electric motor is within an allowable range, and the reference pulse is normal. When the deviation between the actual frequency and the regular reference frequency that gives the set rotation speed of the electric motor is out of the allowable range, or when the reference pulse is not detected, the reference pulse is determined to be abnormal.

When the phase difference from the rotation detection pulse is obtained at the falling edge of the reference pulse, fluctuations in the duty ratio of the reference pulse also pose a problem. Therefore, in this case, the deviation between the actual frequency of the reference pulse and the normal reference frequency that gives the set rotation speed of the motor is within the allowable range, and the actual duty ratio of the reference pulse and the normal duty ratio of the reference pulse are If the deviation between the and is within the allowable range, it is judged that the reference pulse is normal, and the deviation between the actual frequency of the reference pulse and the regular reference frequency that gives the set rotation speed of the motor is outside the allowable range. When the deviation between the actual duty ratio of the reference pulse and the normal duty ratio of the reference pulse is out of the allowable range,
Alternatively, it is preferable to configure the reference pulse determination unit so as to determine that the reference pulse is abnormal when the reference pulse is not detected.

As described above, the reference pulse determination unit is provided, and when the determination unit determines that the reference pulse is normal, the motor drive circuit allows the motor to be driven, and the reference pulse is abnormal. When it is judged that it is prohibited to drive the electric motor by the electric motor drive circuit,
The motor can be stopped when the reference pulse becomes abnormal for some reason, so the operation of the motor becomes unstable, or the motor runs out of control, which adversely affects the load or damages the load. It is possible to eliminate the risk of doing so.

Whether or not the reference pulse is normal is determined by
For example, it can be performed by providing a pulse integrating circuit for integrating the reference pulse and a voltage level judging circuit for judging the level of the integrated output. In this case, for example, the voltage level determination circuit sets the integrated voltage output from the integration circuit to the first reference voltage and the second reference voltage higher than the first reference voltage.
When the integrated voltage is between the first reference voltage and the second reference voltage, the normal reference pulse confirmation signal is generated, and when the integrated voltage is less than or equal to the first reference voltage, And the reference voltage abnormality signal is generated when the integrated voltage is equal to or higher than the second reference voltage.

Further, a reference pulse detection signal whose level changes each time the rising and falling edges of the reference pulse are detected is output, and the reference pulse detection is performed when the rising and falling edges of the reference pulse are no longer detected. A reference pulse detection circuit that stops the output of the signal, an integration circuit that integrates the reference pulse detection signal, and a standard reference pulse when the output voltage of the integration circuit is greater than or equal to the reference voltage by comparing the output voltage of the integration circuit with the reference voltage. It is also possible to determine whether or not the reference pulse is normal by providing a confirmation signal and a voltage level determination circuit that generates a reference pulse abnormality signal when the output voltage of the integrating circuit is less than the reference voltage. it can.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the configuration of a motor speed control device according to the present invention. In FIG. 1, parts that are the same as the parts shown in FIG. 5 are given the same reference numerals.

In the speed control device of FIG. 1, when the reference pulse determining unit 11 determines whether the reference pulse Ps is normal, and when the reference pulse determining unit 11 determines that the reference pulse is normal, A protection circuit 12 is provided that allows the electric motor drive circuit to drive the electric motor and prohibits the electric motor drive circuit from driving the electric motor when the reference pulse judgment unit judges that the reference pulse is not normal.

The reference pulse judging section 11 shown in FIG. 1 includes a pulse integrating circuit 11A for integrating the reference pulse Ps, an integrated voltage Vi output from the integrating circuit 11A as a first reference voltage Vr1 and the first reference voltage Vr1. The second reference voltage V higher than the voltage
Compared with r2 (> Vr1), a normal reference pulse confirmation signal is generated when the integrated voltage Vi is between the first reference voltage Vr1 and the second reference voltage Vr2, and the integrated voltage Vi is the first reference voltage. The voltage level determination circuit 11B is configured to generate a reference pulse abnormality signal when the reference voltage is Vr1 or less and when the integrated voltage Vi is the second reference voltage Vr2 or more.

The integrating circuit 11A has its emitter grounded,
NPN transistor TR2 whose collector is connected to the positive output terminal E + of the DC power source (not shown) through resistor R5
And an integrating capacitor C2 whose one end is connected to the collector of the transistor TR2 through a resistor R6 and whose other end is grounded.
And the reference pulse Ps is applied to the base of the transistor TR2.

When the reference pulse Ps is generated as shown in FIG. 2 (A), the transistor TR2 is turned on / off, and the potential of the transistor TR2 changes like Ps' in FIG. 2 (B). When the level of the reference pulse Ps is zero, the transistor T
When R2 is off, the integrating capacitor C2 is charged from a DC power source (not shown) through resistors R5 and R6 with a constant time constant. During the period when the reference pulse is in the high level state and the transistor TR2 is in the ON state, the integration capacitor C2 is prevented from being charged, and its charge is discharged through the resistor R6 and the transistor TR2. Therefore, both ends of the integrating capacitor C2 are
As shown in (C), a DC voltage that decreases at a predetermined rate while the reference pulse Ps is in the high level state and increases at a predetermined rate while the reference pulse Ps is in the zero level state is taken as an integrated voltage Vi. Output.

Since the magnitude of the integrated voltage is determined by the frequency and duty ratio of the reference pulse, when the frequency and duty ratio of the reference pulse are within the permissible range, the magnitude of the integrated voltage Vi is within a predetermined range ( Figure 2
It falls within the range (between Vr1 and Vr2 of C). Therefore, the integrated voltage Vi is compared with the first reference voltage Vr1 and the second reference voltage Vr2 (> Vr1) to determine that the reference pulse is normal when the integrated voltage is between the reference voltages. You can

In the example shown in FIG. 1, the reference pulse is charged during the period when the reference pulse is in the zero level, but the integration capacitor is charged during the period when the reference pulse Ps is at the high level. The integrating circuit is configured to discharge the integrating capacitor during the period when the reference pulse is in the zero level state, and rises at a predetermined rate during the period when the reference pulse Ps is in the high level state, and the reference pulse Ps is in the zero level state. Alternatively, a DC voltage that decreases at a predetermined rate for a certain period may be obtained as the integrated voltage Vi.

The voltage level determination circuit 11B shown in FIG.
Is the first comparator CP1 to which the integrated voltage Vi and the first reference voltage Vr1 are input to the non-inverting input terminal and the inverting input terminal, respectively, and the integrated voltage Vi and the first reference voltage Vr1 to the inverting input terminal and the inverting input terminal, respectively. It is composed of a second comparator CP2 input to the non-inverting input terminal. Comparator CP
The output terminals of 1 and CP2 are commonly connected to form an AND circuit, and the common connection point of the output terminals of both comparators is the output terminal 11a of the reference pulse determination section 11.

In the voltage level determination circuit 11B shown in FIG. 1, comparison is made when the integrated voltage Vi is between the first reference voltage Vr1 and the second reference voltage Vr2 (when Vr1 <Vi <Vr2). Since both the output of the device CP1 and the output of CP2 are at high level, the potential of the output terminal of the voltage level determination circuit 11B is at high level. In the example of FIG. 1, the state in which the potential of the output terminal of the voltage level determination circuit 11B is at the high level in this manner is the state in which the normal reference pulse confirmation signal is generated. Further, when the integrated voltage Vi is the first reference voltage Vr1 or lower, or when the integrated voltage Vi is the second reference voltage Vr2 or higher, the output of the comparator CP1 or CP2 becomes low level, so the voltage level determination circuit 11B.
The output terminal has a low level potential. In the example shown in FIG. 1, the state in which the potential of the output terminal of the voltage level determination circuit 11B is at the low level in this manner is the state in which the reference pulse abnormality signal is generated.

The protection circuit 12 includes a capacitor C charged through a resistor R7 from a DC power source (not shown) when the potential of the output terminal of the reference pulse determination section 11 is at a high level.
3 and a comparator CP3 to which the voltage across the capacitor C3 and the judgment voltage Vf are input to the non-inverting input terminal and the inverting input terminal, respectively. The output terminal of the comparator CP3 is connected to the output terminal of the PLL control circuit 4. The comparator CP3 allows the phase error signal Vd to be given from the PLL control circuit 4 to the electric motor drive circuit 5 when the potential of its output terminal is in a high level state (non-grounded state), and the electric motor drive circuit When the electric potential of the output terminal of the comparator CP3 is in the low level state (when the output terminal is in the state of being grounded),
The PLL control circuit 4 is prohibited from supplying the phase error signal Vd to the electric motor drive circuit 5 to prohibit the electric motor drive circuit 5 from driving the electric motor.

In the example shown in FIG. 1, the reference pulse determination unit 1
When the output of No. 1 becomes high level, the capacitor C3 is charged from the DC power source (not shown) through the resistor R7, and when the voltage Vc3 across the capacitor C3 exceeds the judgment voltage Vf, the potential of the output terminal of the comparator CP3. Becomes a high level, and driving of the electric motor 1 is permitted. That is, when the normal reference pulse confirmation signal is generated for a certain time or longer, the comparator C
The output of P3 becomes high level, and driving of the electric motor 1 is permitted. When the reference pulse abnormal signal is generated, the voltage Vc3 across the capacitor C3 immediately becomes equal to or lower than the judgment voltage Vf, so that the comparator CP3 sets the potential of its output terminal to a low level to cause the phase from the PLL control circuit 4 to the motor drive circuit 5. The error signal is prohibited from being given, and thus the driving of the electric motor 1 is prohibited.

As described above, the input circuit of the protection circuit 12 is provided with a timer circuit (integrating circuit) consisting of the resistor R7 and the capacitor C3, and the motor reference signal is generated only when the normal reference pulse confirmation signal is generated for a certain time or longer. By allowing the driving, it is possible to prevent the electric motor 1 from being erroneously driven when the reference pulse determination unit 11 instantaneously generates a confirmation signal due to noise in a state where the reference pulse is abnormal.

The electric motor speed control device shown in FIG. 1 is similar to the conventional speed control device shown in FIG. 5 except for the above structure, and operates in the same manner as the speed control device shown in FIG. Control so that the rotation speed of the electric motor is maintained at the set rotation speed.

FIG. 3 shows another structural example of the motor speed control device according to the present invention. In this example, a reference pulse whose level changes every time the rising or falling edge of the reference pulse Ps is detected. A reference pulse detection circuit 11C that outputs the detection signal Vp and stops the output of the reference pulse detection signal Vp when the rising and falling edges of the reference pulse Ps are no longer detected, and an integration that integrates the reference pulse detection signal Vp. The output voltage Vi of the circuit 11D and the output voltage Vi of the integrating circuit 11D are compared with the reference voltage Vr3, and the integrating circuit 11D
Of the reference voltage Vr3 is generated when the output voltage Vi is higher than the reference voltage Vr3, and a reference pulse abnormality signal is generated when the output voltage of the integrating circuit 11D is lower than the reference voltage Vr3. The pulse determination unit 11 is configured.

The reference pulse detection circuit 11C includes an NPN transistor TR2, resistors R5 and R6, and a capacitor C.
And a pulse signal Ps obtained between the output of the pulse integration circuit 11A and the collector ground of the transistor TR2.
, And an exclusive OR circuit EX1 which receives as input. Exclusive OR circuit EX1
4D, when the reference pulse signal Ps is generated as shown in FIG. 4A and the pulse signal Ps' (FIG. 4B) having a waveform obtained by inverting the reference pulse signal Ps is generated, FIG.
As shown in, the reference pulse detection signal Vp having the same waveform as the reference pulse Ps is output. When the reference pulse Ps is no longer input, the transistor TR2 is held in the off state, and the two inputs of the exclusive OR circuit EX1 both hold the high level state, so the output of the exclusive OR circuit EX1 becomes the low level. Then, the output of the reference pulse detection signal Vp is stopped.

The integrating circuit 11D is composed of a resistor R10 and an integrating capacitor C4, and integrates the reference pulse detection signal Vp. When the reference pulse detection signal Vp is generated, the integration circuit 11D causes the integration voltage V shown in FIG.
The integrated voltage Vi 'having the same waveform as i is output.

The voltage level determination circuit 11E is adapted to integrate the integrated voltage V
i'and the reference voltage Vr3 are composed of a voltage comparator CP4 input to the non-inverting input terminal and the inverting input terminal, respectively, and the output terminal of the comparator CP4 is connected to the non-inverting input terminal of the comparator CP3 of the protection circuit 12. It is connected. Protection circuit 1
2 is configured similarly to the example shown in FIG.

When the reference pulse is normally generated, the integrated voltage Vi 'is higher than the reference voltage Vr3, so the comparator CP4 outputs a high-level normal reference pulse confirmation signal. When the reference pulse is not given and the output of the reference pulse detection circuit 11C remains at the low level, the integrated voltage Vi 'is at the low level, so that the comparator CP4 outputs the low level reference pulse abnormal signal. Is output. The operation of the protection circuit 12 when the normal reference pulse confirmation signal and the reference pulse abnormality signal are respectively output is similar to the example shown in FIG.

In the example shown in FIG. 3 as well, by determining the output level of the integrating circuit 11D by a voltage level determination circuit similar to the voltage level determination circuit 11B shown in FIG. It is also possible to determine whether or not there is an abnormality in the frequency and duty ratio of the reference pulse.

In the above example, the reference pulse judgment unit 11 is realized by a hardware circuit, but when the electric motor is controlled by the CPU, this judgment unit can be realized by software.

[0040]

As described above, according to the present invention, the reference pulse determination section is provided, and when the determination section determines that the reference pulse is normal, the motor drive circuit allows the drive of the electric motor. However, when it is determined that the reference pulse is abnormal, the driving of the electric motor by the electric motor drive circuit is prohibited, so when the reference pulse becomes abnormal for some reason, the electric motor can be stopped. It is possible to eliminate the possibility that the load may be adversely affected or the load may be damaged due to unstable operation or runaway of the electric motor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a motor speed control device according to the present invention.

FIG. 2 is a waveform diagram showing signal waveforms of respective parts in FIG.

FIG. 3 is a circuit diagram showing another configuration example of the motor speed control device according to the present invention.

FIG. 4 is a waveform diagram showing signal waveforms of respective parts of FIG.

FIG. 5 is a circuit diagram showing a configuration example of an electric motor speed control device.

[Explanation of Codes] 1 ... motor, 2 ... rotation detector, 3 ... reference pulse generator,
4 ... PLL control circuit, 5 ... motor drive circuit, 11 ... reference pulse determination section, 11A ... pulse integration circuit, 11B ... voltage level determination circuit, 11C ... reference pulse detection circuit, 11D
... integrator circuit, 11E ... voltage level determination circuit, 12 ... protection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02P 5/00 H02H 7/08

Claims (2)

(57) [Claims] 1. A circuit whose frequency is proportional to the rotational speed of the electric motor.
A rotation detector that outputs a rotation detection pulse and the installation of the motor.
Generates a reference pulse whose frequency gives a constant rotation speed
Reference pulse generator, the reference pulse and the rotation detection
Corresponds to the calculated phase error by calculating the phase error with the pulse
And a PLL control circuit for outputting the phase error signal
An electric motor that gives a drive current to the electric motor according to a phase error signal
A machine drive circuit, and the phase of the rotation detection pulse and
Match the frequency to the phase and frequency of the reference pulse
To set the rotation speed of the electric motor
In a motor speed control device that keeps a rotation speed, a pulse integration circuit that integrates the reference pulse, and an integrated voltage output from the integration circuit is a first reference voltage.
And a second reference voltage higher than the first reference voltage
The integrated voltage is the first reference voltage and the second reference voltage.
Generates a normal reference pulse confirmation signal when in pressure
If the integrated voltage is equal to or lower than the first reference voltage,
And the integrated voltage is equal to or higher than the second reference voltage
A voltage level determination circuit that generates a reference pulse abnormality signal, and a voltage level determination circuit when the normal reference pulse confirmation signal is generated.
Allows the drive of the electric motor by the electric motor drive circuit, and
When a pulse abnormality signal occurs, the motor drive circuit
A protection circuit for prohibiting driving of the electric motor by
A motor speed control device characterized by: 2. A frequency whose frequency is proportional to the rotation speed of the electric motor.
A rotation detector that outputs a rotation detection pulse and the installation of the motor.
Generates a reference pulse whose frequency gives a constant rotation speed
Reference pulse generator, the reference pulse and the rotation detection
Corresponds to the calculated phase error by calculating the phase error with the pulse
And a PLL control circuit for outputting the phase error signal
An electric motor that gives a drive current to the electric motor according to a phase error signal
A machine drive circuit, and the phase of the rotation detection pulse and
Match the frequency to the phase and frequency of the reference pulse
To set the rotation speed of the electric motor
In the motor speed control device that keeps the rotation speed, the rising and falling edges of the reference pulse are detected.
Outputs a reference pulse detection signal whose level changes each time it is output
The rising and falling edges of the reference pulse
Is no longer detected, the reference pulse detection signal is output.
A reference pulse detection circuit for stopping the force, an integration circuit for integrating the reference pulse detection signal, an output voltage of the integration circuit is compared with a reference voltage, and the integration is performed.
When the output voltage of the circuit is higher than the reference voltage, the normal reference pulse
Check signal is generated and the output voltage of the integrator circuit is the reference voltage.
If the voltage is less than
Bell judgment circuit and the above when the normal reference pulse confirmation signal is generated.
Allows the drive of the electric motor by the electric motor drive circuit, and
When a pulse abnormality signal occurs, the motor drive circuit
And a protection circuit that prohibits driving of the electric motor by
And a motor speed control device.