JP3501321B2 - Multiple port memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-divisionally accessible multi-port memory, and in particular, it can realize a large throughput with a small occupied area and can transfer read data to a register file with a waiting time of about SRAM access time. Regarding port memory.

[0002]

2. Description of the Related Art Conventionally, in the field of CMOS microprocessors, attempts have been made to improve performance such as processing speed by introducing parallel processing technology such as superscalar, miniaturizing processing technology and devising circuit. A microprocessor that can simultaneously issue four or more instructions at the same time has been announced. As a method of improving performance, a superscalar system, VLIW (Very Long Instruction) is used.
Fine-grain parallel processing technology such as the Word method is expected to occupy an important position in the future. In addition, the operating frequency and the degree of integration are being improved by device miniaturization and circuit arrangements.
CMOS microprocessors up to MHz have been announced. In order to maximize the performance of these high-performance microprocessors, it is necessary to secure the memory bandwidth of instructions and data commensurate with the operation speed. How can the effective memory bandwidth be increased by the cache memory system? , Is the key to improving the effective performance of microprocessors. One way to meet the demand for higher performance of such a cache memory system is to speed up the memory circuit.

As an attempt to increase the speed of a memory circuit, it has been proposed to shorten the memory access time and realize a wave pipeline operation using a synchronous circuit. For example, as a synchronous high-speed CMOS SRAM circuit, US Pat.
Circuits described in the specification of 985, 643, or IE Journal of Solid State Circuits Volume 26 No. 11 1991
Page 1577-1585 (IEEE Journal of Solid-State Circuit
s, Vol. 26, No. 11, November 1991, pp. 1577-1585)
The circuit described in US Pat. This conventional self-reset circuit can achieve high speed by halving the input capacitance as compared with a normal CMOS circuit by performing a pulse operation of the circuit. In addition, by adopting the wave pipeline operation, the access time is about 4n in a CMOS device with an effective channel length of 0.5 μm.
s, a synchronous SRAM having a cycle time of 2 ns has been realized. Furthermore, since the conventional self-reset circuit generates a pulse (reset pulse) for resetting the output signal from the output signal, the reset pulse is supplied only to the circuit where the signal has changed, and the clock is supplied collectively from the outside. Compared to the dynamic circuit of the above method, the power consumption due to the invalid clock is eliminated and the low power consumption is achieved.

Another attempt to increase the speed of the memory circuit is as follows.
For example, IEE Journal of Solid State Circuts Volume 30 Number 4 1995
Page 487-490 (IEEE Journal of Solid-State Circu
The circuit described in its, Vol. 30, No. 4, April 1995, pp. 487-490) is known. This conventional CMOS SR
In the AM circuit, the sense circuit is duplicated to realize stable wave pipeline operation.

In a cache memory of a microprocessor capable of issuing a large number of instructions at the same time as in a super scaler processor, the demand for simultaneous execution of a plurality of load / store instructions for accessing the cache memory increases as the number of simultaneously issued instructions increases. There is. Therefore, a plurality of cache memory access ports are required. Moreover, it is desired that the tag memory of the cache has a plurality of ports in order to support the snoop protocol for guaranteeing the consistency of the cache memory of the multiprocessor system.
A microprocessor incorporating a cache memory with multiple ports and a cache memory chip with multiple ports have already been announced. As a method to realize a memory with multiple ports (that is, multi-port memory),
A method using a multi-port memory cell, a method using interleaving (a method using bank division), and a method of realizing a pseudo multi-port memory by time division access are known.

As an example of the cache memory chip having a plurality of ports as described above, an ISC
See 1994 Page 262-263 (ISSCC, 1994, pp. 262-26
The 3-port memory described in 3) is known. This conventional 3-port memory has a cycle time of 15 by making the internal CMOS SRAM circuit operate in a pipeline.
An internal CMOS SRAM circuit is accessed three times (time-division access) in a period of ns to realize a pseudo three-port memory using one-port memory cells.
This pseudo 3-port memory can achieve a significant reduction in occupied area by using 1-port memory cells.

Another attempt to improve the performance of the cache memory system is to provide the cache with a prefetch function. For example, I E E E
Micro August 1994 Page 59-67 (IEEE Micro, August
1994, pp. 59-67) improves the hit rate by making it possible to avoid a cache miss due to the first access by prefetching. However, it has been pointed out that such a method of providing a cache with a prefetch function has a problem that the throughput required for the cache reaches twice the throughput of the main memory in the worst case (for example,
IPSJ Journal Volume 34 Number 4 1993
See pages 669-680). In order to increase the cache throughput, it is necessary to increase the number of cache memory ports.

[0008]

As described above, the conventional multi-port memory using the multi-port cells has a problem that the occupied area is large, and the multi-port memory by interleaving has different ports. When accessing the same bank at the same time, there is a problem that contention occurs and the effective throughput decreases. The multiport memory by time division access has the above-mentioned problems, a small occupied area can be realized, and there is no problem of competition, so that there is an advantage that high throughput can be obtained. However, conventional multi-port memory circuits with time-division access (ISSC 1994, page 262-263 (ISSCC, 1994, pp. 262-26
(3)) has another problem as follows.

FIG. 13 is a conceptual diagram of access to a conventional multi-port memory circuit by time division access. Problems of the conventional multi-port memory circuit will be described with reference to FIG. Figure 1
Reference numeral 3 represents the state of access when realizing a 2-port memory. Solid arrows 500, 501, 502, 503 in FIG.
Indicates access to the internal 1-port SRAM. Dashed line 50
6,507,508,509 is the waiting time for timing adjustment,
Solid arrows 510 and 511 represent transmission of a signal from the output port to the outside, and a clock 31 represents a reference clock signal for synchronization between the 2-port memory and the outside.

In the figure, at time 0 (and time 2), addresses for accessing the input ports A and B are supplied, and at time 2, data is output to the output ports A and B (where the cycle time is the time From 0 to time 2). The internal 1-port SRAM is accessed twice, access 500 and access 501, and the data obtained by the two accesses at time 2 after the end of the second access 501 is output to the output ports A and B. Because,
As a result of the first access, there is a problem that the access time becomes long because it waits for the waiting time 508. That is, there is a problem that the access time is increased in the conventional multi-port memory by time division access.

On the other hand, in order to eliminate the waiting time 508 for the first access, the time for one stage of the pipeline may be halved (in the example of FIG. 13, one cycle is the time).
It is the period from 0 to time 2, but this is halved to make one cycle the period from time 0 to time 1).
Peripheral circuits such as a register file that receives the output of the memory must operate at twice the cycle frequency. Further, it is possible to overlap the first access 500 and the second access 501 by pipeline-operating the internal SRAM for speeding up. In that case, the operating frequency of the circuit that receives the memory output ( Timing) must be adjusted accordingly, and pipelined memory has a large effect on peripheral circuits such as register files. As described above, when the memory is completely pipelined in order to improve the memory throughput, there is a problem that peripheral circuits are complicated.

In addition to the above-mentioned problems, there are the following problems regarding the practical use of the multiport memory circuit. For example, using the primary cache as an example,
When actually trying to perform many memory accesses at the same time, not all of them are accesses for the load instruction to the register file, but memory accesses that do not require transfer of data to the register file. It is often included. For example, store (stor
e) Writing to memory for instructions, or writing for replacement after a cache miss (refill or relo
ad), or tag read for snoop, cache read to check if there is data to be prefetched in the cache for software prefetch (prefetch lookup; pre-fetch lookup, missed In that case, it is not necessary to transfer the data to the register file for prefetching the data into the cache) and reading for hit determination for associative writing.

Consider a case where two accesses are simultaneously performed. It is assumed that one of two simultaneous accesses is a load instruction to a register file and the other is a write for replacement after a cache miss. In such a case, in the method of FIG. 13, it is necessary to wait until time 2 for the data transfer to the register file regardless of which of the input ports A and B is accessed. The access that actually needs to read the data is one of the two accesses (to the register file
load command), access 500 in FIG. 13 is assigned a read for a load instruction to the register file, and access 501 is assigned a write access. Should be possible, but the conventional method described above requires waiting until time 2. As described above, the conventional multi-port memory based on time-division access has a problem in that optimization including actual application has not been achieved.
The first object of the present invention is to solve the above problems.
Optimize the order of access to the multi-port memory circuit by time-divisional access and load the register file (l
oad) It is to provide a multi-port memory by time division access without increasing the read access time for instructions.

In addition, the conventional high-speed memory circuit (IEEE Journal
l of Solid-State Circuits, Vol.26, No. 11, November
1991, pp. 1577-1585, or IEEE Journal of Soli
d-State Circuits, Vol. 30, No. 4, April 1995, pp. 4
87-490), the wave pipeline operation of the CMOS SRAM was achieved, but the application to a multiport memory circuit by time division access and its specific circuit configuration are not mentioned. A second object of the present invention is to apply a conventional wave pipelined CMOS SRAM to a time-division access control circuit and an internal SR suitable for a multi-port memory circuit which is not considered in the conventional circuit.
It is to provide a specific configuration of an AM circuit.

[0015]

In order to achieve the first object, according to one embodiment (FIGS. 2 and 3) of the present invention, a two-port memory (generally having two or more ports) is used. It is possible to use multiple port memory, but for the sake of simplicity, it is shown in the case of 2 port memory), and 2 address input ports (60,
61) and two data output ports (73, 74) and an internal 1-port SRAM circuit (406), and the output port for transferring data to the register file is limited to one output port (73) and the other The output port (74) is a dedicated output port that does not transfer data to the register file. Two (time division) access to internal 1-port SRAM circuit
(500, 501 in FIG. 3) operates the pipeline to transfer the data to the register file among the accesses accepted by the two address input ports (60, 61) (assuming that the addresses are received at time 0 and time 2). Access that needs to be transferred
(500) is executed first (time 0 to time 2), and access (501) that does not require data transfer to the register file is started 1/2 cycle after the first access (time
1).

At the time (time 2) when the access (500) that needs to transfer the data to the register file is completed, the data is output from the output port (73) that transfers the data to the register file (504). The second access (501) is an access that does not need to transfer data to the register file, such as writing to a memory for a store instruction, writing for replacement after a cache miss (refill or reload), and prefetch lookup ( pre-fetch loo
kup) and so on. If more ports are needed, combine with multi-port memory cells.

In order to achieve the above second object, according to one embodiment (FIGS. 1 and 4) of the present invention, an input circuit (selector) of an internal 1-port SRAM circuit forming a 2-port memory is provided. 2 input 1 output multiplexer (400, 401),
The fall (or rise) time is (in 2-port memory)
An internal clock signal (10, 11) that is shifted by 1/2 cycle, and a P-channel MOS transistor (or N) that creates the logic of the internal clock signal (10, 11) and the multiplexer output signal (50, 51).
Channel MOS transistor, hereafter PMOS respectively,
It is composed of an NMOS (abbreviated as NMOS) (200, 201, 202, 203), a flip-flop (composed of inverters 300 and 301), and a reset transistor (100).

A PMOS (200, 20) that creates logic for one (10) of the internal clock signals and one (50) of the multiplexer output signals.
1) and the other (11) of the internal clock signal and the other (51) of the multiplexer output that connects the PMOS (202, 203) that creates the logic, and the output (40) of the flip-flop (composed of inverters 300 and 301) Connected) to the drain of the reset transistor (100). Reset transistor
A signal (52) in phase with the output (40) and delayed by a predetermined time is applied to the gate electrode (52) of (100).

In order to achieve the above first and second objects,
In order to generate a control signal (30) for a multiplexer (400, 401 in FIG. 1) that is an input circuit to an internal 1-port SRAM circuit that constitutes a 2-port memory according to an embodiment of the present invention, FIG. As shown, a signal (22,25) indicating whether each of the accesses from the two ports is a load instruction, a signal (23,26) indicating a read, and a signal (24,27) indicating a write. ) Is provided separately. Load
Signal indicating instruction (22,25), signal indicating read (23,2
6) Using the signals (24, 27) indicating write, if either of the access from the two input ports is a load instruction, the load instruction is given priority for access (Fig. 3 of 500). If both accesses from the two ports are load instructions, only one of them is allowed access and the other is accessed again in another cycle (see FIGS. 6 and 7) and the data is transferred to the register file. Data is output (504) from the output port (73). In addition, the access (501) that does not need to transfer data to the register file starts with a 1/2 cycle delay from the first access.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION In a typical embodiment of the present invention (FIGS. 2 and 3), a 2-port memory is provided with two address input ports (60, 61) and two data output ports (73, 74). By using the internal 1-port SRAM circuit (406),
The occupied area can be reduced. The output port that transfers data to the register file is limited to one output port (73), and the access that needs to transfer the data to the register file among the accesses accepted by the two address input ports (60, 61) (500 ) Is executed first, and further access to transfer data to the register file (5
(00) is completed, the data is output from the output port (73) that transfers the data to the register file (504). Data can be transferred to the register file during the period of time 2 or the cycle time in the middle.

Two internal 1-port SRAM circuits
Of the (time-division) accesses (500, 501), the access (501) that does not need to transfer data to the register file is started 1/2 cycle after the first access, and the second access (501) is the register file. It is executed first while operating as a time-shared 2-port memory by limiting access to which does not need to transfer data (writing to memory for store instruction, refill or reload, pre-fetch lookup, etc.). The second access (501) can be prevented from affecting the data output (504) of the active access (500). When a larger number of ports are required, the occupied area can be reduced by combining with a multi-port memory cell as compared with the case where all access ports are realized using multi-port memory cells.

Representative Embodiments of the Present Invention (FIGS. 1 and 4)
Then, the internal 1-port SRA that constitutes the 2-port memory
Input the M circuit (address buffer circuit) to 2 inputs 1
Output multiplexer (400, 401), internal clock signal (1
PMO that creates logic of 0,11) and multiplexer output (50,51)
It consists of S (200,201,202,203), flip-flop (300,301) and reset transistor (100), and it is half cycle off from PMOS (200,201) which makes logic of one (10) of internal clock signal and one (50) of multiplexer output. By connecting in parallel the other internal clock signal (11) and the PMOS (202, 203) that creates the logic of the other (51) of the multiplexer output, the address of the port selected by the 2: 1 multiplexer (400) ( It is possible to start the access of (50) at time 0 and the access of the address (51) of the port selected by the other 2: 1 multiplexer (401) at time 1, which is shifted by 1/2 cycle. .

By connecting the flip-flops (300, 301) to the output (40), it can be avoided that the output (40) becomes high impedance, and stable operation can be achieved. output
Reset by connecting the drain of the reset transistor (100) to (40) and applying a signal (52) in phase with the output (40) and delayed by a predetermined time to the gate electrode (52) of the reset transistor (100). The gate capacitance of the transistor (100) is input
Since it can be excluded from the capacity of (50,51,10,11), high speed is achieved.

Representative Embodiments of the Present Invention (FIGS. 6 and 7)
So each access from two ports is loaded
A signal (22,25) indicating whether it is a (load) instruction, a signal (23,26) indicating a read, and a signal (24,27) indicating a write are provided, and an internal 1-port that constitutes a 2-port memory SR
Multiplexer (400, 401) that is the input circuit to the AM circuit
The control signal (30) is generated from a signal (22,25) indicating whether it is a load instruction, a signal (23,26) indicating reading, and a signal (24,27) indicating writing, If either of the accesses from the port is a load instruction, the load instruction is given priority to access (500), and the access accepted by the two address input ports (60, 61) Of these, the access (500) that needs to transfer data to the register file can be executed first. In addition, when access from both ports is a load instruction, access is allowed to only one of them and the other is accessed again in another cycle to transfer data to the register file. The output port can be limited to one output port (73), which simplifies the control of the output port.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the time division access multi-port memory of the present invention will be described below with reference to the drawings. Although a time-division access 2-port memory will be described below as an example for simplification, it goes without saying that it can be expanded to a multi-port memory by combining it with a multi-port memory cell, as will be described later. FIG. 1 shows the time division access 2 of the present invention.
One embodiment of the input circuit (selector, address buffer circuit) of the 1-port SRAM inside the port memory, FIG. 2 is a block diagram showing one embodiment of the time division access 2-port memory of the present invention, and FIG. A conceptual diagram of access to the time-division access 2-port memory of the invention is shown in FIG. 4, and a part of the operation waveform (timing chart) is shown.

The circuit diagram shown in FIG. 2 includes two address input ports 60 (port A) and 61 (port B), two data output ports 73 (port 1) and 74 (port 2), and internal 2 by time division access consisting of 1-port SRAM circuit
The structure of a port memory is shown. 1-port SR
The AM circuit is composed of a one-port memory cell array 406 and peripheral decode circuits 405 and 407.

While realizing a 2-port memory by time-divisionally accessing a 1-port memory cell array, the following measures are taken in this embodiment in order not to increase the access time. One of the two data output ports 73 (port 1) and 74 (port 2)
(Port 1) is a dedicated output port for transferring data to the register file, and the other output port 74
(Port 2) is an output port exclusively for data that does not need to transfer data to the register file. Two (time division) access to internal 1-port SRAM circuit 500,501
Are pipelined and have two address input ports
Of the accesses accepted at time 0, 60 (port A) and 61 (port B) first execute access 500 that requires data transfer to the register file (start at time 0), and then access the register file. Access without the need to transfer data
The 501 is delayed by 1/2 cycle from the first access and starts at time 1 (see FIG. 3).

When the access (500 in FIG. 3) that needs to transfer data to the register file ends (time 2)
Then, the data is output from the data output port 73 (port 1) for transferring the data to the register file (504 in FIG. 3). As a result, it becomes possible to transfer data to the register file at the same latency as the address access time while performing the time division access. Specifically, the first access 500 is preferentially assigned to read for a load instruction that needs to transfer data to the register file, and the second access 501 allocates data to the register file. Accesses that do not need to be transferred, ie write to memory for store instructions, write for replacement after cache miss (refill or reload), prefetch lookup
Assign (pre-fetch lookup) etc. As a result, the data output 504 of the access 500 executed first is operated as the second access while operating as a time division 2-port memory.
You can avoid being affected by 501.

Next, the read operation of the circuit of FIG. 2 will be described in more detail. It is assumed that the addresses of the address input ports 60 (port A) and 61 (port B) are fixed by time 0. Latches 402 and 403 in FIG. 2 are latch circuits for holding the addresses of the address input ports 60 (port A) and 61 (port B), and the reference clock signal 31 (see FIG. 3).
Will be described as being transparent for a period of high level (hereinafter abbreviated as "H"). At time 0, the address signals input to the address input ports 60 (port A) and 61 (port B) are transferred from the latches 402 and 403 to the address signals 62 and 63.
Is output as. At time 0, the selector (multiplexer) 404 selects one of the address signals 62 and 63 and outputs it as multiplexer output signals 64 and 65. Also, time 1
Then, the other one of the address signals 62 and 63 is selected and output as multiplexer output signals 64 and 65.

FIG. 4 shows the relationship between the multiplexer output signal 64 and the reference clock signal 31. As can be seen from the above, the selector (multiplexer) 404 functions as a parallel-serial conversion circuit that converts two address signals 62, 63 applied at the same time into two address signals 64, 65 that are time-shifted. Signals 62, 63, 64, 66, etc. in FIG. 2 represent a plurality of signal lines, and the correspondence relationship between the signals in FIG. 1, FIG. It is shown in parentheses as the signal number. In the present specification, the signal line code and the signal code may be used without distinction unless they are unclear.

Control signal 6 of selector (multiplexer) 404
6 is a control circuit 408 and a control signal 6 input to the control circuit 408.
7 and assigns the access for the load instruction in priority to the first access as described above. In the figure, reference numeral 405 is a row decoder circuit, 407 is a column decoder circuit, and output signals 64 and 65 from the latches 402 and 403 are the row decoder circuit 405 and the column decoder circuit, respectively.
One of the memory cell arrays 406 decoded by 407
(Or a memory cell corresponding to the read width) is selected. A potential difference occurs in the data line depending on the selected memory cell (see the data line in FIG. 4). The signal read from the memory cell array corresponding to the access started at time 0 is amplified and stored in the latch 410, and the signal read from the memory cell array corresponding to the access started at time 1 is latched 409. Memorized in. That is, read data of the access started at time 0 (first access 500) is stored in the latch 410 regardless of which of the input ports 60 (port A) and 61 (port B) is accessed. Access started at time 1 (second access 50
Read data (access with a delay of 1/2 cycle) is stored in the latch 409.

The timing at which the latches 409 and 410 latch the data has almost the same delay time as the delay time from the access start time 1 and time 0 until the read data 70 and 69 are determined, respectively, and the same power supply voltage. , The signal with temperature and process variation dependence. Since the output (signal 72) of the latch 410 is obtained from the time 0 in about the access time, the latch 411 is provided so that the signal of the latch 410 does not pass through other latches receiving the signal at a low operating frequency. . Latch 411 (in the figure,
The right end of the latch is filled in) indicates a latch circuit which is transparent while the reference clock signal 31 is at a low level (hereinafter abbreviated as "L"). Since the latch 411 is transparent when the reference clock signal 31 is "L", the data of the output port 73 (output port 1) of the latch 411 is such that the cycle time of the reference clock signal 31 is about the access time of the 1-port SRAM circuit. , Confirm by time 2 (see FIG. 4). This output port 73 (port 1) is connected to the data bus 450
Connect to. After that, the register file connected to the data bus 450 reads the data of the output port 73 (port 1), and the load (lo) at the latency of the access time of the 1-port SRAM circuit.
ad) is possible.

On the other hand, the latch 409 stores the read data of the access started at time 1 (the second access 501, the access delayed by 1/2 cycle). The timing at which the latch 409 latches the data has a delay time which is almost the same as the delay time from the time 1 until the read data (70) is determined, and is determined by a signal having almost the same power supply voltage, temperature and process variation dependency. Therefore, the output signal 71 of the latch 409 is fixed from time 1 in the access time. A latch 412 is provided so that the signal of the latch 409 does not pass through another latch that receives the signal at a low operating frequency. The latch 412 is a latch circuit which is transparent while the clock 31 is "H". Latch 412
Is transparent when the reference clock signal 31 is "H", the data of the output port 74 (port 2) of the latch 412 is fixed by time 3 (see FIGS. 3 and 4). When the circuit of FIG. 2 is used as a tag memory of a cache, for example, the data of the output port 74 (port 2) is input to the comparison circuit 425, and a hit determination is performed to perform prefetch for cache prefetch. Lookup (pre
-fetch lookup) is possible. Alternatively, the snoop hit judgment can be performed.

Next, the write operation of the circuit of FIG. 2 will be described in detail. Reference numerals 75 and 76 in FIG. 2 indicate write data input ports corresponding to the address input ports 60 (port A) and 61 (port B). Further, reference numerals 421, 42
Reference numeral 2 denotes a latch circuit having the same function as the latches 402 and 403, and reference numeral 423 denotes a selector having the same function as the selector 404. Similar to the read operation described above, the signal 77 (write data) that has been parallel-serial converted by the selector 423 and the write circuit 424 writes data in the memory cell 406.

As described above, according to the present invention, it is possible to load a 2-port memory with a latency of the access time of the 1-port SRAM circuit while realizing a 2-port memory by time division access. In the above explanation,
Although it has been described that the load instruction is assigned to the first access 500, which of the two address input ports 60 and 61 is used when the access accepted at time 0 does not include the load instruction. Since it is possible to access first, it is possible to determine the priority port in advance by hardware, or to provide another signal for designating the priority port and follow the instruction of that signal. 2 and 3 show an example of a time-division 2-port memory, but if more ports are required, combine them with multi-port memory cells to realize all access ports using multi-port memory cells. It goes without saying that the occupied area can be reduced more than in the case of performing.

FIG. 1 shows the selector (multiplexer) of FIG.
3 shows a circuit of one embodiment of the present invention of 404. Reference numeral 2 in FIG.
Reference numerals 0, 21, 40 and 30 indicate signals corresponding to the signals 62, 63, 64 and 66 of FIG. 2, respectively. As described above, the selector 404 in FIG. 2 selects one of the address signals 20 and 21 and outputs it as the selector output signal (address buffer output signal) 40 at time 0, and the address signal at time 1 delayed by 1/2 cycle. 20,21
The other one is selected and output as a selector output signal (address buffer output signal) 40.

Next, the operation of the selector 404 shown in FIG. 1 will be described with reference to the timing chart of FIG. Reference numerals 400 and 401 in FIG. 1 indicate a 2: 1 multiplexer circuit. To the internal clock signals 10 and 11, signals with a constant pulse width made from the rising edge and the falling edge of the reference clock signal 31 are added, respectively. In the standby state, the potential of the selector output signal 40 is "L". By the selector control signal 30 and the 2: 1 multiplexer circuit 400,
One of the address signals 20 and 21 is selected and output as the multiplexer output signal 50. Multiplexer output signal
After the 50 is determined, if the internal clock signal 10 becomes "L" and the multiplexer output signal 50 is "L", the P channel M
OS transistors (hereinafter abbreviated as PMOS) 200 and 201 are conductive
(Hereinafter, abbreviated as ON), and the selector output signal 40 becomes "H". The solid line in FIG. 4 shows such a state. When the multiplexer output signal 50 is "H", the PMOS (200) is non-conducting (hereinafter abbreviated as OFF), the selector output signal 4
0 remains "L" and does not change. The broken line in FIG. 4 shows such a state. At this time, since the internal clock signal 11 is "H" and the PMOS 203 is in the OFF state, the value of the multiplexer output signal 51 does not affect the selector output signal 40.

Further, a flip-flop (inverter 300 and
301) is an element for preventing the selector output signal 40 from becoming high impedance.
It should be designed small enough not to prevent changes in the potential of 40. When the selector output signal 40 becomes "H", the inverter 30
The signal 52 becomes "H" after a delay time determined by the characteristics of 2,303,304,305, and it becomes an N-channel MOS transistor.
A reset pulse is applied to the gate electrode of the reset transistor 100 composed of (hereinafter abbreviated as NMOS).
N-channel MOS transistor (hereinafter abbreviated as NMOS)
100 is turned on, and the selector output signal 40 returns to "L" (is reset). At this time, PMOS 200,201 and N
The delay time of the delay circuits 302, 303, 304, 305 and the internal clock signal 1 are set so that the through current flowing through the MOS 100 is sufficiently small.
Design so that the pulse width of 0 is almost the same.

Similarly, the selector control signal 30 and the 2-to-1 multiplexer circuit 401 select the other one of the address signals 20 and 21 (for example, when the multiplexer circuit 400 selects the address signal 20, the multiplexer circuit
401 selects the address signal 21) and is output as a multiplexer output signal 51. Delayed by 1/2 cycle, internal clock signal 11 becomes "L" and multiplexer output signal 5
When 1 is "L", the selector output signal 40 becomes "H", and when the multiplexer output signal 51 is "H", the selector output signal 40 remains "L" and does not change. At this time, since the internal clock signal 10 is "H" and the PMOS 201 is in the OFF state, the value of the multiplexer output signal 50 is the selector output signal.
Does not affect 40.

It goes without saying that the delay circuits 302, 303, 304, 305 and the NMOS 100 work in the same manner as in the case described above. Figure 4
As is clear from FIG. 1, since the address signal of the access started at time 0 is the address fetched in synchronization with the internal clock signal 10, the multiplexer circuit 40 of FIG.
The multiplexer output signal 50 selected by the output of 0 becomes the address of the first access (corresponding to 500 in FIG. 3), and the time 1
The address of the access started at is the internal clock signal 11
Since the address is taken in in synchronization with the multiplexer output signal 51 selected by the multiplexer circuit 401 in FIG.
Is the address of the second access (corresponding to 501 in FIG. 3).

That is, as shown in FIG. 1, the input circuit of the internal 1-port SRAM circuit forming the 2-port memory.
(Selector 404) is a 2: 1 multiplexer circuit 400, 401
, The internal clock signals 10 and 11, the PMOS 200, 201, 202 and 203 that make the logic of the multiplexer output signals 50 and 51, and the reset transistor 100.
The falling times of 0 and 11 are shifted by 1/2 cycle to form the logic of one internal clock signal 10 and one multiplexer output signal 50, and the other internal clock signal 11 that is 1/2 cycle off By connecting in parallel the PMOSs 202 and 203 that form the logic of one multiplexer output signal 51, access by the multiplexer output signal 50 of the input port selected by the 2: 1 multiplexer 400 starts at time 0, and the other 2 It becomes possible to start access by the multiplexer output signal 51 of the input port selected by the pair-to-one multiplexer 401 at time 1 which is shifted by 1/2 cycle.

By connecting a flip-flop (composed of inverters 300 and 301) to the selector output signal 40,
Period when both internal clock signals 10 and 11 are "H" (PMO
Since the selector output signal 40 does not have a high impedance even when S201 and S203 are non-conductive, stable operation is achieved even at a low operating frequency. Further selector output signal
By connecting the drain of the reset transistor 100 to 40 and adding a signal 52 in phase with the selector output signal 40 and delayed by a predetermined time to the gate electrode of the reset transistor 100, the gate capacitance of the reset transistor 100 becomes the multiplexer output signal 50, Since it can be excluded from the capacity of 51 or the internal clock signals 10 and 11, high speed is achieved.

FIG. 5 shows an embodiment of the circuit for generating the internal clock signals 10 and 11 of FIG. In the figure, PM
OS 204,205, NMOS 101,102, and PMOS 20
6,207 and NMOS 103,104 respectively form a NAND circuit, and the internal clock signal 10 is the reference clock signal 31 and the signal 53.
(Inverted delay signal of reference clock signal 31) is generated as a NAND signal, and the internal clock signal 11 is a NAND signal of signal 55 (inverted delay signal of reference clock signal 31) and signal 54 (inverted delay signal of signal 55). Is generated. Since the signal 53 has a phase opposite to that of the reference clock 31 and is delayed by the delay time due to the inverters 306 to 310, the internal clock signal 10 has a fixed period "when the reference clock signal 31 rises as shown in FIG.
L ".

Similarly, the signal 55 has a phase opposite to that of the reference clock 31, and the signal 54 has a phase opposite to that of the signal 55.
Since the signal is delayed by the delay time of 1 to 315, the internal clock signal 11 is also the reference clock signal 31 as shown in FIG.
It goes to "L" for a certain period at the falling edge of. As described in the description of FIG. 1, after the multiplexer output signal 50 is determined,
Since the internal clock signal 10 must be "L", the internal clock signal 10 of FIG. 5 is further delayed and used as the internal clock signal 10 of FIG. 1 if necessary.

FIG. 6 shows the multiplexer circuits 400 and 40 of FIG.
FIG. 3 is a diagram specifically showing one embodiment of the first embodiment and one embodiment of the control circuit 408 of the present invention in FIG. 2. FIG. 7 is a diagram showing a truth table of the control circuit shown in FIG. FIG. 6 (and FIG. 7) constitutes access start control means in the present invention. Next, FIG.
The operation of the circuit of FIG. 6 will be described in detail with reference to the truth table of the control circuit shown in FIG. The AND-OR-NOT circuit 318 of FIG. 6 serves as the multiplexer circuit 400 of FIG.
23 functions as the multiplexer circuit 401 in FIG. The "selected port" column at the right end of the truth table in FIG. 7 indicates whether the port selected as the access for the first cycle is port A or port B. That is, FIG.
The output of the multiplexer output signal 50 of the
It shows whether it corresponds to (port A) or address signal 21 (port B).

More specifically, when the selector control signal 30 of FIG. 6 is "H" (the complementary signal 32 of the selector control signal 30 is "L"), the output signal 50 of the AND-OR-NOT circuit 318 is It outputs a signal in the opposite phase of the address signal 21 (address of port B) and does not depend on the address signal 20. That is, when the selector control signal 30 is “H”, the AND-OR-NOT circuit 318 selects the address signal 21 (address of port B). AND at this time
-In the OR-NOT circuit 323, the address signal 20 (address of port A) is selected. When the selector control signal 30 is "L",
The AND-OR-NOT circuit 318 selects the address signal 20 (port A address), and the AND-OR-NOT circuit 323 selects the address signal 21 (port B address). Reference numerals 56 and 57 in FIG. 6 denote terminals for outputting complementary signals of the multiplexer output signals 50 and 51, which are used for decoding the address in the decode circuit of the internal 1-port SRAM circuit.

Further, in order to preferentially assign the load instruction to the access of the first cycle, the following measures are taken in the present invention. Each of the accesses from the two input ports is a load instruction in order to generate the selector control signal 30 of the multiplexers 400 and 401 of FIG. 1 which constitute the selector 404 which is an input circuit to the internal 1-port SRAM circuit. Signal indicating whether or not (load specified signal)
22, 25 are provided independently of the signals (read designation signal) 23, 26 indicating read and the signals (write designation signal) 24, 27 indicating write. Signals 22,2 indicating these load instructions
5, signals 23 and 26 indicating reading, signals 24 and 2 indicating writing
If either one of the access from the two input ports is a load instruction using 7, the load (loa
d) The instruction is accessed with priority, that is, the address signal of the priority input port (the input port corresponding to the load instruction) is selected and output as the multiplexer output signal 50.
Access from two input ports are both loaded
If it is an instruction, only one of them is allowed to be accessed first, and the other is accessed again in another cycle. Which input port to access the load instruction first may be fixedly determined in advance or may be determined by a control signal.

Next, the truth table of the control circuit of FIG. 6 shown in FIG. 7 will be described in detail. In each input port, a signal indicating read and a signal indicating write are true at the same time (“1” in the truth table indicates true, and “0” is true).
Shall represent false. Also in the following explanation, in the explanation of the truth table, “1” and “0” correspond to true and false, respectively, and do not correspond to potentials “H” and “L”, respectively.
It is also assumed that the signal indicating the load instruction does not become "1" at the same time as the signal indicating the writing. Further, when the signal indicating the load instruction is "1", the signal indicating the reading of the port is always "1" at the same time. That is, signals 23 and 24, signals
26 and 27, signals 22 and 24, and signals 25 and 27 do not become "1" at the same time. Whenever signal 22 (or signal 25) becomes "1", signal 23 (or signal 26) also becomes "1" at the same time. 1 ”.

In the first line of the truth table of FIG. 7, since signals 22 to 27 are all "0", it represents a state (NOP) in which neither input port A nor input port B is requested to read or write. ing. In this case, multiplexer output signal 50,5
Although 1 may be don't care, FIG. 7 shows an example in which port B is selected. At this time, the address signal of the input port B is output as the multiplexer output signal 50.

In the second line of the truth table of FIG. 7, the input port
Since only B is in the write state, the address signal of input port B is selected for the first cycle access. At this time, the address signal of the input port B is output as the multiplexer output signal 50. Similarly, the third and fourth lines of the truth table of FIG. 7 are access requests for only input port B, so 1
Select the address of input port B for the cycle cycle access. At this time, the address signal of the input port B is output as the multiplexer output signal 50.

From the fifth line to the seventh line of the truth table of FIG.
Since there is a write request from input port A and no access request from input port B (NOP) or an access request other than a load (load) instruction, either input port may be prioritized. Alternatively, a signal for designating a priority port may be provided, and any input port may be preferentially selected according to the signal, but FIG. 7 shows an example in which the input port A is preferentially selected. . At this time, the address signal of the input port A is output as the multiplexer output signal 50.

The eighth line of the truth table of FIG. 7 is input port A.
Write request from input port, load from input port B
Input port B is selected because there is an access request for the (load) instruction. At this time, the multiplexer output signal 50
The address of input port B is output as. At this time, the address signal of the input port B is output as the multiplexer output signal 50.

Similarly to the fifth to seventh lines in the ninth to eleventh lines of the truth table of FIG. 7, there is a read request other than the load instruction from the input port A, and the input port has a read request.
No access request from B (NOP) or load
Since there is an access request other than an instruction, either input port may be prioritized, and FIG. 7 shows an example in which the input port A is selected preferentially. At this time, the address signal of the input port A is output as the multiplexer output signal 50.

The 12th line of the truth table of FIG. 7 is the input port.
There is a read request from A other than the load instruction,
Since there is a load instruction access request from the input port B, the input port B is selected. At this time,
The address of the input port B is output as the multiplexer output signal 50. Lines 13 to 15 of the truth table of FIG. 7 are states in which there is a read request for a load instruction from only input port A, so input port A is selected preferentially. At this time, the address signal of the input port A is output as the multiplexer output signal 50.

In the 16th line of the truth table of FIG. 7, since there is a load instruction access request for both input port A and input port B, either input port may be prioritized, or another may be prioritized. Although a signal for designating a port may be provided and any input port may be preferentially selected according to the signal, FIG. 7 shows an example in which the input port A is preferentially selected. At this time, the address signal of the input port A is output as the multiplexer output signal 50.

Next, consider that the control signal 30 is generated under the condition that the control signal 30 is "1" (that is, the condition that the input port B is selected). 4 from the 1st line of the truth table of FIG.
Up to the second row, since the input port B is selected and the control signal 30 must be "1", the logic for generating the control signal 30 in this part is the signal 22 (input port A
load instruction specification signal), 23 (input port A read signal), 24
30 when all (write signal of input port A) is "0"
Must be designed to be "1". This condition is expressed as [/ 22] * [/ 23] * [/ 24]. Here, / is a symbol representing a negative signal, * is a symbol representing a logical product, and [] is a symbol representing a logical function of a signal.

Further, the fourth line, the eighth line, 1 of the truth table of FIG.
Since the control signal 30 must be "1" also in the second line, the logic for generating the control signal 30 in this part is that the signal 22 (load instruction designating signal of the input port A) is "0",
Signal 25 (load command designation signal of input port B) is "1", signal
The control signal 30 should be designed to be "1" when 26 (read signal of the input port B) is "1".
Although the signal 26 is included in the logic in FIG. 7, the signal 26 need not be included in the logic because the signal 26 is always “1” when the signal 25 is “1”. However, the read signal 26 of the input port B is not shown in FIG. 6 and is included in the logic for generating the control signal 30 because it is necessary for memory control in other portions even if it is not used for controlling the multiplexer circuit. This condition is expressed as [/ 22] * [25] * [26]. Based on the above conditions, the generation logic of the control signal 30 is [30] = [/ 22] * [/ 23] * [/ 24] + [/ 22] * [25]
* Represented by [26]. Here, + is a symbol representing a logical sum.

The generation logic of the control signal 30 is shown by a specific gate circuit in the 3-input NOR circuit 316 of FIG.
([/ 22] * [/ 23] * [/ 24]), Inverter 319 ([/ 2
2]), 3-input AND circuit 320 ([/ 22] * [25] * [26]),
2-input NOR circuit 317 ([/ 30]), inverter circuit 322 ([3
0]). Here we show the output logic function in parentheses after the gate circuit.

As described above, according to the circuit of FIG. 6 and the truth table of FIG. 7, when one of the accesses from the two input ports is a load instruction, that load (loa
d) It becomes possible to preferentially assign the read for the instruction to the access of the first cycle, that is, the access that needs to transfer the data to the register file among the received access can be executed first.

In addition, the 2-input NAND circuit 321 of FIG.
When both 2 (load instruction designating signal of input port A) and signal 25 (load instruction designating signal of input port B) are "1", that is, read for two input ports compete for load instruction The element for detecting the case where it is doing is shown. When both signal 22 and signal 25 are "1"("H"), N
The output 33 of the AND circuit 321 becomes "0"("L"). 2 and 6,
In the example of FIG. 7, the access of the input port A is prioritized and is first accessed, and the output is output to the output port 73 (output port 1) to the register file. then,
Access to the input port B is started with a delay of 1/2 cycle, and its output is output to the output port 74 (output port 2) not connected to the data bus 450.

Therefore, in order to transfer the result of the access of the input port B to the register file, a signal indicating a conflict is generated.
When 33 becomes "0"("L"), it is understood that the address of the input port B should be input again not in 1/2 cycle but in the next cycle one cycle later. For the sake of simplicity, in the above description, the access to the input port B is started with a delay of 1/2 cycle even when two load instructions conflict with each other. However, the signal 33 indicating the conflict is "0". "
When it becomes ("L"), set the internal clock signal 11 to "0"("
Since it is easy to control not to use "L") (Signal 33
And the NAND logic of the signal (/ 11) should be used as a new internal clock), and it is 1/2 when conflict occurs due to low power consumption.
It goes without saying that it is desirable not to execute the second access that starts with a cycle delay.

At this time, it is desirable to add the address of the input port B in the previous cycle to the input port A in the next cycle. This is because, in the example of FIGS. 2, 6 and 7 described above, since the input port A is the priority port, if the address of the input port B in the previous cycle is added to the input port B in the next cycle, contention will occur again. This is because there is a possibility that it will not be accessed. As explained above, 2-input NAND
The circuit 321 makes it possible to detect a read conflict for a load instruction of two ports and deal with it optimally.

Next, the output signals 34 and 35 of the circuit of FIG. 6 will be described. The output signals 34 and 35 are used to generate control signals for writing. Figure 10 shows these signals
FIG. 11 is a diagram showing a write control signal generation circuit for inputting 34, 35 and internal clock signals 10, 11 to generate a write control signal, and FIG. 11 is an operation waveform diagram. The signals 34 and 35 of the circuit of FIG. 6 and the circuit of FIG. 10 will be described in detail with reference to these drawings.

The AND-OR-NOT circuits 326 and 327 shown in FIG.
Like the NOT circuits 318 and 319, it works as a 2: 1 multiplexer. When the control signal 30 is "H", the AND-OR-NOT circuit 326 outputs a signal having a phase opposite to that of the signal 27 (port B write designation signal) to 34, and when the control signal 30 is "L", Outputs a signal in phase opposite to the signal 24 (write designation signal for port A) to 34 (signal 27,
24 indicates the state of writing when "1").
AND-OR-NOT circuit 327 outputs signal 24 when control signal 30 is "H".
When the control signal 30 is "L", the opposite phase signal is output to 35,
A signal having a phase opposite to that of the signal 27 is output to 35.

PMOS 236,237,238,2 in the circuit of FIG.
39 and NMOS 127 are PMOS 200,20 in the circuit of FIG.
Similar to 1,202,203 and NMOS 100, it works as a parrel-serial conversion circuit. Since the operation of the circuit that generates the signal 97 in FIG. 10 is the same as the operation of the circuit in FIG. 1, detailed description of the operation of each transistor will be omitted.

FIG. 11 is a diagram for explaining a case where a read instruction and a write instruction accompanied by a load instruction are received at time 0, reading for loading is started at time 0, and writing is started at time 1. is there. It is assumed that the address of the input port A is the write address and the address of the input port B is the read address. At this time, as described above, the control signal 30 is generated so that the first access is the read for loading, so the control signal 30 in this case becomes "H" (the truth value in FIG. 7). (8th row of the table).

Since the address of the input port A is the write address, the signal 24 (write designation signal of the input port A) is "
"H" and signal 27 (write command signal for input port B) are "L". Control signal 30 is "H", signal 24 is "H", signal 27 is "
Since it is L ", the signal 34 is" H "and the signal 35 is" L "by the circuit of FIG.
Becomes When the internal clock signal 10 changes from “H” to “L”, the signal 97 in FIG. 10 is output as a signal having a phase opposite to that of the signal 34. The signal 97 indicates a writing state when it is "H". Since the first access (access starting at time 0) is the reading of the address of the input port B, the signal 97 must not change to "L" at the falling edge of the internal clock signal 10. Signal 34 is "H", so PMOS 236 is OFF
, The signal 97 does not change from "L" even when the internal clock signal 10 falls. Then at time 1 input port A
Since the signal 35 is "L" when the writing of the address of is started, the signal 97 is generated by the fall of the internal clock signal 11.
Becomes "H".

As described above, the AND-OR-NOT circuits 326 and 327 similar to the 2-to-1 multiplexers (AND-OR-NOT circuits) 318 and 323 for selecting the address in FIG. 6 and the parrel-serial conversion circuit (PMOS 236, 237, 238, 239, NMOS) are used. 127, inverter 343 to 348), write designation signal for each input port
By outputting (the signals 27 and 24 in FIG. 6) as the signal 97, the write control signal at the time division access can be generated.

When writing data, as shown in FIG. 11, one of the data line pairs must be set to "L" in accordance with the time when the word line corresponding to the write address becomes "H". The circuit is configured so that one of the data line pairs is set to "L" by the signal 94 obtained by delaying 97 by an appropriate delay time. A circuit 418 in FIG. 10 shows a delay circuit pulse width adjusting circuit for adjusting the delay time and the pulse width of the signal 94 for this writing. Next, the delay circuit pulse width adjusting circuit 418 will be described.

Delay circuit pulse width adjusting circuit 418 in FIG.
The PMOS 240, 241, the NMOS 128, and the delay circuit 417 in the above function as an inverter circuit. The delay circuit 417 is a delay circuit that functions the same as the inverters 302 to 305 in FIG. 1, and a signal in phase with the output signal 99 and delayed by a predetermined delay time is added to the reference numeral 98. PMOS 242, NMOS 12
9. The inverters 349 to 356 also work as an inverter circuit.
Therefore, the output signal 94 is a delayed signal in phase with the signal 97. When writing, signal 97 becomes "H" and signal 99
Becomes "L". When the signal 99 becomes "L", the PMOS 242
Turns ON and the signal 94 becomes "H". After the signal 99 becomes "L", the signal 98 becomes "L" with a delay time of the delay circuit 417,
The PMOS 241 turns on and the signal 99 returns to "H". Traffic light 99
Returns to "H", the PMOS 242 is turned off. However, if the delay time of the inverters 351 to 356 is set larger than the delay time of the delay circuit 417 at this time, the signal 99 returns to "H". At the time, the output signal 36 of the inverters 351-356 is still "
You can prevent it from changing from "L" to "H".

Since the potential of the signal 94 is kept at "H" by the flip-flop (composed of the inverters 349 and 350), the pulse width of the signal 94 can be greatly extended by designing the delay time of the inverters 351 to 356 to be large. it can. That is, the delay time and pulse width of the signal 94 can be adjusted by the delay circuit pulse width adjusting circuit 418. Figure 10
In the above example, the delay circuit pulse width adjustment circuit 418 has an example of a circuit configuration of two stages, but it goes without saying that the delay time can be adjusted by increasing the number of stages as necessary.

FIGS. 8 and 9 are diagrams showing an embodiment of the circuit of the 1-port SRAM inside the time division 2-port memory of the present invention. Next, the operation of the circuits of FIGS. 8 and 9 will be described with reference to FIG.
This will be described in detail with reference to the operation waveform diagram of No. 1. Reference numeral 405 in FIG. 8 indicates a part of the row decoding circuit 405 in the block diagram of FIG. Signal 41 in FIG. 8 represents one of signals 64 in FIG. 2 similar to signal 40. PMOS 208,2
09 and NMOS 105 and 106 form a NAND circuit, and PMO
The S211 and the NMOS 107 form an inverter circuit. The PMOS 210 and the NMOS 108 are the NMOS 10 of FIG.
It works as a reset transistor that works the same as 0.
The inverters 328 to 331 work in the same manner as the inverters 302 to 305 of FIG. 1, and include the reset transistors PMOS 210 and NM.
Generates a gate signal of OS 108. That is, the inverter
As the output signal 45 of 330, PMOS 208,209 and NM
A signal delayed by a predetermined delay time in phase with the output signal 42 of the NAND circuit composed of the OSs 105 and 106 is obtained, and the output signal 46 of the inverter 331 has the same phase as the output signal 43 of the inverter circuit composed of the PMOS 211 and the NMOS 107 ( A signal delayed by a predetermined delay time is obtained by the signal 42, 45 and the opposite phase.

As shown in the operation waveform diagram of FIG. 11, time 0
When access is started to the internal clock signal 10 in FIG. 1, the selector output signal corresponding to the address signal is output.
40 becomes "H". The row decoder circuit 405 decodes the signals 40 and 41, and the word line 48 becomes "H" (selected). When the word line 48 becomes "H", a read current flows through the memory cell 413 and the data line pair 1
A potential difference is generated at 4, 15 (12, 13 indicate data line pairs in other columns).

The PMOS 212,213,214,215,2 shown in FIG.
16, 217 are elements (precharge PMOS) for precharging and equalizing the data line, and set the precharge signal 16 (φpc) to "H" before the word line 48 becomes "H".
Turn off the precharge PMOS. Signals 3, 4 (and 17, 18) represent the column select signal (and its complement). It is assumed that the signal 3 is a complementary signal of the signal 17 and the signal 4 is a complementary signal of the signal 18. The signals 3, 4, 17, and 18 are also decoded by the column decoding circuit 407 (FIG. 2) similarly to the word line 48, and the word line 4
Select the column at the same timing as 8

PMOS 218, 219, 220, 221 and NMOS 11
Reference numerals 1,112,113,114 denote elements for transmitting the potential difference of the selected data line to the common data line pair 5,6.
For example, if the column of data line pair 14,15 is selected,
Signal 3 becomes "H", signal 17 becomes "L", signal 4 remains "L",
The signal 18 remains "H" and does not change. Signal 3 is "H", Signal 17 is "
L ", PMOS 220,221 and NMOS 113,114
Is turned on, and the potential difference between the data line pairs 14 and 15 is transmitted to the common data line pairs 5 and 6 (see FIG. 11). At this time, signal 4
Remains at "L" and signal 18 remains at "H", so PMO
Since S 218,219 and the NMOS 111,112 are OFF, the potential difference between the data line pair 12,13 does not affect the potential of the common data line pair 5,6.

FIG. 9 is a diagram showing a circuit for amplifying the potential difference between the common data line pair 5 and 6. In the figure, common data lines 5 and 6 are signals corresponding to the signal 68 in the block diagram of FIG. As described in the description of FIG. 2, the signal read from the memory cell array 406 of FIG. 2 by the access started at time 0 is stored in the latch 410 and started at time 1 with a 1/2 cycle delay. The signal read from the memory cell array 406 by the access is stored in the latch 409. The sense amplifier 416 and the SR latch 410 of FIG. 9 (NAND circuit 3
38,339) and switch MOS 224,225,117,11
8 corresponds to the latch 410 of FIG.
The R latch 409 (consisting of NAND circuits 336 and 337) and the switch MOSs 222, 223, 115 and 116 correspond to the latch 409 in FIG.

That is, at the time when the signal read from the memory cell array 406 by the access started at time 0 causes a potential difference on the common data line pair 5 and 6, the switch M
Control signals 81,83 of OS 224,225,117,118 are set to "L", "respectively.
H "(the control signal 83 is a complementary signal of the control signal 81). By setting the control signals 81 and 83 to" L "and" H ", respectively, the switch MOSs 224, 225, 117 and 118 are all turned on,
The potential difference between the common data line pair 5 and 6 is transmitted to the input signal line pair 88 and 89 of the sense amplifier. At the time when the control signals 81 and 83 are set to "L" and "H", respectively, as shown in FIG. 11, the control signals 80 and 82 of the switch MOS 222, 223, 115 and 116 are "H" and "L".
The control signal 82 is not changed (the control signal 82 is a complementary signal of the control signal 80). Since the control signals 80 and 82 are "H" and "L",
The switch MOSs 222, 223, 115, 116 are kept OFF, and the read data 92 in the previous cycle is not destroyed.

After transmitting the potential difference of the common data line pair 5, 6 to the input signal line pair 88, 89 of the sense amplifier, the control signal 91 of the sense amplifier is set to "H", and the potential difference of the input signal line pair 88, 89 is set. SR latch 410 (consisting of NAND circuits 338 and 339)
Remember. Output signal 93 from SR latch (410) of FIG.
Corresponds to signal 72 in the block diagram of FIG. PMO
S 229,230,231 represents a PMOS for precharging the input signal line pair 88,89 of the sense amplifier, and sets the precharge control signal 84 to "H" before setting the sense amplifier control signal 91 to "H". It goes without saying that the charge PMOS is turned off. As shown in the operation waveform diagram of FIG. 11, when the control signal 91 of the sense amplifier is set to “H” and the potential difference between the input signal line pairs 88 and 89 is amplified to some extent, the switch MOSs 224, 225, 117 and 118 are turned off and the input signal line is turned off. Vs 88,89
And the common data line pair 5 and 6 are separated from each other, the signal amplitude of the common data line pair 5 and 6 can be reduced.

Similarly, when the access started at time 1 with a delay of 1/2 cycle is a read, the signal read from the memory cell array 406 of FIG. 2 is the common data line pair 5, 6 of FIG. At the time when a potential difference occurs in the switch MOS
The control signals 80 and 82 of 222, 223, 115 and 116 are set to "L" and "H", respectively. By setting the control signals 80 and 82 to "L" and "H" respectively,
The switch MOSs 222, 223, 115, 116 are all turned on, and the potential difference between the common data line pair 5, 6 is transmitted to the input signal line pair 86, 87 of the sense amplifier. Control signals 80 and 82 respectively "
At the time of making L "," H ", the control signals 81,83 remain unchanged as" H "," L. "Since the control signals 81,83 are" H "," L ", the switch MOS 224,225,117,118 Is kept OFF. The potential difference between the common data line pair 5 and 6 is set to the input signal line pair 8 of the sense amplifier.
After being transmitted to 6,87, the control signal 90 of the sense amplifier is set to "H", the potential difference between the input signal line pair 86,87 is amplified, and stored in the SR latch 409 (composed of NAND circuits 336,337).

Sense amplifier 415, precharge PMOS
226, 227, 228, SR latch 409 (consisting of NAND circuits 336, 337), switch MOS 222, 223, 115, 116, except that the read signal of the access started with a delay of 1/2 cycle is stored in SR latch 409 (consisting of NAND circuits 336, 337). Works as described above for reading access initiated at time 0. In the operation waveform diagram of FIG. 11, time 1
The case where the access started at is a write is shown. Further, the signal 92 corresponds to the signal 71 in the block diagram of FIG.

Next, the operation when the access started at time 1 is writing will be described. As described in the description of the write control signal generation circuit of FIG. 10, the control signal 94 in the circuit of FIG. 10 becomes "H" at the time of writing. This control signal 9
4 becomes the write control signal 94 of the write circuit 414 of FIG. Write data is added to 95 of the write circuit 414 in FIG. 9 at the timing when the word line corresponding to the write address becomes “H”. Write control signal
When 94 becomes "H", the NMOS 125 and 126 are turned on, and one of the common data line pairs 5 and 6 goes to "GND" (lower potential than the low level at the time of reading) corresponding to the write data. Become. Similar to the case of reading, the column selection signal (and its complementary signal) 3, 4, 17, 18 shown in FIG. 8 selects a column at substantially the same timing as the word line 48. Selected row switch MOS (218, 219, 111, 112 or 220,
One of 221,113,114) turns ON, and the common data line pair
When one of 5, 6 becomes "GND", one of the data line pairs in the selected column becomes "GND". When one of the data line pairs in the selected column becomes "GND" (and the word line is selected), data is written in the selected memory cell.

For writing, the common data line pair 5,
It is only necessary to set one of "6" to "GND", and it is not necessary to transmit the signals of the common data line pair 5 and 6 to the input signal lines 86 to 89 to the sense amplifier. In other words, when writing, the switch MOS 22
2,223,115,116 may be ON or OFF. Figure 1
The waveform of the sense amplifier input control signal 82 shown by the solid line 1 is the switching MOS 22
An example of control for turning on 2,223,115,116 is shown as in the case of reading. According to this control example, it is not necessary to separately control the sense amplifier input control signals 80, 81, 82, 83 for writing and reading, so that the circuit is simplified. The waveform of the sense amplifier input control signal 82 shown by the broken line in FIG. 11 is the switch MOS 222, 223, 115, 116 in the writing started at time 1.
Unlike the case of reading, an example of control for turning OFF is shown. This control example is suitable for speeding up because the parasitic capacitance of the common data line pair 5, 6 becomes small.

At the time of writing, the switch MOS 222, 223, 1
If the sense amplifier 415 is operated when 15,116 is turned on, data different from the write data applied to 95 may be written to the memory cell from the input signal lines 86 and 87. You have to prevent it from working. The operation waveform diagram of FIG. 11 shows an embodiment in which the sense amplifier control signal 90 is kept at "L" so as not to operate the sense amplifier 415 during writing. When writing, switch MOS 222,22
When 3,115 and 116 are turned off, the sense amplifier 415 may be operated. As described above, FIG. 8 and FIG.
An internal 1-port SRAM circuit can be realized by this circuit.

FIG. 12 shows the sense amplifier control signal 9 of FIG.
It is a figure which shows the generation circuit of 0,91. At the time of writing, the sense amplifier control signal 90 or 91 is kept at "L" so as not to operate the sense amplifier 415, 416 (as described above, when the switch MOS 222, 223, 115, 116 is turned off at the time of writing, the sense amplifier control signal 90 or 91 for "H"
Then, the sense amplifiers 415 and 416 may be operated. When the access starting at time 0 is writing, the write control signal 34 becomes "L", and when the access starting at time 1 is writing, the write control signal 35 becomes "L".

That is, when the access started at time 0 is writing, the writing control signal 34 becomes "L", and the PMO
S243 turns off. In this case, even if the internal clock signal 10 falls, the signal 37 does not become "H", and the sense amplifier control signal 91 maintains "L". Similarly, when the access started at time 1 is writing, the write control signal 35 becomes "L" and the PMOS 245 is turned off. Even when the internal clock signal 11 falls, 38 does not become "H", and the sense amplifier control signal 90 maintains "L". The operation waveform diagram of access starting at time 1 in FIG. 11 shows this state.

When the two accesses starting at time 0 and time 1 are both read, the write control signals 34 and 35 are both "H", so that the PMOSs 243 and 245 are turned on and the PMOSs 244 and 246 are also turned on by the fall of the internal clock signals 10 and 11. O
N, and the signals 37 and 38 both become "H". Reference number 419,4
Reference numeral 20 represents a delay circuit pulse width adjusting circuit similar to 418 in FIG. 10, and signals in phase with the signals 37 and 38 are output as sense amplifier control signals 91 and 90, respectively. In this case, the falling of the internal clock signals 10 and 11 causes signals 37 and 38
Becomes "H", the sense amplifier control signals 91 and 90 also become "H", and the sense amplifiers 416 and 415 are activated.

That is, when the access started at time 0 is a read, the sense amplifier 416 (see FIG. 9) is activated. In accordance with the delay time from the time 0 until the signals on the input signal lines 88 and 89 of the sense amplifier 416 are fixed, the sense amplifier
The delay time and pulse width of the delay circuit pulse width adjusting circuit 419 are adjusted so as to activate 416. Similarly, if the access starting at time 1 is a read, the sense amplifier 415 (FIG. 9) is activated. Input signal lines 86,8 of the sense amplifier 415 from time 1
Delay circuit pulse width adjustment circuit 420 to activate the sense amplifier 415 according to the delay time until the 7 signal is fixed.
Adjust the delay time and pulse width of. As described above, the circuit of FIG. 12 makes it possible to control the sense amplifier to operate during reading and not to operate during writing. 6, FIG. 9, and FIG.
2 constitutes the output port selecting means of the present invention.

[0088]

As described above, according to the present invention,
Since it is possible to realize a 2-port memory by time-division access that can load data to a register file with a waiting time comparable to the access time of 1-port SRAM,
It is possible to improve the throughput of the cache memory of the high performance microprocessor. According to the selector of the present invention, it is possible to perform parallel-serial conversion of an address signal with a simple circuit, and it is possible to provide a circuit suitable for a 2-port memory by time division access. Furthermore, according to the selector control method and control circuit of the present invention, the load
The read for the instruction can be prioritized and accessed first.

[Brief description of drawings]

FIG. 1 is a diagram of a selector (parallel-serial conversion circuit, address buffer circuit) circuit showing an embodiment of the present invention.

FIG. 2 is a block diagram of time division access 2 according to an embodiment of the present invention.
It is a block diagram of a port memory.

FIG. 3 is a diagram showing a concept of access to a 2-port memory by time division access according to the present invention.

FIG. 4 is a diagram showing operation waveforms of the circuit of FIG.

FIG. 5 is a diagram showing an example of an internal clock generation circuit suitable for a two-port memory by time division access according to the present invention.

FIG. 6 is a diagram of a control circuit of the circuit of FIG. 1 showing an embodiment of the present invention.

FIG. 7 is a diagram showing a truth table of the circuit of FIG. 6;

FIG. 8 is a diagram showing an example of an internal 1-port SRAM circuit suitable for a 2-port memory by time division access according to the present invention.

FIG. 9 is a diagram showing an example of a sense amplifier of an internal 1-port SRAM circuit suitable for a 2-port memory by time division access according to the present invention.

10 is a diagram showing an example of a write control signal generation circuit of the circuit of FIG.

FIG. 11 is a diagram showing an outline of operation waveforms of the circuits of FIGS. 8 and 9;

12 is a diagram showing an example of a sense amplifier control signal generation circuit of the circuit of FIG.

FIG. 13 is a diagram showing a concept of conventional 2-port memory access by time division access.

[Explanation of symbols]

1: GND terminal 2: Positive power supply terminal 3,4,17,18: Column selection signal 5,6: Common data line 10,11: Internal clock signal 12,13,14,15: Data line 16,84,85 : Precharge control signal 20: Input port A address signal 21: Input port B address signal 22: Input port A load designation signal 23: Input port A read designation signal 24: Input port A write designation signal 25: Input port B load designation signal 26: Input port B read designation signal 27: Input port B write designation signal 30: Selector control signal 31: Reference clock signal 32: Selector control signal 33: Conflict detection signals 34, 35: Write Control signal 37, 38: Signal for controlling sense amplifier 40, 41: Selector output signal 42, 47: NAND circuit output 43, 44: Inverter circuit output signal 48: Word line 50, 51, 56, 57: Multiplexer output signal 52,53,54,45,46,96,98,36: Reset pulse 60: Input port A address signal 61: Input B address signal 62, 63, 78, 79: Latch circuit output signal (address signal) 64, 65, 77: Multiplexer output signal 66: Multiplexer control signal 67: Control signal 68: Read signal 69: First access 70: Signal read by the second access 71: 72, 92, 93: SR latch circuit output 73: Port 1 output signal 74: Port 2 output signal 75: Port A write data 76: Port B write data 80, 81, 82, 83: Sense amplifier signal input control signal 86, 87, 88, 89: Sense amplifier input signal 90, 91: Sense amplifier start signal 94, 97, 99: Write control signal 95: Write Data 100-129: NMOS transistor 200-242: PMOS transistor 300-315,319,322,324,325,328-331,333,334,335,340
-370: Inverter 316: 3-input NOR circuit 317: 2-input NOR circuit 318, 323, 326, 327: AND-OR-NOT circuit 320: 3-input AND circuit 321, 332, 336, 337, 338, 339: 2-input NAND circuit 400, 401: Multiplexer circuit 402, 403, 412, 421, 422: Latch (reference clock signal 31 is "
404,423: Multiplexer circuit 405: Row decoder circuit 406: Memory cell array 407: Column decoder circuit 408: Control circuit 409,410: SR latch 411: Latch (Transparent when the reference clock signal 31 is "L") 413: Memory cell 414: Write circuit 415, 416: Sense amplifier 417: Delay circuit 418, 419, 420: Delay circuit pulse width adjustment circuit 424: Write circuit 425: Comparison circuit 450: Data bus 500, 502: First access of time division access 501, 503: 2 of time division access Second access 504,505: Transfer data to register file 506,507,508,509: Wait time

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyuki Mizuno 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Metropolitan Institute of Hitachi, Ltd. (72) Makoto Suzuki 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Kenichi Nagata 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi Co., Ltd. Central Research Laboratory (72) Inventor Koichiro Ishibashi 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Hitachi Central Research Institute ( 72) Inventor Toshinobu Shinbo 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitachi Ultra LSI Engineering Co., Ltd. (56) Reference JP-A-7-84987 (JP, A) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/401-11/419

Claims (6)

(57) [Claims] 1. N number of memory cells (N: 1)
A memory cell array having a port number of (the above integer),
A multi-port memory having at least 2N input ports and at least 2N output ports, wherein at least 2 ports are accessed per port of a memory cell array in a time-division manner and within at least one cycle period. An access start control means for starting two accesses of a first access and a second access performed subsequent to the first access, and a port involved in the two accesses as a first input port and a first input port. Two input ports, a first output port and a second
When the read data of the access that needs to be output to another storage element is set to the output port of, the read data for the access from any of the input ports is output to the first output port. A multi-port memory having output port selection means. 2. The first access out of the two accesses that needs to be output to another storage element when accessed from either the first input port or the second input port is performed. 2. The multi-port memory according to claim 1, wherein the access is 1 access. 3. The data output from the second output port
Data is transferred to the data bus, and the time at which data is output from the first output port by the first access is before the time at which read data is output by the second access. The multi-port memory according to claim 2 . 4. The first access is load (loa).
d) A read access for an instruction, and the second access is a write access to a memory for a store instruction, and a write access (refill or reloa) for replacement after a cache miss.
d), or prefetch lookup (pre-fe)
4. The multi-port memory according to claim 1, wherein the multi-port memory is a read access for hit determination of tch lookup. 5. The access start control means, as a control signal of the first input port and the second input port, a first read request signal indicating that the access of each port is read, and Second read request signal, a first write request signal indicating that the access of each port is a write, and a second write request signal, a first write request signal indicating that the access of each port is a load instruction 1 load instruction designating signal, and a second load (lod)
ad) command instruction signal, the first read request signal, the second read request signal, the first write request signal, the second write request signal, the first load (loa)
5. A plurality of ports according to claim 1, wherein d) the instruction instruction signal and the second load instruction instruction signal are used to control the start of the first and second accesses. memory. 6. A multi-port memory, comprising: a first parallel-serial conversion circuit that receives outputs of the first input port and the second input port, respectively, and the first parallel-serial conversion circuit. Is a first multiplexer circuit, a second multiplexer circuit, a first conductivity type first transistor, a second transistor, a third transistor, a fourth transistor, a second conductivity type fifth transistor, and a first A flip-flop, wherein the first transistor and the second transistor are connected in series, the third transistor and the fourth transistor are connected in series, and the first transistor and the second transistor are connected in series Connecting the third transistor and the fourth transistor connected in series in parallel, The drain electrode and the drain electrode of the second transistor are used as the output of the first parallel-serial conversion circuit, the first clock signal is applied to the gate electrode of the second transistor, and the gate electrode of the fourth transistor is applied to the gate electrode of the fourth transistor. A second clock signal is applied, the output of the first multiplexer circuit is applied to the gate electrode of the first transistor, the output of the second multiplexer circuit is applied to the gate electrode of the third transistor, The output of the first parallel-serial conversion circuit is connected to the first flip-flop, the output of the first parallel-serial conversion circuit is connected to the drain electrode of the fifth transistor, and the gate electrode of the fifth transistor is connected. A signal obtained by delaying the output of the first parallel-serial conversion circuit is added to the first clock Phase and a second clock signal the phase of the first input port and said second plurality port memory, wherein the different half of time cycle time of the input ports of No..