JP3497963B2 - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JP3497963B2 JP3497963B2 JP01622997A JP1622997A JP3497963B2 JP 3497963 B2 JP3497963 B2 JP 3497963B2 JP 01622997 A JP01622997 A JP 01622997A JP 1622997 A JP1622997 A JP 1622997A JP 3497963 B2 JP3497963 B2 JP 3497963B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- supply terminal
- potential
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Microcomputers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
- Dram (AREA)
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電圧変換回路を内
蔵するＬＳＩ等の集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device such as an LSI having a built-in voltage conversion circuit.
【０００２】[0002]
【従来の技術】従来、異なる電源電圧を半導体ＩＣ回路
装置内部に供給する方法としては、例えば特開平4−345
995 号及び特開平8−211954 号に示されている電圧降圧
方法がある。これを図２に示す。図２において、電圧降
圧回路１０の降圧電圧１２と、電圧降圧回路１０を経由
しない外部電源電圧８とを電源切り換え回路１１により
択一的に導出して、内部ロジック５の内部電源電圧７と
して用いるようになっている。この電源切り換え回路１
１の切り換え制御の為に、電源電圧検出回路９が設けら
れており、外部電源電圧８がある判定電圧以下のときに
は、電圧降圧回路１０を介すことなく、直接に外部電源
電圧８を内部電源電圧７とするものである。図２中の電
圧降圧回路の例としては図３に示す様なものがある。図
３において、外部電源電圧８は電圧降圧回路１０により
電圧が降圧され、この降圧電圧１２により内部電源負荷
回路１３を制御して降圧電圧１２として出力される様に
なっている。2. Description of the Related Art Conventionally, as a method for supplying different power supply voltages to the inside of a semiconductor IC circuit device, for example, Japanese Patent Application Laid-Open No. 4-345 is known.
There is a voltage step-down method shown in Japanese Patent No. 995 and Japanese Patent Application Laid-Open No. 8-211954. This is shown in FIG. In FIG. 2, the step-down voltage 12 of the voltage step-down circuit 10 and the external power supply voltage 8 not passing through the voltage step-down circuit 10 are selectively derived by the power supply switching circuit 11 and used as the internal power supply voltage 7 of the internal logic 5. It is like this. This power supply switching circuit 1
The power supply voltage detection circuit 9 is provided for the switching control of No. 1 and when the external power supply voltage 8 is lower than a certain judgment voltage, the external power supply voltage 8 is directly supplied to the internal power supply without using the voltage down converter 10. The voltage is set to 7. An example of the voltage step-down circuit in FIG. 2 is shown in FIG. In FIG. 3, the external power supply voltage 8 is stepped down by the voltage step-down circuit 10, and the step-down voltage 12 controls the internal power supply load circuit 13 to output it as the step-down voltage 12.
【０００３】電圧降圧回路１０は、抵抗１４とＮチャネ
ル型ＭＯＳトランジスタ１５とによる分圧回路と、この
分圧出力を差動入力の一方とする差動回路からなる。こ
の差動回路は差動対のＮチャネル型ＭＯＳトランジスタ
２４，２５と電流源用Ｎチャネル型ＭＯＳトランジスタ
２６と、カレントミラー型アクティブロードであるＰチ
ャネル型ＭＯＳトランジスタ２１，２２とからなってい
る。The voltage step-down circuit 10 is composed of a voltage dividing circuit including a resistor 14 and an N-channel MOS transistor 15, and a differential circuit using the voltage dividing output as one of differential inputs. This differential circuit is composed of N-channel MOS transistors 24 and 25 of a differential pair, N-channel MOS transistor 26 for current source, and P-channel MOS transistors 21 and 22 which are current mirror active loads.
【０００４】Ｎチャネル型ＭＯＳトランジスタ２４のド
レイン出力は内部電源負荷回路１３を構成するＰチャネ
ル型ＭＯＳトランジスタ２３のゲート入力となってお
り、このＰチャネル型ＭＯＳトランジスタ２３のソース
には外部電源電圧８が印加されている。そして、そのド
レイン出力から降圧電圧１２が導出されて内部回路（図
示せず）の動作電源となると共に、差動回路の差動入力
のＮチャネル型ＭＯＳトランジスタ２５のゲート入力へ
印加されることにより、フィードバックされている。こ
の構成により、抵抗１４とＮチャネル型ＭＯＳトランジ
スタ１５とによる分圧出力２７と降圧電圧１２とが常に
等しくなる様に制御されるものである。例えば外部電源
電圧８が５Ｖのとき降圧電圧１２は３Ｖになる様に設計
される。The drain output of the N-channel MOS transistor 24 serves as the gate input of the P-channel MOS transistor 23 forming the internal power supply load circuit 13, and the source of the P-channel MOS transistor 23 has an external power supply voltage 8 Is being applied. Then, the step-down voltage 12 is derived from the drain output to serve as an operating power supply for an internal circuit (not shown) and is applied to the gate input of the N-channel type MOS transistor 25 of the differential input of the differential circuit. , Have been fed back. With this configuration, the divided output 27 by the resistor 14 and the N-channel MOS transistor 15 and the step-down voltage 12 are controlled to be always equal. For example, the step-down voltage 12 is designed to be 3V when the external power supply voltage 8 is 5V.
【０００５】又、例えは特開平7−31134号に示されてい
る電圧昇圧方法がある。Further, for example, there is a voltage boosting method disclosed in JP-A-7-31134.
【０００６】これを図４に示す。図４において、Ｎチャ
ネル型ＭＯＳトランジスタ３２のソース側とゲート側を
外部電源電圧８に接続し、ドレイン側をＮチャネル型Ｍ
ＯＳトランジスタ３１のゲート側３９に接続する。Ｎチ
ャネル型ＭＯＳトランジスタのソース側を外部電源電圧
８に接続する。Ｎチャネル型ＭＯＳトランジスタ３１の
ソース側とゲート側をＮチャネル型ＭＯＳトランジスタ
２９のドレイン側４０に接続し、ドレイン側をＮチャネ
ル型ＭＯＳトランジスタ２８のゲート側４１に接続す
る。Ｎチャネル型ＭＯＳトランジスタ２８のゲート側４
１に接続する。Ｎチャネル型ＭＯＳトランジスタ３０の
ソース側とゲート側をＮチャネル型ＭＯＳトランジスタ
２８のゲート側４１に接続し、ドレイン側をＮチャネル
型ＭＯＳトランジスタ３１のドレイン側４０に接続す
る。Ｎチャネル型ＭＯＳトランジスタ２８のソース側を
Ｎチャネル型ＭＯＳトランジスタ３１のドレイン側４０
に接続する。Ｎチャネル型ＭＯＳトランジスタ３１のゲ
ート側３９と外部信号端子３７との間に容量３３を接続
する。Ｎチャネル型ＭＯＳトランジスタ２８のゲート側
４１と外部信号端子３８との間に容量３５を接続する。
Ｎチャネル型ＭＯＳトランジスタ３１のドレイン側４０
と外部信号端子３６との間に容量３４を接続する。This is shown in FIG. In FIG. 4, the source side and the gate side of the N-channel type MOS transistor 32 are connected to the external power supply voltage 8, and the drain side is an N-channel type M transistor.
It is connected to the gate side 39 of the OS transistor 31. The source side of the N-channel MOS transistor is connected to the external power supply voltage 8. The source side and the gate side of the N channel type MOS transistor 31 are connected to the drain side 40 of the N channel type MOS transistor 29, and the drain side is connected to the gate side 41 of the N channel type MOS transistor 28. Gate side 4 of N-channel MOS transistor 28
Connect to 1. The source side and the gate side of the N channel type MOS transistor 30 are connected to the gate side 41 of the N channel type MOS transistor 28, and the drain side is connected to the drain side 40 of the N channel type MOS transistor 31. The source side of the N-channel MOS transistor 28 is connected to the drain side 40 of the N-channel MOS transistor 31.
Connect to. The capacitor 33 is connected between the gate side 39 of the N-channel MOS transistor 31 and the external signal terminal 37. A capacitor 35 is connected between the gate side 41 of the N-channel MOS transistor 28 and the external signal terminal 38.
Drain side 40 of N-channel type MOS transistor 31
The capacitor 34 is connected between the external signal terminal 36 and the external signal terminal 36.
【０００７】まず外部信号端子３６，３７，３８の電位
を全てＧＮＤレベルとし、Ｎチャネル型ＭＯＳトランジ
スタ３２はソース側とゲート側に外部電源電圧を印加す
る為接続点３９の電位は（外部電源電圧−Ｎチャネル型
ＭＯＳトランジスタのスレシュホールド電圧、以下Ｖtn
と称す）となり、Ｎチャネル型ＭＯＳトランジスタ３１
はソース側に外部電源電圧が印加されゲート側３９には
（外部電源電圧−Ｖtn）が印加されているため接続点４
０の電位は(外部電源電圧−２Ｖtn)となり、Ｎチャネル
型ＭＯＳトランジスタ２９のソース側４０とゲート側４
０の電位は（外部電源電圧−２Ｖtn）となり、Ｎチャネ
ル型ＭＯＳトランジスタ２９のソース側４０とゲート側
４０に（外部電源電圧−２Ｖtn）が印加されている為接
続点４１の電位は（外部電源電圧−３Ｖtn）となり、Ｎ
チャネル型ＭＯＳトランジスタ２８はソース側４０に
（外部電源電圧−２Ｖtn）が印加されゲート側には（外
部電源電圧−３Ｖtn）が印加されている為内部電源電圧
７は（外部電源電圧−４Ｖtn）となる。First, all the potentials of the external signal terminals 36, 37 and 38 are set to the GND level, and since the N-channel MOS transistor 32 applies the external power supply voltage to the source side and the gate side, the potential at the connection point 39 is (external power supply voltage -Threshold voltage of N channel type MOS transistor, below Vtn
Is called), and the N-channel type MOS transistor 31
Since the external power supply voltage is applied to the source side and the (external power supply voltage −Vtn) is applied to the gate side 39, the connection point 4 is
The potential of 0 becomes (external power supply voltage-2Vtn), and the source side 40 and the gate side 4 of the N-channel type MOS transistor 29 are
The potential of 0 is (external power supply voltage-2Vtn), and the potential of the connection point 41 is (external power supply voltage) because (external power supply voltage-2Vtn) is applied to the source side 40 and the gate side 40 of the N-channel MOS transistor 29. Voltage -3Vtn) and N
In the channel type MOS transistor 28, (external power supply voltage-2Vtn) is applied to the source side 40 and (external power supply voltage-3Vtn) is applied to the gate side, so the internal power supply voltage 7 is (external power supply voltage-4Vtn). Become.
【０００８】次に、外部信号端子３７の電位をＧＮＤレ
ベルから外部電源電圧レベルに変化させる。この時接続
点３９の電位は（外部電源電圧−Ｖtn）から（２倍の外
部電源電圧−Ｖtn）に変化する為Ｎチャネル型ＭＯＳト
ランジスタ３１のゲート側の電位はソース側の電位（外
部電源電圧＋Ｖtn）より高くなり接続点４０の電位はＮ
チャネル型ＭＯＳトランジスタ３１のソース側電位と同
じ外部電源電圧電位に変化する。Next, the potential of the external signal terminal 37 is changed from the GND level to the external power supply voltage level. At this time, the potential of the connection point 39 changes from (external power supply voltage −Vtn) to (double external power supply voltage −Vtn), so that the gate side potential of the N-channel MOS transistor 31 is the source side potential (external power supply voltage + Vtn) and the potential at the connection point 40 is N
The external power supply voltage potential is the same as the source side potential of the channel type MOS transistor 31.
【０００９】その後、外部信号端子３７の電位を外部電
源電圧レベルからＧＮＤレベルに変化させると、接続点
３９の電位は（２倍の外部電源電圧−Ｖtn）から（外部
電源電圧−Ｖtn）へ変化し、Ｎチャネル型ＭＯＳトラン
ジスタ３１がＯＦＦ状態となり接続点４０の電位は外部
電源電圧が保持されたままとなる。外部信号端子３７の
電位が立ち下がってから外部信号端子３６の電位をＧＮ
Ｄレベルから外部電源電圧レベルに変化させる。この
時、接続点４０の電位は外部電源電圧から２倍の外部電
源電圧へ変化し、接続点４１の電位は（２倍の外部電源
電圧−Ｖtn）となる。After that, when the potential of the external signal terminal 37 is changed from the external power supply voltage level to the GND level, the potential of the connection point 39 is changed from (double external power supply voltage −Vtn) to (external power supply voltage −Vtn). Then, the N-channel MOS transistor 31 is turned off, and the potential of the connection point 40 remains held at the external power supply voltage. After the potential of the external signal terminal 37 falls, set the potential of the external signal terminal 36 to GN.
The D level is changed to the external power supply voltage level. At this time, the potential of the connection point 40 changes from the external power supply voltage to the double external power supply voltage, and the potential of the connection point 41 becomes (double the external power supply voltage-Vtn).
【００１０】外部信号端子３６の電位がＧＮＤレベルか
ら外部電源電圧レベルへ変化してから外部信号端子３８
の電位をＧＮＤレベルから外部電源電圧レベルへ変化さ
せる。この時、Ｎチャネル型ＭＯＳトランジスタ３０の
ソース側とゲート側が接続点４１に接続されドレイン側
は接続点４０に接続されている為に、接続点４１の電位
は（２倍の外部電源電圧＋Ｖtn）に変化し、Ｎチャネル
型ＭＯＳトランジスタ２８のゲート側の電位はソース側
４１の電位（２倍の外部電源電圧＋Ｖtn）となる為、内
部電源電圧７の電位はＮチャネル型ＭＯＳトランジスタ
２８のソース側４０の電位と同じ２倍の外部電源電圧と
なる。そして、外部信号端子３６の電位を外部電源電圧
レベルからＧＮＤレベルへ変化させることによりＮチャ
ネル型ＭＯＳトランジスタ３０のドレイン側４０の電位
は外部電源電圧になる為Ｎチャネル型ＭＯＳトランジス
タ３０のソース側とゲート側に接続する接続点４１の電
位はドレイン側の電位（外部電源電圧＋Ｖtn）まで変化
する。After the potential of the external signal terminal 36 changes from the GND level to the external power supply voltage level, the external signal terminal 38
The potential of is changed from the GND level to the external power supply voltage level. At this time, since the source side and the gate side of the N-channel MOS transistor 30 are connected to the connection point 41 and the drain side is connected to the connection point 40, the potential of the connection point 41 is (double the external power supply voltage + Vtn). Since the potential on the gate side of the N-channel type MOS transistor 28 becomes the potential on the source side 41 (double the external power supply voltage + Vtn), the potential of the internal power supply voltage 7 is on the source side of the N-channel MOS transistor 28. The external power supply voltage is twice as high as the potential of 40. Then, by changing the potential of the external signal terminal 36 from the external power supply voltage level to the GND level, the potential of the drain side 40 of the N-channel MOS transistor 30 becomes the external power supply voltage, so that the potential of the source side of the N-channel MOS transistor 30 becomes The potential of the connection point 41 connected to the gate side changes to the potential on the drain side (external power supply voltage + Vtn).
【００１１】外部信号端子３６の電位が立ち下がってか
ら外部信号端子３８の電位を外部電源電圧レベルからＧ
ＮＤレベルに変化させると、Ｎチャネル型ＭＯＳトラン
ジスタ２９のソース側とドレイン側に接続している接続
点４０の電位は外部電源電圧となっている為、Ｎチャネ
ル型ＭＯＳトランジスタ２９のドレイン側の接続点４１
の電位は（外部電源電圧−Ｖtn）に変化する。その為、
Ｎチャネル型ＭＯＳトランジスタ２８はＯＦＦ状態とな
り内部電源電位は２倍の外部電源電圧の電位が保持され
たままとなる。After the potential of the external signal terminal 36 falls, the potential of the external signal terminal 38 is changed from the external power source voltage level to G
When the potential is changed to the ND level, the potential of the connection point 40 connecting the source side and the drain side of the N-channel type MOS transistor 29 is the external power supply voltage. Therefore, the connection of the drain side of the N-channel type MOS transistor 29 is made. Point 41
Changes to (external power supply voltage-Vtn). For that reason,
The N-channel MOS transistor 28 is turned off, and the internal power supply potential remains twice as high as the external power supply voltage.
【００１２】[0012]
【発明が解決しようとする課題】この様に従来技術で
は、ＬＳＩ内部に電圧変換回路を内蔵するＬＳＩは、外
部電源電圧もしくは電圧変換回路にて電圧を昇圧，降圧
した電圧のみ供給可能であった、したがってＬＳＩ内部
ロジックに供給する実動作電圧がＬＳＩ外部から直接制
御することが出来ない。As described above, according to the prior art, an LSI having a voltage conversion circuit built-in inside the LSI can supply only an external power supply voltage or a voltage obtained by stepping up or down the voltage by the voltage conversion circuit. Therefore, the actual operating voltage supplied to the LSI internal logic cannot be controlled directly from outside the LSI.
【００１３】又、電源電圧検出回路，電源切り換え回路
をＬＳＩ内部に内蔵すると、チップ面積が大きくなる。If the power supply voltage detection circuit and the power supply switching circuit are built in the LSI, the chip area becomes large.
【００１４】システム面ではＬＳＩ内部に電圧変換回路
を内蔵するＬＳＩと同一システム内で使用する周辺ＬＳ
Ｉの、実動作電圧がＬＳＩ内部に電圧変換回路を内蔵す
るＬＳＩと同じ電源電圧を必要とした場合、周辺ＬＳＩ
内部に電圧変換回路を備えていなければ、別に電圧変換
回路を設けなければならない。In terms of system, a peripheral LS used in the same system as an LSI having a voltage conversion circuit built in the LSI.
If the actual operating voltage of I requires the same power supply voltage as the LSI having a voltage conversion circuit inside the LSI, the peripheral LSI
If the voltage conversion circuit is not provided inside, a separate voltage conversion circuit must be provided.
【００１５】[0015]
【課題を解決するための手段】そこで本発明では、ＬＳ
Ｉ等の集積回路装置に供給する為の電源端子とは別に、
入出力可能な電源端子を設けることにより、集積回路装
置の実動作電圧が集積回路装置の外部から直接制御する
ことが出来るようにし、電源電圧検出回路，電源切り換
え回路を不要とする。又、この電源端子から集積回路装
置の実動作電圧を出力可能にし、この電源端子から周辺
回路またはシステム用の電源を供給可能にすることによ
り、周辺回路またはシステム用の電源回路を別にシステ
ム内に設置する必要がなくなることを実現する。Therefore, in the present invention, the LS
In addition to the power supply terminal for supplying to the integrated circuit device such as I,
By providing the input / output power supply terminal, the actual operating voltage of the integrated circuit device can be directly controlled from outside the integrated circuit device, and the power supply voltage detection circuit and the power supply switching circuit are unnecessary. Also, by making it possible to output the actual operating voltage of the integrated circuit device from this power supply terminal and supply the power supply for the peripheral circuit or the system from this power supply terminal, the power supply circuit for the peripheral circuit or the system can be separately provided in the system. Realize that there is no need to install.
【００１６】本願により開示される発明の概要を簡単に
説明すれば以下の通りである。The outline of the invention disclosed by the present application will be briefly described as follows.
【００１７】集積回路装置内部に内蔵した電圧変換回路
により電圧変換された後の電源ラインに、直接外部から
電源を入力可能な外部端子を設ける。この端子は内蔵電
圧変換回路からの電圧を外部へ出力することもできる。An external terminal to which power can be directly input from the outside is provided on the power line after the voltage is converted by the voltage conversion circuit built in the integrated circuit device. This terminal can also output the voltage from the built-in voltage conversion circuit to the outside.
【００１８】前記手段によれば、集積回路装置の実動作
電圧が外部から直接制御することが可能となり、チップ
面積の縮小にもなる。According to the above means, the actual operating voltage of the integrated circuit device can be directly controlled from the outside, and the chip area can be reduced.
【００１９】又、周辺回路またはシステムに電圧変換後
の電源電圧を供給出来る為、システム内の電圧変換回路
の節約が可能となる。Further, since the power supply voltage after the voltage conversion can be supplied to the peripheral circuits or the system, the voltage conversion circuit in the system can be saved.
【００２０】[0020]
（実施例１）請求項１および請求項３に関わる実施例を
図１に示す。本例は内部電源電圧を外部電源から得る
か、内部降圧した電源から得るか、両方を選択可能にし
た例である。(Embodiment 1) An embodiment relating to claims 1 and 3 is shown in FIG. This example is an example in which both the internal power supply voltage can be obtained from an external power supply or an internally stepped down power supply, and both can be selected.
【００２１】電源端子１はＬＳＩ６の外部電源端子の１
本で、電源端子１から入力された電源は電圧変換回路４
に入力される。電圧変換回路４によって変換された内部
電源電圧７は内部ロジック５へ入力されるのと並行し
て、もうひとつの電源端子の電源端子２に接続される。
一方内部ロジック５の接地電位の電源はＧＮＤ端子３へ
接続する。次に、電圧変換回路４の実施例を図５に示
す。電源端子１は、デプレッション形ｎチャネルＭＯＳ
トランジスタ（以下、ＮＤＭＯＳと称す）１７のソース
に接続され、NDMOS17のドレインは内部電源電圧７へ接
続される。The power supply terminal 1 is an external power supply terminal 1 of the LSI 6.
In this book, the power input from the power supply terminal 1 is the voltage conversion circuit 4
Entered in. The internal power supply voltage 7 converted by the voltage conversion circuit 4 is connected to the power supply terminal 2 of the other power supply terminal while being input to the internal logic 5.
On the other hand, the ground potential power source of the internal logic 5 is connected to the GND terminal 3. Next, an embodiment of the voltage conversion circuit 4 is shown in FIG. Power supply terminal 1 is a depletion type n-channel MOS
The source of a transistor (hereinafter referred to as NDMOS) 17 is connected, and the drain of the NDMOS 17 is connected to the internal power supply voltage 7.
【００２２】NDMOS17のゲート電圧１６は接地電位へ接
続する。The gate voltage 16 of the NDMOS 17 is connected to the ground potential.
【００２３】ＮＤＭＯＳは、一般にソースに供給した電
圧とゲート電圧間の電圧差がNDMOSのスレシュホールド
電圧ＮＶthＤ以下の場合、ＮＤＭＯＳはＯＮ状態である
ためドレインにはソースに供給した電圧と同じ電圧が供
給される。一方、ソースに供給した電圧とＮＤＭＯＳの
ゲート電圧間の電位差がＮＤＭＯＳのスレシュホールド
電圧ＮＶthＤ以上の場合もＮＤＭＯＳはＯＮ状態である
がＮＤＭＯＳのスレシュホールド電圧ＮＶthＤでクラン
プされるため、ＮＤＭＯＳのスレシュホールド電圧ＮＶ
thＤ以上の電圧はドレインから出力されない。このクラ
ンプ動作を利用し、本例ではNDMOS17 のゲート電圧１６
は接地電位に固定する。これにより電源端子１から入力
された電圧はNDMOS17 のスレシュホールド電圧ＮＶthＤ
でクランプされるため内部電源電圧７はNDMOS17 のスレ
シュホールド電圧ＮＶthＤ以上になることはない。In the NDMOS, in general, when the voltage difference between the voltage supplied to the source and the gate voltage is equal to or lower than the threshold voltage NVthD of the NDMOS, the NDMOS is in the ON state and the same voltage as the voltage supplied to the source is supplied to the drain. To be done. On the other hand, even when the potential difference between the voltage supplied to the source and the gate voltage of the NDMOS is equal to or higher than the threshold voltage NVthD of the NDMOS, the NDMOS is in the ON state but is clamped by the threshold voltage NVthD of the NDMOS, and thus the threshold voltage of the NDMOS. NV
A voltage above thD is not output from the drain. Using this clamp operation, in this example, the gate voltage of NDMOS17 16
Is fixed to ground potential. As a result, the voltage input from the power supply terminal 1 is the threshold voltage NVthD of the NDMOS 17.
The internal power supply voltage 7 does not exceed the threshold voltage NVthD of the NDMOS 17 because it is clamped by.
【００２４】この方式では、内部ロジック５に直接外部
から内部電源電圧７を供給したい場合は、電源端子２か
ら入力可能である。この時、電源端子１と電源端子２に
電位差が生じると、電源端子１と電源端子２にNDMOS17
を通して電流が流れてしまう。そこで、図１中の様に電
源端子１と電源端子２を接続させることにより、電源端
子１の電位を電源端子２と等電位とし、この電流を防ぐ
ことが可能である。一方、内部電源電圧７を電圧変換回
路４によって降圧された電圧で使用したい場合、電源端
子２を図８の様に開放状態にし、電源供給端子を電源端
子１のみとすることにより、電圧変換回路４の出力電圧
を有効とすることが可能である。In this system, when it is desired to directly supply the internal power supply voltage 7 to the internal logic 5, the power can be input from the power supply terminal 2. At this time, if a potential difference occurs between the power supply terminal 1 and the power supply terminal 2, the NDMOS 17
An electric current will flow through it. Therefore, by connecting the power supply terminal 1 and the power supply terminal 2 as shown in FIG. 1, it is possible to make the potential of the power supply terminal 1 equal to that of the power supply terminal 2 and prevent this current. On the other hand, when it is desired to use the internal power supply voltage 7 at the voltage reduced by the voltage conversion circuit 4, the power supply terminal 2 is opened as shown in FIG. 8 and the power supply terminal is the power supply terminal 1 only. It is possible to make the output voltage of 4 valid.
【００２５】以上をまとめると、内部ロジック５に直接
外部から内部電源電圧７を供給したい場合は電源端子１
と電源端子２を短絡し、電圧を外部から供給する。ま
た、内部で降圧した電源電圧を供給したい場合、電源端
子１から電源を供給し、電源端子２を開放状態にする。
この様にして、本例では、内部電源電圧７を電圧変換回
路４から得る従来の仕様を保持したうえで、さらに、Ｌ
ＳＩの実動作電圧がLSI外部から直接制御することが可
能となる。To summarize the above, if it is desired to directly supply the internal power supply voltage 7 to the internal logic 5, the power supply terminal 1
And the power supply terminal 2 are short-circuited, and the voltage is supplied from the outside. When it is desired to supply the internally reduced power supply voltage, power is supplied from the power supply terminal 1 and the power supply terminal 2 is opened.
In this way, in this example, the internal power supply voltage 7 is kept from the conventional specifications obtained from the voltage conversion circuit 4, and
The actual operating voltage of SI can be controlled directly from outside the LSI.
【００２６】（実施例２）実施例１は電圧変換回路４が
降圧回路の場合の実施例であり、電圧変換回路４が昇圧
回路の場合についての実施例を図６に示す。電源端子
１，エンハンスメント型Ｐチャネル型ＭＯＳトランジス
タ（以下、ＰＭＯＳと称す）４２，４３，４４，４５，
４６，４７，４８，４９，５０，エンハンスメント型Ｎ
チャネル型ＭＯＳトランジスタ（以下、ＮＭＯＳと称
す）５１，５２，５３，５４，５５，容量５７，５８，
外部信号端子６５，内部電源電圧７から構成される。外
部信号端子はPMOS42とNMOS51で構成するインバータの入
力に接続し、そのインバータの出力は容量５７に接続
し、容量５７の逆側はPMOS45とNMOS54で構成するインバ
ータのドレイン及びPMOS46のドレイン及びPMOS49のソー
ス及びPMOS50のゲートに接続している。又、外部信号端
子はPMOS43とNMOS52で構成するインバータの入力に接続
し、そのインバータの出力はPMOS44とNMOS53で構成する
インバータの入力、PMOS47とNMOS55で構成するインバー
タの入力に接続している。PMOS44とNMOS53で構成するイ
ンバータの出力は容量５８に接続し、容量５８の逆側は
PMOS47とNMOS55で構成するインバータのドレイン及びPM
OS48のドレイン及びPMOS50のソース及びPMOS49のゲート
に接続している。(Embodiment 2) Embodiment 1 is an embodiment in which the voltage conversion circuit 4 is a step-down circuit, and FIG. 6 shows an embodiment in which the voltage conversion circuit 4 is a booster circuit. Power supply terminal 1, enhancement type P channel type MOS transistor (hereinafter referred to as PMOS) 42, 43, 44, 45,
46, 47, 48, 49, 50, enhancement type N
Channel type MOS transistors (hereinafter referred to as NMOS) 51, 52, 53, 54, 55, capacitors 57, 58,
It is composed of an external signal terminal 65 and an internal power supply voltage 7. The external signal terminal is connected to the input of the inverter composed of PMOS 42 and NMOS 51, the output of the inverter is connected to the capacitor 57, and the opposite side of the capacitor 57 is the drain of the inverter composed of PMOS 45 and NMOS 54, the drain of PMOS 46 and the PMOS 49. It is connected to the source and the gate of PMOS 50. The external signal terminal is connected to the input of the inverter composed of PMOS43 and NMOS52, and the output of the inverter is connected to the input of the inverter composed of PMOS44 and NMOS53 and the input of the inverter composed of PMOS47 and NMOS55. The output of the inverter composed of the PMOS 44 and the NMOS 53 is connected to the capacitor 58, and the opposite side of the capacitor 58 is
The drain and PM of the inverter composed of PMOS 47 and NMOS 55
It is connected to the drain of OS48, the source of PMOS50, and the gate of PMOS49.
【００２７】電源端子１はPMOS42，４３，４４，４６，
４８のソースに接続し、NMOS51，５２，５３，５４，５
５のソースはＧＮＤに接続している。又PMOS49，５０の
ドレインが接続されて内部電源電圧７となる。The power supply terminal 1 has PMOSs 42, 43, 44, 46,
48 sources, NMOS51,52,53,54,5
The source of 5 is connected to GND. Further, the drains of the PMOSs 49 and 50 are connected to become the internal power supply voltage 7.
【００２８】外部信号端子６５にPMOS42，４３，４５の
スレッシュホールド電圧以上の電圧を入力するとPMOS42
がＯＮ状態となり接続点６０の電位は電源端子１の電位
になり、容量５７に電荷が充電される、又PMOS45がＯＮ
状態になるとPMOS46のゲート電位は電源端子１の電位と
なりPMOS46はＯＦＦ状態となる為、接続点６１は電源端
子１の電位となる。次に外部信号端子６５にNMOS51，５
２，５４のスレッシュホールド電圧以上の電圧を入力す
るとNMOS52がＯＮ状態となり接続点５９はGND電位とな
り先程と同様に容量５８に電荷が充電される。When a voltage higher than the threshold voltage of the PMOS 42, 43, 45 is input to the external signal terminal 65, the PMOS 42
Is turned on, the potential of the connection point 60 becomes the potential of the power supply terminal 1, the capacitor 57 is charged, and the PMOS 45 is turned on.
In this state, the gate potential of the PMOS 46 becomes the potential of the power supply terminal 1 and the PMOS 46 is in the OFF state, so that the connection point 61 becomes the potential of the power supply terminal 1. Next, the external signal terminal 65 is connected to the NMOS 51, 5
When a voltage higher than the threshold voltage of 2, 54 is input, the NMOS 52 is turned on, the connection point 59 becomes the GND potential, and the electric charge is charged in the capacitor 58 as before.
【００２９】このときPMOS46がＯＮ状態である為、容量
５７は電源端子１の電荷を保持している。次に、再び外
部信号端子６５にPMOS42，４３，４５のスレッシュホー
ルド電圧以上の電圧を入力するとPMOS42がＯＮ状態とな
り接続点６０の電位は電源端子１の電位になり、容量５
７に電荷が充電される、しかし容量５７に電源端子１と
同様の電荷が充電されている為接続点６１は２倍の電源
端子１の電位となる。以上の動作を繰り返し行うことに
より、常に接続点６１，６３の電位は２倍の電源端子１
の電位になる。接続点６１，６３の電位はPMOS49，５０
を通って内部電源電圧７の電位となる、内部電源電圧７
の電位は常に２倍の電源端子１の電位に保持されるのは
言うまでもない。At this time, since the PMOS 46 is in the ON state, the capacitor 57 holds the electric charge of the power supply terminal 1. Next, when a voltage higher than the threshold voltage of the PMOS 42, 43, 45 is input to the external signal terminal 65 again, the PMOS 42 is turned on, the potential of the connection point 60 becomes the potential of the power supply terminal 1, and the capacitance 5
7 is charged, but since the capacitor 57 is charged with the same charge as the power supply terminal 1, the connection point 61 has twice the potential of the power supply terminal 1. By repeating the above operation, the potentials of the connection points 61 and 63 are always doubled.
It becomes the potential of. The potentials of the connection points 61 and 63 are PMOS 49 and 50.
Internal power supply voltage 7 which becomes the potential of internal power supply voltage 7 through
It goes without saying that the potential of is always held at twice the potential of the power supply terminal 1.
【００３０】又、図９中の様に電源端子１と電源端子２
を独立にし、かつ、電源端子１を開放状態にし、電源端
子２からＬＳＩの実動作電圧を印加することによりＬＳ
Ｉ外部から直接制御することが可能となる。Further, as shown in FIG. 9, the power supply terminal 1 and the power supply terminal 2
Is independent, the power supply terminal 1 is opened, and the actual operating voltage of the LSI is applied from the power supply terminal 2 to the LS.
It becomes possible to control directly from the outside.
【００３１】（実施例３）請求項２に関わる実施例を図
７に示す。ＬＳＩ６の構成要素、電源端子１，電源端子
２，ＧＮＤ端子３，電圧変換回路４，内部ロジック５，
内部電源電圧７は実施例１と同じである。システム構成
要素として、ＬＳＩ６の周辺に周辺ＬＳＩ１８，周辺Ｌ
ＳＩ１９，周辺ＬＳＩ２０が電源端子２を電源とするよ
うに接続される。電圧変換回路４についても実施例１の
図５で示した構成と同一のものを使用する。実施例１で
示した様に図７中で電源端子１に供給した電圧は電圧変
換回路４により電圧変換され内部電源電圧７となり、内
部ロジック５へ供給される。本実施例では実施例１と同
様に電源端子２を設け、かつ電源端子１と電源端子２を
独立にすることにより電源端子１に供給された電圧を電
源端子２を介して周辺ＬＳＩ１８，周辺ＬＳＩ１９，周
辺ＬＳＩ２０に供給可能としたものである。この時、電
圧変換回路４の中のNDMOS17 を介して内部ロジック５と
周辺LSI18 ，周辺ＬＳＩ１９，周辺ＬＳＩ２０に電源を
供給するため、このNDMOS17は 電流容量を大きくする必
要がある。そのためには大きなＭＯＳサイズを用いる。
これによりＬＳＩ６の電源端子２から内部ロジック５と
周辺ＬＳＩ１８，周辺LSI19 ，周辺ＬＳＩ２０のすべて
に電源供給可能となる。NDMOS17 の電流容量を大きくす
るとＭＯＳサイズも大きくなりＬＳＩ６のチップ面積も
増大する。このため、NDMOS17 のＭＯＳサイズ設計時
に、内部ロジック５と周辺ＬＳＩ１８，周辺ＬＳＩ１
９，周辺ＬＳＩ２０の負荷電流を考慮しＭＯＳサイズを
最適化することにより、ＬＳＩ６のチップ面積が必要以
上に大きくなることはない。(Embodiment 3) An embodiment relating to claim 2 is shown in FIG. Components of LSI 6, power supply terminal 1, power supply terminal 2, GND terminal 3, voltage conversion circuit 4, internal logic 5,
The internal power supply voltage 7 is the same as that in the first embodiment. As system components, peripheral LSI 18 and peripheral L around LSI 6
The SI 19 and the peripheral LSI 20 are connected so that the power supply terminal 2 is used as a power supply. The same voltage conversion circuit 4 as that of the first embodiment shown in FIG. 5 is used. As shown in the first embodiment, the voltage supplied to the power supply terminal 1 in FIG. 7 is converted into the internal power supply voltage 7 by the voltage conversion circuit 4 and supplied to the internal logic 5. In this embodiment, as in the first embodiment, the power supply terminal 2 is provided, and the power supply terminal 1 and the power supply terminal 2 are independent, so that the voltage supplied to the power supply terminal 1 is supplied to the peripheral LSI 18 and the peripheral LSI 19 via the power supply terminal 2. , Can be supplied to the peripheral LSI 20. At this time, since power is supplied to the internal logic 5, the peripheral LSI 18, the peripheral LSI 19, and the peripheral LSI 20 via the NDMOS 17 in the voltage conversion circuit 4, the NDMOS 17 needs to have a large current capacity. For that purpose, a large MOS size is used.
As a result, power can be supplied from the power supply terminal 2 of the LSI 6 to all of the internal logic 5, the peripheral LSI 18, the peripheral LSI 19, and the peripheral LSI 20. When the current capacity of the NDMOS 17 is increased, the MOS size also increases and the chip area of the LSI 6 also increases. Therefore, when designing the MOS size of the NDMOS 17, the internal logic 5, the peripheral LSI 18, the peripheral LSI 1
9. By optimizing the MOS size in consideration of the load current of the peripheral LSI 20, the chip area of the LSI 6 does not become larger than necessary.
【００３２】従来なら周辺ＬＳＩ１８，周辺ＬＳＩ１
９，周辺ＬＳＩ２０用の電源回路をシステム内にＬＳＩ
６と独立に設けなければならなかったが、本例では、Ｌ
ＳＩ６の電源端子２から供給可能となり、システムの部
品点数の削減が図れ、簡潔化が可能となる。Conventionally, peripheral LSI 18 and peripheral LSI 1
9. Power supply circuit for peripheral LSI 20 is integrated in the system
6 had to be provided independently, but in this example, L
The power can be supplied from the power supply terminal 2 of SI6, the number of parts of the system can be reduced, and the simplification can be achieved.
【００３３】[0033]
【発明の効果】本発明によれば、入出力可能な電源端子
を設けることにより、ＬＳＩの実動作電圧がＬＳＩ外部
から直接制御することが可能になる。According to the present invention, by providing the input / output power supply terminal, the actual operating voltage of the LSI can be controlled directly from outside the LSI.
【図１】本発明の１実施例の構成を示し電源端子の構成
例を示す。FIG. 1 shows a configuration of an embodiment of the present invention and shows a configuration example of a power supply terminal.
【図２】従来技術の電源電圧の降圧するブロック図の例
を示す。FIG. 2 shows an example of a block diagram for stepping down a power supply voltage in a conventional technique.
【図３】従来技術の電源電圧の降圧する実施例を示す。FIG. 3 shows an embodiment of stepping down the power supply voltage in the prior art.
【図４】従来技術の電源電圧の昇圧する実施例を示す。FIG. 4 shows an example of boosting the power supply voltage in the prior art.
【図５】本発明の１実施例の構成を示し電源電圧変換回
路の例を示す。FIG. 5 shows a configuration of an embodiment of the present invention and shows an example of a power supply voltage conversion circuit.
【図６】本発明の１実施例の構成を示し電源電圧変換回
路の例を示す。FIG. 6 shows a configuration of one embodiment of the present invention and shows an example of a power supply voltage conversion circuit.
【図７】本発明の１実施例の構成を示し電源端子の構成
例を示す。FIG. 7 shows a configuration of one embodiment of the present invention and shows a configuration example of a power supply terminal.
【図８】本発明の１実施例の構成を示し電源端子の構成
例を示す。FIG. 8 shows a configuration of one embodiment of the present invention and shows a configuration example of a power supply terminal.
【図９】本発明の１実施例の構成を示し電源端子の構成
例を示す。FIG. 9 shows a configuration of one embodiment of the present invention and shows a configuration example of a power supply terminal.
１，２…電源端子、３…ＧＮＤ端子、４…電圧変換回
路、５…内部ロジック、６…ＬＳＩ、７…内部電源電
圧、１７…ＮＤＭＯＳ、１８，１９，２０…周辺ＬＳ
Ｉ、４２，４３，４４，４５，４６，４７，４８，４
９，５０…ＰＭＯＳ、５１，５２，５３，５４，５５…
ＮＭＯＳ、５７，５８…容量、６５…外部信号端子。1, 2 ... Power supply terminal, 3 ... GND terminal, 4 ... Voltage conversion circuit, 5 ... Internal logic, 6 ... LSI, 7 ... Internal power supply voltage, 17 ... NDMOS, 18, 19, 20 ... Peripheral LS
I, 42, 43, 44, 45, 46, 47, 48, 4
9, 50 ... PMOS, 51, 52, 53, 54, 55 ...
NMOS, 57, 58 ... Capacitance, 65 ... External signal terminal.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｇ１１Ｃ 11/413 Ｇ１１Ｃ 11/34 ３５４Ｆ Ｈ０１Ｌ 27/04 (72)発明者 沼田 正彦 茨城県日立市弁天町三丁目10番２号 日 立原町電子工業株式会社内 (72)発明者 菅井 賢 茨城県日立市幸町三丁目１番１号 株式 会社 日立製作所 日立工場内 (72)発明者 小池 勝則 茨城県日立市幸町三丁目２番１号 日立 エンジニアリング株式会社内 (72)発明者 三瓶 忠 茨城県日立市幸町三丁目１番１号 株式 会社 日立製作所 日立工場内 (72)発明者 木田 博之 茨城県日立市幸町三丁目１番１号 株式 会社 日立製作所 日立工場内 (56)参考文献 特開 平５−74140（ＪＰ，Ａ) 特開 平１−253949（ＪＰ，Ａ) 実開 平５−59519（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/822 G05F 3/24 G06F 1/26 G06F 15/78 G11C 11/407 G11C 11/413 H01L 27/04 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI G11C 11/413 G11C 11/34 354F H01L 27/04 (72) Inventor Masahiko Numata 3-10-10 Bentencho, Hitachi City, Ibaraki Prefecture (72) Inventor Ken Sugai, 3-1-1 Hachimachi, Hitachi City, Ibaraki Hitachi Ltd., Hitachi Factory (72) Inventor, Katsunori Koike, 3-chome, Saiwaicho, Hitachi City, Ibaraki Prefecture No. 1 In Hitachi Engineering Co., Ltd. (72) Inventor Tadashi Sanpe 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Hiroyuki Kida 3-chome, Saiwaicho, Hitachi, Ibaraki No. 1 Hitachi, Ltd., Hitachi factory (56) References JP-A-5-74140 (JP, A) JP-A-1-253949 (JP, A) JP, U) (58) investigated the field (Int.Cl. 7, DB name) H01L 21/822 G05F 3/24 G06F 1/26 G06F 15/78 G11C 11/407 G11C 11/413 H01L 27/04
Claims (3)
２電源端子に接続される電圧出力ノードとを有する電圧
変換回路と、前記電圧出力ノードに接続され、前記第1電源端子には
外部電源電圧が供給され前記第2電源端子には前記外部
電源電圧が供給されない場合に、前記電圧変換回路から
供給される前記外部電源電圧より小さい電圧が内部動作
電圧として供給され、前記第１及び第２電源端子に前記
外部電源電圧が供給される場合に前記外部電源電圧が前
記内部動作電圧として供給される 内部ロジックとを具備
し、前記電圧変換回路は、前記電圧出力ノードと前記電圧入
力ノードとの間に接続されるソース・ドレイン経路と、
固定的に所定の電圧が供給されるゲートとを有するMOS
トランジスタを有することを特徴とする集積回路装置。 1. A voltage conversion circuit having a first power supply terminal, a second power supply terminal, a voltage input node connected to the first power supply terminal, and a voltage output node connected to the second power supply terminal, Connected to the voltage output node, the first power supply terminal
The external power supply voltage is supplied and the external power is supplied to the second power supply terminal.
If the power supply voltage is not supplied, the voltage conversion circuit
Internal operation at a voltage lower than the external power supply voltage supplied
Is supplied as a voltage to the first and second power supply terminals.
When the external power supply voltage is supplied, the external power supply voltage
With internal logic supplied as internal operating voltage
And, wherein the voltage conversion circuit, the electrostatic pressed and the voltage output node
A source / drain path connected to the force node,
MOS having a gate to which a predetermined voltage is fixedly supplied
An integrated circuit device having a transistor.
記電圧変換回路からの電圧を外部へ出力する機能を有す
ることを特徴とする集積回路装置。2. The integrated circuit device according to claim 1, wherein the second power supply terminal has a function of outputting the voltage from the voltage conversion circuit to the outside.
ンジスタは、ディプレッション型ｎチャネルＭＯＳトラ
ンジスタであり、前記所定の電圧は、接地電圧であるこ
とを特徴とする集積回路装置。3. The integrated circuit device according to claim 1, wherein the MOS transistor is a depletion type n-channel MOS transistor, and the predetermined voltage is a ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01622997A JP3497963B2 (en) | 1997-01-30 | 1997-01-30 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01622997A JP3497963B2 (en) | 1997-01-30 | 1997-01-30 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10214938A JPH10214938A (en) | 1998-08-11 |
| JP3497963B2 true JP3497963B2 (en) | 2004-02-16 |
Family
ID=11910726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01622997A Expired - Fee Related JP3497963B2 (en) | 1997-01-30 | 1997-01-30 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3497963B2 (en) |
-
1997
- 1997-01-30 JP JP01622997A patent/JP3497963B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10214938A (en) | 1998-08-11 |
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