JP3496528B2 - Ferroelectric memory and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory suitable for a non-volatile semiconductor device and a manufacturing method thereof, and more particularly to a ferroelectric memory having a low leak current and improved fatigue characteristics and a manufacturing method thereof .

[0002]

2. Description of the Related Art Conventionally, a ferroelectric memory (FRAM (Ferr
The lead-based oxide ferroelectric material and the bismuth layered structure ferroelectric material are used as the ferroelectric material used in the ferroelectric film in the electrical electric random access memory). As an example of the former lead-based oxide ferroelectric material, PZT (Pb (Zr, T
i) O ₃ ) based ferroelectric materials may be mentioned. This PZT-based ferroelectric material has a property of large spontaneous polarization but low fatigue characteristics. In addition, PZT-based ferroelectric materials have L
It is known that the addition of a cation such as a, Nb or Bi changes the spontaneous polarization and the relative permittivity, and has the effect of reducing the leak current. On the other hand, an example of the latter bismuth layered structure ferroelectric material is SBT.
(SrBi ₂ TaO ₉ ). SBT has a property that fatigue characteristics are good but spontaneous polarization is small.

The fatigue property of a ferroelectric material shows deterioration of spontaneous polarization when a large number of polarization inversions are repeated.

Recently, a method of reducing fatigue by improving a capacitor electrode when an insulating film made of a PZT type ferroelectric material is used as a capacitor insulating film has been studied. Generally, a Pt electrode or a Ti electrode is used as the capacitor electrode, but the RuO _x electrode and the IrO ₂ electrode are PZ electrodes.
Attention has been paid to the fact that the fatigue characteristics of the T-based ferroelectric film can be improved.

Further, a method of reducing fatigue by improving a capacitor insulating film when an insulating film made of a PZT type ferroelectric material is used as a capacitor insulating film is being studied. For example, by adding Li to a PZT type ferroelectric material, P
A ZT-based ferroelectric film having improved fatigue characteristics has been proposed.

Further, when an insulating film made of a PZT type ferroelectric material is used as a capacitor insulating film, a leak current is reduced and a fatigue resistance characteristic is provided by providing a buffer layer between the capacitor electrode and the capacitor insulating film. Ways to improve are being studied. For example, PbTiO ₃ or (Ba, Sr) TiO ₃ is used as the buffer layer, and the generation of leak current and fatigue resistance are improved.

[0007]

However, in the above-mentioned ferroelectric memory, the leakage current from the grain boundary is large,
There is a problem that the fatigue characteristics cannot be significantly improved. There is also a problem that other materials are affected because a ferroelectric memory cannot be produced unless the annealing temperature is raised.

The present invention has been made in view of the above problems, and it is possible to reduce leakage current and improve fatigue resistance by decreasing the annealing temperature to reduce the crystal grain size. Body memory and its manufacture
The purpose is to provide a manufacturing method .

[0009]

The ferroelectric memory according to the present invention SUMMARY OF THE INVENTION comprises a Pb (Zr, Ti) made of O ₃ layer capacitor insulating layer with added Li, the Pb (Zr, Ti) O ₃
It has a buffer layer made of PbTiO ₃ layers laminated on at least one top of the other upper and lower surfaces of the layer, prior to
The PbTiO ₃ layer is one in which Li is added, and
The buffer layer and the capacitor insulating layer are characterized by being crystallized .

Method for manufacturing a ferroelectric memory according to the present invention
Is a process of forming an interlayer insulating film on the substrate,
2 step of forming the conductive film, and a step for forming the capacitor insulating layer.
Process for preparing Rugel liquid and sol-gel liquid for buffer layer
And the sol-gel solution for the buffer layer.
Pre-baking after pin coating, and
After spin coating the sol-gel solution for the insulating layer,
And anneal to form a crystallized buffer layer and key.
Forming a capacitor insulating layer and forming an upper electrode
And a process.

A method of manufacturing a ferroelectric memory according to the present invention includes a step of forming an interlayer insulating film on a substrate, a step of forming first and second conductive films, and a Pb (Z) layer containing Li.
r, Ti) a step of preparing a sol-gel solution for a capacitor insulating layer composed of an O ₃ layer , and a PbTiO ₃ layer added with Li
A step of preparing a sol-gel solution for a buffer layer consisting of
Pre-baking after spin-coating the sol-gel solution for the buffer layer, and spin-coating the sol-gel solution for the capacitor insulating layer, followed by pre-baking and annealing to form a crystallized buffer layer and capacitor insulating layer And a step of forming an upper electrode.

Further, the buffer layer is made of Pb _α TiO ₃
And a value of α is 0.8 to 1.
It is preferably 2. In this case, the Li content is preferably 20 mol% or less with respect to the Pb _α TiO ₃ content.

Furthermore, it is preferable that the thickness of the capacitor insulating layer is 50 to 500 nm and the thickness of the buffer layer is 0.5 to 30 nm.

In the present invention, since Li is added to the Pb (Zr, Ti) O ₃ layer constituting the capacitor insulating layer, the annealing temperature can be lowered and the fatigue characteristics can be improved. .

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The inventors of the present invention have conducted extensive studies to solve the above-mentioned problems, and as a result, Pb _x Zr _(1-y) Ti
_y (hereinafter, also referred to as PZT) and PZT ferroelectric material having a composition containing Li , P
b _alpha TiO ₃ (hereinafter also referred to as PTO.) in by providing a buffer layer having a composition prepared by adding Li, the leakage current can be lowered, fatigue resistance has been found that it is possible to improve.

Embodiments embodying the present invention will be described below with reference to the accompanying drawings. 1 (a) to 1 (d)
FIG. 3 is a cross-sectional view showing a ferroelectric memory according to this example.

In the embodiment shown in FIG. 1A, an interlayer insulating layer 2 made of a SiO ₂ film is provided on a silicon substrate 1, and a first conductive film 3 made of a Ti film and a Pt film are formed thereon. The second conductive film 4 is formed. Further, on the second conductive film 4, a capacitor insulating layer 6a having a composition in which 1% of Li is added to PbZr _0.52 Ti _0.48 , PbTiLi _0.005 O ₃
A ferroelectric memory is formed by sequentially forming a buffer layer 5a made of Pt and an upper conductive film 7 made of Pt film.

In the embodiment shown in FIG. 1B, an interlayer insulating layer 2 made of a SiO ₂ film is provided on a silicon substrate 1, and a first conductive film 3 made of a Ti film and a Pt film are provided thereon. The second conductive film 4 is formed. Further, on the second conductive film 4, a buffer layer 5a made of PbTiLi _{0. 005} O _3, an upper conductive film 7 consisting of a capacitor insulating layer 6a and the Pt film having a composition by adding Li 1% to PbZr _0.52 Ti _0.48 is The ferroelectric memory is formed by being sequentially formed.

In the embodiment shown in FIG. 1C, an interlayer insulating layer 2 made of a SiO ₂ film is provided on a silicon substrate 1, and a first conductive film 3 made of a Ti film and a Pt film are provided thereon. The second conductive film 4 is formed. Further, on the second conductive film 4, PbTiLi _{0. 005} consists O ₃ buffer layer 5a, a composition obtained by adding Li 1% to PbZr _0.52 Ti _0.48 capacitor insulating layer 6a, a buffer layer 5a made of PbTiLi _0.005 O ₃ And the upper conductive film 7 made of a Pt film are sequentially formed to form the ferroelectric memory.

In the embodiment shown in FIG. 1D, an interlayer insulating layer 2 made of a SiO ₂ film is provided on a silicon substrate 1, and a first conductive film 3 made of a Ti film and a Pt film are formed thereon. The second conductive film 4 is formed. Further, on the second conductive film 4, the buffer layers 5b and P made of PbTiO ₃ are formed.
bZr _0.52 Ti _0.48 , a capacitor insulating layer 6a having a composition in which 1% of Li is added, and a buffer layer 5b made of PbTiO ₃
And the upper conductive film 7 made of a Pt film are sequentially formed to form the ferroelectric memory.

In these examples, Pb _α TiO ₃ (hereinafter, P
Also called TO. ), Preferably, since the buffer layer having the composition in which Li is added to PTO is provided, the leak current can be reduced and the fatigue resistance can be improved.

Next, a method for manufacturing the ferroelectric memory according to the present invention, which includes the capacitor insulating layer and the buffer layer having the above composition, will be described. 2A to 2D are sectional views showing a method of manufacturing the ferroelectric memory according to the embodiment of the present invention in the order of steps.

As shown in FIG. 2A, a 450 nm-thickness SiO ₂ film is formed as an interlayer insulating film 2 on the surface of the 6-inch silicon substrate 1 or on the surface by a method similar to the conventional method. Then, a Ti film having a film thickness of 20 nm is formed as the first conductive film 3 and a Pt film having a film thickness of 200 nm is formed as the second conductive film 4 on the entire surface of the interlayer insulating film 2. A specific method for forming the capacitor insulating layer 6 and the buffer layer 5 having the above composition will be described later.

A Ti film having a film thickness of 20 nm is used as the first conductive film 3 of the memory, and a film thickness of 20 is used as the second conductive film 4.
Although the Pt film has a thickness of 0 nm, the thickness is not limited to this, and the thickness of the Ti film is 5 to 50 nm and the thickness of the Pt film is 5 nm.
It is preferably 0 to 500 nm. Preferably,
The Ti film has a thickness of 5 to 20 nm, and the Pt film has a thickness of 100 to 300 nm.

Next, a method for forming the capacitor insulating layer 6 and the buffer layer 5 will be specifically described. The capacitor insulating layer 6 and the buffer layer 5 can be formed by various methods. Here, as an example, a forming method using a sol-gel solution will be shown.

First, a method of forming the capacitor insulating layer 6 will be described. First, lead diacetate trihydrate is put in metaxyethanol which is a solvent, and then heated and stirred at 80 ° C. for 30 to 60 minutes to dissolve lead diacetate trihydrate.

Next, the solution was transferred to a reactor, and at 124 ° C. for 1 hour.
Dehydration is performed by heating and stirring for 2 hours.

Next, after the temperature of the reaction system is lowered to 60 ° C., tetraisopropoxyzirconium, tetraisoproxitane and lithium ethoxide are added to the reaction system, and the mixture is heated and stirred at 124 ° C. for 6 hours.

After completion of stirring, a solvent is further added to the solution so that the total amount becomes 1 mol / liter. As a result, a PZT sol-gel solution of the capacitor insulating layer 6 containing lithium is created. When the coating is used, the sol-gel solution is used at 0.3 mol / liter. Note that all heating and stirring are performed under a nitrogen stream.

Next, a method of forming the buffer layer 5 will be described. The difference between the method of forming the buffer layer 5 and the method of forming the capacitor insulating layer 6 is that the capacitor insulating layer 6
In the case of, the substance added to the reaction system is tetraisopropoxydiene.
Ruconium and tetraisoproxitan and lithium eth
In the case of the buffer layer 5, the substances added to the reaction system are only tetraisoproxitane and lithium ethoxide , whereas the others are the same as the method of forming the capacitor insulating layer 6. Is omitted.

[0031] By creating the above-described buffer layer 5, PTO sol-gel solution of the buffer layer 5 containing lithium is produced. When the coating is used, the PTO sol-gel solution is used at 0.01 mol / liter.

Next, as shown in FIG. 2 (b), a predetermined amount of methoxyethanol was added to the PTO sol-gel solution containing lithium prepared as described above at room temperature to obtain 0.01 mol / mol.
3000 rp on the second conductive film 4 with a concentration of liter
Spin-coat for 30 seconds at a rotation speed of m. Then, it is prebaked at 400 ° C. for 10 minutes. As a result, the buffer layer 5 is formed.

Then, as shown in FIG. 2 (c), a predetermined amount of methoxyethanol was added to the PZT sol-gel solution containing lithium prepared as described above at room temperature to give 0.3 mol / mol.
3000 rp on the buffer layer 5 at a concentration of liter
Spin-coat for 30 seconds at a rotation speed of m. Then, it is prebaked at 400 ° C. for 10 minutes. Thereafter, spin coating and prebaking are repeated 4 times. As a result, the capacitor insulating layer 6 is formed.

Next, annealing is performed in an oxygen atmosphere at 600 ° C. for 1 hour. Or 60 in oxygen atmosphere
Anneal for 1 minute in an infrared image furnace (RTA) at 0 ° C. As a result, the amorphous film is crystallized to form the capacitor insulating layer 6 and the buffer layer 5, respectively. As described above, the method for forming the capacitor insulating layer 6 and the buffer layer 5 is not limited to the method using the sol-gel solution, and it may be formed by the sputtering method or the CVD method.

Further, a Pt film having a thickness of 200 nm is formed as an upper conductive film 7 on the capacitor insulating layer 6 formed as shown in FIG. 2D by sputtering.

In the above-mentioned forming method, the capacitor insulating layer 6 is formed to a thickness of 200 nm, but the film thickness of the capacitor insulating layer 6 is not limited to this, and is 50 to 50.
It is preferably 0 nm. Preferably, the film thickness is 10
It is 0 to 300 nm.

If the film thickness of the capacitor insulating layer 6 is less than 50 nm, it becomes difficult to obtain a uniform film, and the leak current may increase. On the other hand, when the film thickness of the capacitor insulating layer 6 exceeds 500 nm, the voltage required for polarization reversal becomes high and the drive voltage may be insufficient. Therefore, the thickness of the capacitor insulating film is preferably 50 to 500 nm.

In the above-mentioned forming method, the buffer layer 5 is formed to have a film thickness of 0.5 nm, but the film thickness of the buffer layer 5 is not limited to this, and it is preferably 0.5 to 30 nm. . Preferably, the film thickness is 2 to 20n
m.

The annealing temperature is not limited to 600 ° C., but is preferably 550 to 650 ° C.

Next, another embodiment will be described. this
The other embodiment is the same as the above embodiment except that the second conductive film 3 and the upper conductive portion 7 formed on the Ti film of the first conductive film 3 are IrO ₂ and Ir. And
The description is omitted.

In this embodiment, the film thickness of IrO ₂ is 10
To 200 nm, preferably 20 to 100
It is preferably nm. Further, the film thickness of Ir is preferably 50 to 300 nm, and 100 to 250
It is preferably nm.

Further, as the upper conductive film of this embodiment, I
It may be r and Ir with IrO ₂ formed thereon.

In any of the embodiments, the buffer layer 5
Is provided below the capacitor insulating layer 6, but the present invention is not limited to this, and the buffer layer 5 may be provided above the capacitor insulating layer 6, and further,
The buffer layer 5 may be provided above and below the capacitor insulating layer 6.

[0044]

EXAMPLE An example of the present invention will be described below with reference to FIG.
3A to 3D and the ferroelectric substance having the structure of the embodiment shown in FIG.
The results of comparing the characteristics of the ferroelectrics of the comparative examples shown in (a) to (d) will be described.

In FIG. 1A, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a T conductive film having a film thickness of 15 nm is formed as a first conductive film 3 thereon.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. PbZr having a film thickness of 200 nm is formed on the second conductive film 4.
A capacitor insulating layer 6a having a composition in which 1% of Li is added to _0.52 Ti _0.48 is formed, PbTiLi _0.005 O ₃ having a film thickness of 5 nm is formed thereon as a buffer layer 5a, and an upper conductive film 7 is formed on the buffer layer 5a. As a result, a Pt film having a film thickness of 200 nm was formed.

In FIG. 1B, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a T conductive film having a film thickness of 15 nm is formed as a first conductive film 3 thereon.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. A 5 nm thick PbTiLi _0.005 O ₃ film is formed on the second conductive film 4 as a buffer layer 5 a, and a 200 nm thick PbZr _0.52 Ti _0.48 L film is formed on the buffer layer 5 a.
A capacitor insulating layer 6a having a composition containing 1% of i was formed, and a Pt film having a film thickness of 200 nm was formed as an upper conductive film 7 on the capacitor insulating layer 6a.

In FIG. 1C, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a T conductive film having a film thickness of 15 nm is formed as a first conductive film 3 thereon.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. A 5 nm thick PbTiLi _0.005 O ₃ film is formed on the second conductive film 4 as a buffer layer 5 a, and a 200 nm thick PbZr _0.52 Ti _0.48 L film is formed on the buffer layer 5 a.
A capacitor insulating layer 6a having a composition in which i is added by 1% is formed, and Pb having a film thickness of 5 nm is formed thereon as a buffer layer 5a.
TiLi _0.005 O ₃ was formed, and a Pt film having a film thickness of 200 nm was formed as the upper conductive film 7 on the buffer layer 5a.

In FIG. 1D, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a first conductive film 3 having a film thickness of 15 nm is formed on the SiO ₂ film.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. A PbTiO ₃ film having a thickness of 5 nm is formed as a buffer layer 5 a on the second conductive film 4, and PbZr _0.52 Ti _0.48 having a film thickness of 200 nm is formed on the buffer layer 5 b with 1% of Li.
A capacitor insulating layer 6a having the added composition was formed, a buffer layer 5a was formed of PbTiO ₃ having a film thickness of 5 nm, and a Pt film having a film thickness of 200 nm was formed as an upper conductive film 7 on the buffer layer 5b. .

In FIG. 3A, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a first conductive film 3 having a film thickness of 15 nm is formed on the SiO ₂ film.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. PbZr having a film thickness of 200 nm is formed on the second conductive film 4.
A capacitor insulating layer 6a having a composition obtained by adding 1% of Li to _0.52 Ti _0.48 is formed, and an upper conductive film 7 having a film thickness of 2 is formed thereon.
A Pt film of 00 nm was formed.

In FIG. 3B, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on a silicon substrate 1, and a T conductive film having a film thickness of 15 nm is formed on the SiO ₂ film as a first conductive film 3.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. PbZr having a film thickness of 200 nm is formed on the second conductive film 4.
A capacitor insulating layer 6b of _0.52 Ti _0.48 is formed, and a film thickness of 200 n is formed as an upper conductive film 7 on the capacitor insulating layer 6b.
m Pt film was formed.

In FIG. 3C, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on the silicon substrate 1, and a T conductive film having a film thickness of 15 nm is formed as a first conductive film 3 thereon.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. A 5 nm thick PbTiLi _0.005 O ₃ film is formed on the second conductive film 4 as a buffer layer 5 a, and a 200 nm thick PbZr _0.52 Ti _0.48 capacitor insulating layer 6 b is formed on the buffer layer 5 a. The buffer layer 5a
To form PbTiLi _0.005 O ₃ with a thickness of 5 nm,
A film thickness of 200 n is formed as the upper conductive film 7 on the buffer layer 5a.
m Pt film was formed.

In FIG. 3D, a SiO ₂ film having a film thickness of 500 nm is formed as an interlayer insulating film 2 on the silicon substrate 1, and a first conductive film 3 having a film thickness of 15 nm is formed on the SiO ₂ film as a T ₂ film.
A Pt film having a film thickness of 200 nm is formed as the i film and the second conductive film 4. A PbTiO ₃ film having a film thickness of 5 nm is formed on the second conductive film 4 as a buffer layer 5 b, and a capacitor insulating layer 6 b having a PbZr _0.52 Ti _0.48 composition film having a film thickness of 200 nm is formed on the buffer layer 5 b. As the buffer layer 5b, PbTiO ₃ having a film thickness of 5 nm is formed, and the buffer layer 5
A Pt film having a film thickness of 200 nm was formed as an upper conductive film 7 on b.

[0053]First embodiment Examples (a) to (d) and Comparative Examples (a) to
(D) is an infrared image furnace (R
Example 1 obtained by annealing in TA) for 1 minute
To the residual polarization value Pr of Example 4 and Comparative Examples 13 to 16,
Leakage current and fatigue resistance were measured. Of remanent polarization value Pr
In the measurement, a voltage of ± 5V was applied. Leakage current
In the measurement of, leakage when applying a voltage of 5V
The current was measured. ± 5V when measuring fatigue resistance
When the voltage of is applied at a frequency of 25 kHz, the initial value P
r₀Remanent polarization value Pr for is the initial value Pr₀Half of
The number of cycles C was measured. The results are shown in Table 1.
You

[0054]

[Table 1]

It is only in Examples 1 to 4 in which the buffer layer has a good result that the remanent polarization value Pr, the leak current, and the fatigue resistance are good.

[0056]Second embodiment Examples (a) to (d) and Comparative Examples (a) to
(D) is an infrared image furnace (R
Example 5 to Example which was annealed in TA) for 1 minute
The remanent polarization value Pr and leakage current of Example 8 and Comparative Examples 17 to 20
Flow and fatigue resistance were measured in the same manner as in the first embodiment. That conclusion
The results are shown in Table 2.

[0057]

[Table 2]

It is only in Examples 5 to 8 in which the buffer layer has a good result that the residual polarization value Pr, the leak current and the fatigue resistance are good.

[0059]Third embodiment Examples (a) to (d) and Comparative Examples (a) to
(D) is an infrared image furnace (R
Example 9 to Example which was annealed in TA) for 1 minute
Remanent polarization value Pr and leak of Example 12 and Comparative Examples 21 to 24
The current and fatigue resistance were measured in the same manner as in the first embodiment. That
The results are shown in Table 3.

[0060]

[Table 3]

Good results were obtained for the remanent polarization value Pr, the leakage current, and the fatigue resistance characteristics only in Examples 9 to 12 in which the buffer layer was provided.

[0062]

As described in detail above, according to the present invention,
Li vertically on one of the capacitor insulating layer made of PZT ferroelectric material having a composition obtained by adding, L the PTO
Since the buffer layer having the composition to which i is added is provided, the leak current can be reduced and the fatigue resistance can be improved. Moreover, since the annealing temperature can be lowered by adding Li, the influence on other members is reduced.

[Brief description of drawings]

1A to 1D are cross-sectional views of a ferroelectric memory according to an embodiment.

2A to 2D are cross-sectional views showing a method of manufacturing a ferroelectric memory according to an embodiment of the present invention in the order of steps.

3A to 3D are cross-sectional views of a ferroelectric memory of a comparative example.

[Explanation of symbols]

1; Silicon substrate, 2; Interlayer insulating layer, 3; First conductive film, 4; Second conductive film, 5, 5a, 5b; Buffer layer, 6, 6a, 6b; Capacitor insulating layer, 7; Upper conductive film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 H01L 29/78 371 27/10 451 29/788 29/792 (56) Reference JP-A-9-139474 (JP , A) JP-A-8-186235 (JP, A) JP-A-10-173143 (JP, A) JP-A-54-25909 (JP, A) JP-A-2000-7430 (JP, A) JP-B-40 -24062 (JP, B1) (58) Fields surveyed (Int.Cl. ⁷ , DB name) C01G 21/00-23/08 H01B 3/00 H01B 3/12 H01L 21/822 H01L 27/04

Claims (11)

(57) [Claims] 1. Pb (Zr, Ti) O ₃ with addition of Li
And a capacitor insulating layer made of Pb (Zr, T
i) a buffer layer composed of a PbTiO ₃ layer laminated on at least one of the upper surface and the lower surface of the O ₃ layer, wherein the PbTiO ₃ layer is one to which Li is added, and the buffer layer and the Ferroelectric memory characterized in that the capacitor insulating layer is crystallized. 2. The capacitor insulating layer is made of Pb _x Zr.
_(1-y) Ti _y has a composition in which Li is added, and the value of x is 0.
The ferroelectric memory according to claim 1, wherein the values of 9 to 1.2 and y are 0.3 to 0.7. 3. The content of Li is Pb _x Zr _(1-y) Ti
_The ferroelectric memory according to claim 2, wherein the content of _y is 0.2 to 20 mol%. 4. The buffer layer comprises Pb _α TiO ₃ and L
The ferroelectric memory according to claim 1, wherein the ferroelectric memory has a composition to which i is added, and the value of α is 0.8 to 1.2. 5. The ferroelectric memory according to claim 4, wherein the content of Li is 20 mol% or less with respect to the content of Pb _α TiO ₃ . 6. The ferroelectric memory according to claim 1, wherein the capacitor insulating layer has a film thickness of 50 to 500 nm. 7. The buffer layer has a thickness of 0.5 to 30.
7. The ferroelectric memory according to claim 1, wherein the ferroelectric memory has a thickness of nm. 8. A step of forming an interlayer insulating film on a substrate,
A step of forming the first and second conductive films, and adding Li
And a step of preparing a sol-gel solution for a capacitor insulating layer composed of a Pb (Zr, Ti) O ₃ layer, and Pb added with Li
A step of preparing a sol-gel solution for a buffer layer composed of a TiO ₃ layer, a step of spin-coating the sol-gel solution for the buffer layer and then pre-baking, and a spin-coating of the sol-gel solution for the capacitor insulating layer, followed by pre-baking and A method of manufacturing a ferroelectric memory, comprising a step of forming a crystallized buffer layer and a capacitor insulating layer by annealing, and a step of forming an upper electrode. 9. The step of preparing a sol-gel solution for the capacitor insulating layer comprises dissolving lead diacetate trihydrate in a solvent,
It is a step of dehydrating by heating and stirring at 24 ° C., lowering the temperature, and then adding tetraisopropoxyzirconium, tetraisoproxitane and lithium ethoxide to the reaction system, heating and stirring at 124 ° C., and adding a solvent. Item 9. A method of manufacturing a ferroelectric memory according to item 8. 10. The step of preparing the sol-gel solution for the buffer layer comprises dissolving lead diacetate trihydrate in a solvent,
After dehydration by heating with stirring at ℃, and after cooling the temperature, tetraisoproxitan and lithium ethoxide were added to the reaction system.
The method for manufacturing a ferroelectric memory according to claim 8 or 9, which is a step of heating and stirring at 24 ° C and adding a solvent. 11. The annealing is performed at a temperature of 550 to 6
11. The method of manufacturing a ferroelectric memory according to claim 8, wherein the heating is an oven heating at 50 ° C. or an RTA annealing.