JP3495468B2 - Matching circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matching circuit, and more particularly to a matching circuit capable of preventing a decrease in gain due to a phase shift when synthesizing a plurality of chips of semiconductor elements such as transistors in parallel.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram in which three transistors 1, 2 and 3 are combined in parallel. In FIG. 7, 4, 5
Reference numerals 6 and 6 are wirings drawn from the transistors 1, 2 and 3, respectively. Now, as shown in the figure, the three transistors 1, 2 and 3 are arranged linearly and are combined in parallel. More specifically, the branch circuit 4, which is branched from the input end 50a of the microstrip line 50 to the wirings 4, 5 and 6 through the impedance matching taper circuit,
5 and 6 are formed, and the tips of the branch circuits 4, 5 and 6 are connected to the input terminals (not shown) of the above-mentioned three transistors 1, 2 and 3 which are linearly arranged. ing. Further, branch circuits 4, 5 and 6 of the same shape are formed so that the output side to which the output terminals (not shown) of the three transistors 1, 2 and 3 are connected is completely symmetrical to the input side. The tips are collected and connected to the output end 50b of the microstrip line 50. At this time, the wirings 4 and 6 connected to the transistors 1 and 3 arranged above and below are connected to the microstrip line 50.
Is configured to be line-symmetric with respect to the line connecting the input end 50a and the output end 50b.

[0003]

However, as described above, when the three transistors 1, 2 and 3 are combined in parallel so that the wirings 4 and 6 drawn from the vertically arranged transistors 1 and 3 are symmetrical, The wirings 4 and 6 are
It is longer than the wiring 5 drawn out from the transistor 2 arranged in the center. Since there is a phase difference due to the difference in the wiring length between the input and the output, there is a problem that the synthesis efficiency is lowered and the gain is lowered.

The present invention has been made in order to solve such a problem, makes it possible to change and adjust the effective length of the wiring on the substrate, and further lowers the gain due to the phase shift when synthesizing the transistors in parallel. The purpose is to obtain a matching circuit that can prevent

[0005]

The present invention is provided on a substrate.
Mounted on the substrate and a plurality of chipped semiconductor chips
To combine the above-mentioned semiconductor chips in parallel
Multiple line lengths with different line lengths
And the shortest of the above wirings or
Touch the above wiring except one of the longest ones
A dielectric constant that is provided and differs from the dielectric constant of the above substrate.
Phase adjustment to eliminate the phase difference between the above wiring
Means, the phase adjusting means is provided with the plurality of wirings.
Between the wiring except the longest one and the board
Is provided and has a dielectric constant less than that of the substrate
It is made up of layers, where the layers partially cover the wiring.
From the air layer provided by making it an arbridge
It is a matching circuit characterized by being configured.

[0006]

[0007]

[0008]

[0009]

[0010]

In addition, a plurality of semiconductor chips provided on the substrate, a branch circuit provided on the substrate and having a combining point for combining the plurality of semiconductor chips in parallel, and between the semiconductor chip and the branch circuit. A plurality of wirings connected to the semiconductor chip and a wire connecting the plurality of wirings to the branch circuit, and the plurality of wirings are provided apart from the synthesis point. Those connected to the semiconductor chip that are connected are short, those connected to the semiconductor chip that are provided near the synthesis point are long, and those that are shortened as the distance from the semiconductor chip to the synthesis point is long. Has been.

Also, a plurality of semiconductor chips, a three-dimensional substrate formed in three dimensions, and a branch circuit provided on the three-dimensional substrate and connected to the plurality of semiconductor chips to synthesize the plurality of semiconductor chips in parallel are provided. And a plurality of wirings that are configured so that the lengths of the wirings between the combining point of the branch circuit and the plurality of semiconductor chips are equal to each other.

[0013]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. FIG. 1 is a top view showing a matching circuit according to an embodiment of the present invention, which is a top view of a chip in which output combining of three transistors combined in parallel is realized on a semiconductor substrate. is there. FIG. 2 is a partially enlarged view of the vicinity of the wiring in the matching circuit of FIG.
Since the circuit diagram is almost the same as that in FIG. 7,
Here, it is omitted and reference is made to FIG. 7. In FIGS. 1 and 2, 7 is a semiconductor substrate made of a substrate material such as GaAs, 1, 2 and 3 are transistors provided on the substrate 7, and 4, 5 and 6 are transistors, respectively. The wirings are drawn from 1, 2 and 3. Here, in the three transistors 1, 2 and 3, as in the conventional example, the wirings 4 and 6 drawn from the transistors 1 and 3 are the input ends 5 of the microstrip line 50.
0a and the output terminal 50b are connected in parallel so as to be symmetric with respect to the line connecting them, and the wirings 4 and 6 are longer than the wiring 5 drawn from the transistor 2 provided in the center.

In order to eliminate the phase difference caused by this, in the present embodiment, as shown in FIG. 2, as the phase adjusting means for eliminating the phase difference between the wirings, that is, the effective length of the wirings is changed and adjusted. As the effective length change adjusting means, the wiring 4 drawn from the transistors 1 and 3 is used.
The wirings 4 and 6 are brought into contact with a part or the whole of the wirings 6 and 6 to provide a dielectric film 8 having a larger dielectric constant than the substrate material forming the substrate 7. As a method of installing the dielectric film 8, as shown in FIG. 2, it may be embedded like a part of the substrate 7, or it may be provided on the surface of the flat substrate 7 and the wirings 4 and 6 may be formed thereon. May be provided.
The dielectric film 8 is formed of, for example, PbZrTi (dielectric constant of about 4).
50) or BaTiO ₃ (dielectric constant of about 38).

Here, the effective length λ of the wirings 4, 5 and 6 is
The physical length (the length as it is) of the wirings 4, 5 and 6 is λ ₀ ,
When the permittivity is ε _r , it is expressed by λ = λ ₀ / (ε _r ) ^1/2 (1). The larger the permittivity ε _r , the greater the wavelength shortening rate (ε _r ) ^1/2. Therefore, it is known that the effective length λ is shortened. Therefore, from this fact, the dielectric constant ε _r for the long wirings 4 and 6 having the physical length λ ₀
It is possible to make the effective length λ equal to the effective length of the wiring 5 having the shortest physical length by laying down those having a larger size than the substrate.

As described above, in this embodiment, the dielectric film 8 having a larger dielectric constant than the substrate material is provided below the wirings 4 and 6, and the range where the dielectric film 8 is provided is the wirings 4 and 6. The effective lengths of the wirings 4 and 6 drawn from the transistors 1 and 3 are selected from the transistor 2 by using the above formula (1) based on the difference in length with the dielectric film 8 and the dielectric constant of the dielectric film 8. Since it can be made equal to the effective length of the drawn out shortest wiring 5, the occurrence of the phase shift between the wirings 4, 5 and 6 is eliminated, and the gain is reduced due to the phase shift when the transistors are combined in parallel. Can be prevented.

Embodiment 2. In the above-described first embodiment, an example in which the dielectric film 8 having a larger dielectric constant than the substrate material forming the substrate 7 is provided below the longer wirings 4 and 6 has been described. In the embodiment, as the phase adjusting means, that is, the effective length change adjusting means, the insulating film 48 (having a dielectric constant smaller than that of the substrate material of the substrate 7 is formed under a part or the whole of the wiring 5 having a shorter length. (See Figure 2)
Was set up. The installation method may be the same as that of the dielectric film 8 shown in FIG. Further, as the material of the insulating film 48, for example, SiON (dielectric constant 5) or the like is suitable. In this embodiment, as described above, the insulating film 48 having a small dielectric constant is provided below the wiring 5 having a shorter length. Since the effective length of the drawn wiring 5 can be made equal to the effective length of the wirings 4 and 6 drawn from the transistors 1 and 3, the respective wirings 4, 5 and 6 are similar to the first embodiment. It is possible to prevent the occurrence of a phase shift between them and prevent a decrease in gain due to a phase shift when the transistors are combined in parallel.

Embodiment 3. In the present embodiment,
As shown in FIG. 3, as the phase adjusting means, that is, the effective length change adjusting means, air 10 is put under a part of the wiring 5 having a shorter length to form a part of the wiring 5 into an air bridge. I did it. As a result, a layer having a very small dielectric constant due to the air 10 is formed in a portion below the wiring 5, and thus the transistor 2 is formed in the same manner as in the second embodiment.
Since the effective length of the shorter wiring 5 drawn from the transistor can be made equal to the effective length of the wirings 4 and 6 drawn from the transistors 1 and 3, the above-described first embodiment
Similarly, it is possible to eliminate the occurrence of the phase shift between the wirings 4, 5 and 6 and prevent the decrease in the gain due to the phase shift when the transistors are combined in parallel.

Embodiment 4. In the first, second and third embodiments described above, the example in which GaAs is used as the substrate material of the substrate 7 has been described, but the present invention is not limited to this case, and Si, InP or the like may be used. Further, as shown in FIG. 4 to be described later, other constituent elements except the transistor of the matching circuit are provided on an external substrate 11 instead of on the same substrate as the substrate 7 on which the transistor (13, see FIG. 4) is formed. It may be provided. Also in those cases,
It is possible to obtain the same effect as that of the first to third embodiments. Further, in the above-described first, second and third embodiments, the case where three transistors are combined in parallel has been described as an example. Can also be applied to.

Embodiment 5. In the present embodiment,
As shown in FIG. 4, external MIC (monolithic integrated circuit) substrates 11 are provided on both sides of the substrate 7 on which a plurality of transistors 13 are formed, and other components of the matching circuit other than the transistors 13 are provided. Are provided on the MIC substrate 11. In addition, the wiring 12 on the MIC substrate 11
As shown in FIG. 4, the one provided at both ends is the shortest, and the one provided at the center is the longest, and is formed so as to gradually become longer as it approaches the center. In FIG. 4, 16A and 16B are wirings forming a branch circuit for synthesizing a plurality of transistors 13 in parallel, and 14 and 15 are synthesizing points at which the wirings 16A and 16B are synthesizing. Is wiring 12 and 16
It is a wire connecting between A. The wire 35 is also connected between the transistor 13 and the wiring 12. In this embodiment, that is, each wiring 12 is short to be connected to the transistor 13 provided apart from the combining points 14 and 15, and is provided near the combining points 14 and 15. Transistor 1
Transistor 1 so that the one connected to 3 becomes longer
It is provided so that it becomes shorter as the distance from 3 to the combining points 14 and 15 becomes longer.

Here, the wire 35 can be regarded as having almost zero resistance in consideration of only the inductance, and its effective length is considerably smaller than that of a wire having the same length. Therefore, in FIG. 4, the wiring 1 connected to the transistors 13 provided at both ends
By reducing the line length of 2, the wiring 16A and 16
Composite point 1 even though tracks are gathered in the middle in B
It can be corrected that the line lengths up to 4 and 15 are longer at both end portions than at the central portion, and the entire line length (effective length) can be made the same.

In this embodiment, as described above, the wiring 12 is short to be connected to the transistor 13 provided apart from the combining points 14 and 15.
Since the one connected to the transistor 13 provided near the combining points 14 and 15 is made longer, the connection is made shorter as the distance from the transistor 13 to the combining points 14 and 15 becomes longer. Wirings 12, 16A and 16 drawn from each transistor 13
Since the line lengths of B can be made equal, that is, the distances (effective lengths) from the respective transistors 13 to the combining points 14 and 15 of the wirings 12, 16A and 16B can be made equal, the above-mentioned first embodiment can be made. As in the case of 4 to 4, it is possible to eliminate the occurrence of a phase shift between the wirings 12 with respect to the respective transistors 13, and it is possible to prevent a decrease in gain due to a phase shift when the transistors 13 are combined in parallel. This embodiment can also be applied to the case where one transistor 13 is composed of a plurality of cells (or bonding pads), and in that case, it is provided at both ends of the transistor 13. The same effect can be obtained if the wiring 12 connected to the cell is short and the wiring 12 connected to the cell provided in the central portion of the transistor 13 is long.

Sixth Embodiment FIG. 5 is a side view of a matching circuit according to another embodiment of the present invention as viewed from the transistor side, and FIG. 6 is a top view of the matching circuit shown in FIG. In the figure, 17 is a three-dimensionally formed substantially quadrangular pyramid-shaped three-dimensional MIC substrate, 18, 19, 20, 21, 22,
23 and 24 are transistors, 26, 27, 28, 2
Reference numerals 9, 30, 31, and 32 are wirings provided on the surface of the three-dimensional MIC substrate 17 and connected to the respective transistors 18 to 24, and 25 is a combining point where the wirings 18 to 24 are combined.

As described above, in this embodiment, the transistors 18 to 24 are output-combined at the combining point 25 by the wirings 26 to 32. At this time, the solid M
By using the IC board 17, the wirings 26 to 32 are
Since it can be wired three-dimensionally, each transistor 1
The line lengths of the wirings 26 to 32 drawn from 8 to 24 can be the same. That is, each transistor 18
24 to 24, since the transistor 21 provided at the center of them is closest to the composite point 25 in the horizontal direction, the wiring 29 drawn from it is formed so as to pass through the highest point in the vertical direction of the three-dimensional MIC substrate 17. On the contrary, the transistor 1 farthest from the synthesis point 25 in the horizontal direction is
For 8 and 24, the wiring 2 drawn from them
6 and 32 are formed so as to pass through a position lower than any of the other wirings 27 to 31.

As described above, in this embodiment, by using the three-dimensional MIC substrate 17, the lengths of the wirings 26 to 32 drawn out from the transistors 18 to 24 can be made uniform, so that the wirings can be made uniform. The effective lengths of 26 to 32 can be the same, and the above-described first to third embodiments can be used.
As in the case of No. 5, it is possible to eliminate the occurrence of the phase shift between the wirings 26 to 32 and prevent the decrease in the gain due to the phase shift when the transistors 18 to 24 are combined in parallel. In addition,
In this embodiment, the example in which the three-dimensional MIC substrate 17 is formed in the shape of a quadrangular pyramid has been described, but not limited to this case, the wirings 26 to 32 are provided so that the lengths (effective lengths) are equal. If so, a polyhedron such as a triangular pyramid, a cone, or a hemisphere may be used, and any shape may be used.

Since the present invention is configured as described above, it is possible to obtain the effects described below.

Since the effective length change adjusting means having a dielectric constant different from that of the substrate is provided in contact with the wiring provided on the substrate, the effective length of the wiring is changed and adjusted. When there are a plurality of wirings, the effective length of each wiring can be made equal, and when these wirings are combined and connected, the phase difference caused by the difference in length between the wirings can be eliminated, It is possible to prevent a decrease in gain due to a phase shift.

With respect to a plurality of wirings having different line lengths and forming a branch circuit for synthesizing a plurality of semiconductor chips in parallel on a substrate, one of the shortest and the longest of them is selected. Since the phase adjustment means having a dielectric constant different from that of the substrate, which is provided except for the above, is provided, the effective length of each wiring can be made equal, and the phase difference caused by the difference in the length between the wirings can be made. Since it can be eliminated, it is possible to prevent a decrease in gain due to a phase shift.

Further, the phase adjusting means is provided between the wiring except the shortest one of the plurality of wirings and the substrate, and is composed of a dielectric film having a dielectric constant higher than that of the substrate. Since the effective lengths of the respective wirings can be made equal to each other and the phase difference caused by the difference in the length between the wirings can be eliminated, it is possible to prevent the gain from decreasing due to the phase shift.

Further, the phase adjusting means is provided between the wiring except the shortest one of the plurality of wirings and the substrate, and has a dielectric constant smaller than that of the substrate (insulating film or air layer). The effective length of each wiring can be made equal, and the phase difference caused by the difference in the length between the wirings can be eliminated, so that the decrease in gain due to the phase shift can be prevented. There is an effect that can be.

Further, it is short to connect a plurality of wirings forming a branch circuit for synthesizing a plurality of semiconductor chips in parallel to a semiconductor chip provided apart from the synthesis point of the branch route. , The one connected to the semiconductor chip provided near the synthesis point of the branch circuit is made longer, and the distance is shortened as the distance from the semiconductor chip to the synthesis point becomes longer. Since the line lengths of the wirings drawn from the chips can be made equal, that is, the distances from the respective semiconductor chips to the composite points of the branch circuits can be made equal, the occurrence of the phase shift between the wirings for the respective semiconductor chips can be prevented. This can be eliminated, and a decrease in gain due to a phase shift when semiconductor chips are combined in parallel can be prevented.

Further, since a three-dimensional three-dimensional substrate is used as a substrate for forming a plurality of wirings forming a branch circuit for synthesizing a plurality of semiconductor chips in parallel, a combination point of the branch circuits is obtained. It can be provided so that the length of each wiring between a plurality of semiconductor chips is uniform to each other,
It is possible to eliminate the occurrence of the phase shift between the wirings and prevent the decrease in the gain due to the phase shift when the semiconductor chips are combined in parallel.

[Brief description of drawings]

FIG. 1 is a top view showing a matching circuit according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged view of the vicinity of wiring in the matching circuit of FIG.

FIG. 3 is a partially enlarged view of the vicinity of wiring in a matching circuit according to a third embodiment of the present invention.

FIG. 4 is a top view showing a matching circuit according to a fifth embodiment of the present invention.

FIG. 5 is a side view showing a matching circuit according to a sixth embodiment of the present invention.

FIG. 6 is a top view showing a matching circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional matching circuit.

[Explanation of symbols]

1,2,3,18,19,20,21,22,23,2
4 transistors, 4, 5, 6, 26, 27, 28, 2
9, 30, 31, 32 wiring, 7 substrate, 8 dielectric film, 9
Air bridge, 10 air, 17 three-dimensional MIC substrate, 48 insulating film.

Continuation of the front page (56) Reference JP-A-7-30401 (JP, A) JP-A-4-365201 (JP, A) JP-A-8-46459 (JP, A) JP-A-5-243804 (JP , A) JP-A-3-66205 (JP, A) JP-A-2-128501 (JP, A) JP-A-63-281502 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) H01P 5/12 H01P 3/08 H01P 5/02 603 H03F 3/60 H03F 3/68

Claims (3)

(57) [Claims] 1. A plurality of semiconductor chips provided on a substrate
And a plurality of semiconductor chips arranged side by side on the substrate.
A branch circuit having a synthesis point for column synthesis is constructed.
A plurality of wires with different line lengths and the shortest or the longest of the above wires
It is provided in contact with the above wiring except one of
Along with having a dielectric constant different from that of the substrate,
Phase adjusting means for eliminating a phase difference between the wirings , the phase adjusting means being arranged above the wirings excluding the longest one of the plurality of wirings.
It is provided between the substrate and the dielectric constant of the substrate
It is composed of a layer having a dielectric constant, and the layer is an air bridge part of the wiring.
A matching circuit characterized by being composed of an air layer provided by . 2. A plurality of semiconductor chips provided on a substrate
And a plurality of semiconductor chips arranged side by side on the substrate.
A branch circuit having a combination point for column combination, and provided between the semiconductor chip and the branch circuit,
A plurality of wires connected to the semiconductor chip and a wire connecting the plurality of wires and the branch circuit
When provided with a plurality of wirings are provided apart with respect to the combining point
What is connected to the semiconductor chip is short,
Connect to the above semiconductor chip provided near the synthesis point
The above-mentioned semiconductor chip should be
As the distance to the composite point becomes longer, it becomes shorter
A matching circuit characterized by being provided. 3. A plurality of semiconductor chips, a three-dimensional three-dimensional substrate, and a plurality of semiconductors provided on the three-dimensional substrate.
Connected to a chip to combine the above semiconductor chips in parallel.
A plurality of wires constituting the branches circuit for forming comprises, between the combining point and the plurality of semiconductor chips of the branch circuit
The length of each of the above wirings should be uniform
Matching circuit characterized by having.