JP3494563B2 - Power amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier circuit having a plurality of cascaded amplifiers and amplifying an input signal in a plurality of stages.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional power amplifier circuit. This power amplifier circuit includes, for example, a field effect transistor (hereinafter referred to as FET) 11 which is an initial stage amplifier, and an FET 12 which is a final stage amplifier connected to the output side of the FET 11. The gate of the FET 11 is connected to the terminals T1 and T2, and the terminal T1
The input signal Si is input via 1 and the terminal T
The gate voltage Vg as a power supply voltage is input via the input terminal 2. The drain of the FET 11 is the terminal T
3 is connected to the power supply voltage Vdd, and the source of the FET 11 is connected to the gate of the FET 12. FET
The gate of 12 is further connected to the terminal T4,
The gate voltage Vg is supplied through the gate line 4. The drain of the FET 12 is connected to the power supply voltage Vdd via the terminal T5, and the source of the FET 12 is connected to the output terminal T6. The gate voltage Vg is a voltage generated from the power supply voltage Vdd by a resistor (not shown), for example. In such a power amplifier circuit, the input signal Si is biased by the gate voltage Vg and
1 is given to the gate. FET11 is the power supply voltage Vd
Amplification based on d is performed and a voltage signal S11 is output. F
The gate voltage Vg from the terminal T4 is applied to the gate of ET12.
The voltage signal S11 biased by
12 performs amplification based on the power supply voltage Vdd. FET1
The amplified signal So generated by the amplification of 2 is the FET
It is output via the 12 sources and the output terminal T6.

[0003]

However, the conventional power amplifier circuit has the following problems. FE
Since the amplified signal So as a result of being amplified at T11 and 12 is output as it is through the output terminal T6,
If the characteristics of 11 and 12 vary, the amplified signal So output from the output terminal T6 varies from product to product. Therefore, in order to suppress variations among products, it is necessary to strictly manage lots of the FETs 11 and 12 used in the power amplifier circuit, and at the same time, multipliers such as capacitors and resistors of other circuit parts mounted in the power amplifier circuit are required. Had to be set for each manufacturing lot. In addition, the amplified signal So
However, there is also a problem that the power supply voltage Vdd, the gate voltage Vg generated from the power supply voltage Vdd, the level of the input signal Si, the load, and the like do not reach a desired level, but change.

[0004]

In order to solve the above problems, a first invention of the present invention is directed to a plurality of stages which are respectively connected to power supply terminals and are cascade-connected to input terminals for inputting input signals. In the power amplifier circuit that includes the amplifier of FIG. 1 and amplifies the input signal to a desired level and outputs the amplified signal by the amplification operation of each amplifier using the power supply voltage given from the power supply terminal, Correction means are provided. The correction means is connected to the output side of the amplifier at the final stage, generates a correction signal by superimposing a voltage corresponding to the power supply voltage on the amplified signal given from the amplifier at the final stage, and outputs the correction signal. a means for outputting instead of the amplified signal. According to a second aspect of the invention, the power amplifier circuit is provided with the following correcting means and selecting means. The correction unit is a unit that is connected to the output side of the final stage amplifier and that generates a correction signal by superimposing a voltage corresponding to the power supply voltage on the amplified signal provided from the final stage amplifier. The selecting means compares the amplified signal with the correction signal, selects and outputs the correction signal when the amplified signal is not at a desired level, and the amplified signal has a desired level. If so, it is means for selecting and outputting the amplified signal.

A third invention is the power amplifier circuit of the first and second inventions, which is connected between the power supply terminal and each of the amplifiers and absorbs the fluctuation of the power supply voltage to stabilize the power supply voltage. A power supply voltage stabilizing circuit for supplying each of the amplifiers is provided. The invention of the younger brother 4 is the power amplifier circuit according to the third invention , wherein the power supply voltage stabilizing circuit provides the stabilized power supply voltage to the correcting means. According to the present invention , since the power amplifier circuit is configured as described above, the input signal is amplified by the plurality of cascaded amplifiers connected in series, and the amplified signal is obtained from the final amplifier. Here, even if the level of the amplified signal has not reached the desired level, the correction signal corrects the amplified signal .

[0006]

1 is a block diagram of a power amplifier circuit showing an embodiment of the present invention. The power amplifier circuit 20 includes FETs 21 and 22 that are two-stage amplifiers that are cascade-connected to the input terminal T11. The gate of the FET 21 is connected to the input terminal 11, and the output terminal of the FET 22 is connected to the output terminal T12 of the power amplifier circuit 20 via the output signal level stabilizing circuit 23. Further, the power amplifier circuit 20 has two power supply terminals T1.
Four power supply voltage stabilizing circuits 2 commonly connected to 3 and 14
4, 25, 26, 27 are provided. Each power terminal T13,14 is a terminal for introducing a supply voltage V _1, V ₂ respectively. The output terminal of the power supply voltage stabilizing circuit 24 is F
It is connected to the gate of ET21 and the output terminal of the power supply voltage stabilizing circuit 25 is connected to the drain of FET21.
The output terminal of the power supply voltage stabilizing circuit 26 is connected to the gate of the FET 22, and the output terminal of the power supply voltage stabilizing circuit 27 is F
It is connected to the drain of the ET 22 and to the output signal level stabilizing circuit 23.

FIG. 3 is a circuit diagram showing an example of the output signal level stabilizing circuit in FIG. The output signal level stabilizing circuit 23 includes a resistor 23a, which is a correcting unit that superimposes the power supply voltage V ₂₇ output from the power supply voltage stabilizing circuit 27 on the amplified signal S22 output from the FET 22 to generate a correction signal S22a, and an amplifier. The signal S22 and the correction signal S22 are compared, and when the amplified signal S22 is not at the desired level, the correction signal S22a is selected and output, and when the correction signal S22 is at the desired level, the signal is output. Amplified signal S22a
An OR circuit 23b which is a selection means for selecting and outputting
And a variable resistor 23c for setting the level of the output signal S23b of the OR circuit 23b. Note that the configuration of the output signal level stabilizing circuit 23 is O as shown in FIG. 3 when, for example, only when the level of the amplified signal S22 is low.
The resistor 23a and the resistor 23c may be provided without providing the R circuit 23c. Further, the resistor 23c may be omitted and the resistor 23a may be configured by a variable resistor instead of the resistor 23c.
It is also possible to configure the OR circuit 23b with a wired OR. FIG. 4 is a circuit diagram showing an example of the power supply voltage stabilizing circuit in FIG. Each of the power supply voltage stabilizing circuits 24 to 27 has the same configuration and includes a FET 30 having a drain connected to the power supply terminal T13, and a resistor 31 having one end connected to the power supply terminal T13. The other end of the resistor 31 is connected to the source of the FET 30 via the resistor 32. A connection point between the resistor 31 and the resistor 32 serves as an output terminal of each power supply voltage stabilizing circuit 24-27. A resistor 33 is connected between the gate of the FET 30 and the power supply terminal T14, and a resistor 3 is connected between the gate and the source of the FET 30.
4 is connected. The source of the FET 30 is connected to the ground GND of the power amplifier circuit 20.

Next, the operation of the power amplifier circuit 20 of FIG. 1 will be described. In the power supply voltage stabilizing circuits 24 to 27, the power supply voltage V ₁ given from the power supply terminal T13 is the FET 30.
Of the resistor 31 and one end of the resistor 31. Resistance 3
3, 34 are the power supply voltage V applied from the power supply terminal T14
₂ is divided and applied to the gate of the FET 30. here,
Since the source of the FET 30 is connected to the ground GND, when the power supply voltage V ₂ fluctuates and drops, the FET 30
The gate-source voltage of is also decreased. Gate of FET30
When the source-source voltage drops, the FET 30
The drain-source current increases, and the voltage applied to the resistors 31 and 32 increases. However, when the power supply voltage V ₁ changes and drops in the same manner as the power supply voltage V ₂ , the gate voltage and the source voltage in the FET 30 also change, so the drain-source voltage also drops,
The drain-source current in the FET 30 is kept constant. As a result, the power supply voltage applied from the power supply voltage stabilizing circuits 24 and 26 to the gates of the FETs 21 and 22 is stabilized by the voltage fluctuations absorbed by the power supply voltage stabilizing circuits 24 and 26. The power supply voltage applied from the power supply voltage stabilizing circuits 25 and 27 to the drains of the FETs 21 and 22 is stabilized by the voltage fluctuations absorbed by the power supply voltage stabilizing circuits 25 and 27.

The FET 21 amplifies the input signal Si using the power supply voltage provided from the power supply voltage stabilizing circuits 24 and 25, and the FET 22 responds to the signal output from the source of the FET 21 by the power supply voltage stabilizing circuit. Amplification signal S is obtained by performing amplification using the power supply voltage given from 24 and 25.
22 is output. In the output signal level stabilization circuit 23, the resistor 23a superimposes the voltage corresponding to the power supply voltage V ₂₇ given from the power supply voltage stabilization circuit 27 on the amplified signal S22 and raises it to a constant level. As a result, the correction signal S22a
Is generated. The OR circuit 23b compares the amplified signal S22 with the correction signal S22a, selects the one with the higher level, and outputs it. As a result, for example, when the amplified signal S22 does not reach the desired level due to variations in the characteristics of the FETs 21 and 22, the correction signal S22a is selected and the signal S2 is selected.
It is output as 3b. Signal S output from OR circuit 23
23b is output from the output terminal T12 as the output signal So of the power amplifier circuit 20.

As described above, in the power amplifier circuit 20 of the present embodiment, the output signal level stabilizing circuit 23 is provided on the output side of the cascade-connected FETs 21 and 22, so that, for example, the characteristics of the FETs 21 and 22 vary. Also, the output signal So that is not affected by the variation can be obtained. Also, each F
Since the power supply voltage stabilizing circuits 24 to 27 that absorb the voltage fluctuations of the power supply voltages V ₁ and V ₂ given to the ETs 21 and 22 are provided, a stable output voltage So can be obtained even if the power supply voltages V ₁ and V ₂ fluctuate. You will get it. Further, since the power supply voltage V ₂₇ applied to the output signal level stabilizing circuit 23 is also stabilized by the power supply voltage stabilizing circuit 27, the level of the output signal So becomes a constant level and becomes stable. The present invention is not limited to the above-mentioned embodiment, and various modifications can be made. The following are examples of such modifications. (1) FET21 cascaded to the input terminal T11,
22 is not limited to two stages, and FETs 21 and 2 are provided in three or more stages.
Even if you increase 2 and amplify the input signal with these,
By providing the power supply voltage stabilizing circuits 24 to 27 and the output signal level stabilizing circuit 23 correspondingly, the same effect as that of the above-described embodiment can be obtained. (2) The FETs 21, 22 and 30 can also be composed of, for example, bipolar transistors or the like that perform the same operation.

[0011]

As described in detail above, according to the first and second aspects of the invention, the voltage corresponding to the power supply voltage is superimposed on the amplified signal given from the final stage amplifier of the cascaded amplifiers. Since the correction means for generating the correction signal is provided, for example, even when the characteristics of the amplifier vary and the amplified signal of a desired level cannot be obtained, the correction means can perform the correction . According to the third invention , since the correction means and the power supply voltage stabilizing circuit are provided, a stable output signal can be obtained at a desired level without being influenced by, for example, fluctuations in the power supply voltage or variations in the characteristics of the amplifier. . According to the fourth invention, since the structure which gives a stable power supply voltage to be output from the power supply voltage regulator circuit to the correction means it can realize a high power amplifier circuits From Jodo Furthermore than the third invention.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a power amplifier circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional power amplifier circuit.

3 is a circuit diagram showing an example of an output signal level stabilizing circuit in FIG.

FIG. 4 is a circuit diagram showing an example of a power supply voltage stabilizing circuit in FIG.

[Explanation of symbols]

20 power amplifier circuit 21,22 FET (amplifier) 23 Output signal level stabilization circuit 23a Resistance (correction means) 23b OR circuit (selecting means) 24-27 Power supply voltage stabilization circuit T11 input terminal T12 output terminal T13, T14 power supply terminal Si input signal S22 amplified signal S22b Correction signal

Claims (4)

(57) [Claims] 1. An amplifying operation of each of the amplifiers, comprising a plurality of stages of amplifiers connected to power supply terminals and cascaded to input terminals for inputting an input signal, and using a power supply voltage supplied from the power supply terminals. In the power amplifier circuit that amplifies the input signal to a desired level and outputs the amplified signal, the power supply circuit is connected to the output side of the final-stage amplifier and supplies the amplified signal given from the final-stage amplifier to the amplified signal. power amplifier circuit, characterized in that a correction means for superimposing a voltage corresponding to a voltage to generate a correction signal, and outputs the correction signal instead of the amplification signal. 2. An amplifying operation of each of the amplifiers, which comprises a plurality of stages of amplifiers each connected to a power supply terminal and cascaded to an input terminal for inputting an input signal, and using a power supply voltage given from the power supply terminal. In a power amplifier circuit that generates an output signal by amplifying the input signal to a desired level by the above, it is connected to the output side of the amplifier at the final stage, and the amplified signal given from the amplifier at the final stage becomes the power supply voltage. A correction unit that superimposes a corresponding voltage to generate a correction signal, compares the amplified signal with the correction signal, and selects and outputs the correction signal when the amplified signal does not reach a desired level. Then, the power amplifier circuit is provided with a selecting means for selecting and outputting the amplified signal when the amplified signal is at a desired level. 3. A power amplifier circuit according to claim 1 or 2.
Is connected between the power supply terminal and each of the amplifiers in the path.
Amplifies the stabilized power supply voltage by absorbing the fluctuation of the source voltage
It is characterized by the provision of a power supply voltage stabilization circuit
Power amplifier circuit. 4. The power amplifier circuit according to claim 3.
The power supply voltage stabilizing circuit is provided with the stabilized power supply voltage.
Is provided to the correction means.
Word amplifier circuit