JP3491254B2 - Logic device including low voltage supply device and method for supplying voltage to logic device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic device including a low voltage supply device for reducing the power consumption of a device that operates by a clock, and a method for supplying a voltage to the logic device.

[0002]

2. Description of the Related Art Logic devices such as a microprocessor, a digital signal processor, and a memory which operate with a clock are put into practical use as a system. The operating speed of each logic device is the input clock, power supply voltage, temperature,
Determined by manufacturing variations. The specifications are set to operate within all of these conditions. For example, if there is a logic device having an input frequency of 100 MHz, a power supply voltage of 3.3 ± 10%, and a temperature of −40 to 125 degrees, this logic device always has a power supply voltage of 3.3 ± 10% when the input frequency is 20 MHz. It works even if it is not 10%.

If it can operate at 2 V at 20 MHz, power consumption P is frequency F and power supply voltage V is P∝FVV
Since it works with the square of the voltage, power consumption is 37% compared to 3.3V operation.

As a method of controlling these power supply voltages, A LEAN of 1997 VLSI SYNPOSIUM SAKIYAMA ET AL
There is a method of inputting an input frequency to a dummy cell proposed in POWER MANAGEMENT TECHNIQUE and transmitting the state to a DC-DC converter which is a power supply device by a DA converter.

[0005]

However, in these power supply voltage control methods, a logic device including a highly accurate low voltage supply device such as a DA converter must be placed inside or outside the chip. There is a problem that the area is increased or the cost of the chipset is increased.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to supply an optimum power supply voltage and current according to operating frequency, process condition and temperature condition to a logic device to keep power consumption low. .

[0007]

In order to achieve the above object, the present invention uses a voltage applied to a VCO circuit in a PLL circuit that generates the same clock frequency as a logic device operating with a clock as a reference voltage of the power supply device. Then, based on the reference voltage, the lowest voltage that operates at the frequency value of the clock is generated and supplied to the power supply terminal of the logic device.

This VCO circuit has a considerably smaller number of elements than a DA converter or the like, does not require any precision, and can reduce the power consumption of a logic device with only a small area, which is economical.

FIG. 1 shows each embodiment of the present invention.
From now on, it demonstrates using FIG.

[0010]

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a logic device including a low voltage supply device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 is a logic device 1 including a CPU bus controller timer and the like, which has an input clock terminal 11 and a power supply terminal 12. The input clock 2 is input to the input clock terminal 11 of the logic device 1, and the output terminal 52 of the power supply device 5 is connected to the power supply terminal 12 of the logic device 1.
It is connected to the. 3 is a PLL circuit. This PLL
The circuit 3 includes a phase comparator 31, a charge pump 32,
The loop filter 33 and the VCO circuit 34 make up V
The CO circuit 34 is incorporated in the logic device 1. Here, the phase comparator 31 has a reference clock input terminal 311.
And a comparison target clock input terminal 312, an up signal output terminal 313, and a down signal output terminal 314, and the reference clock input terminal 311 is connected so that the input clock 2 is input. If the phase of the rising edge of the comparison target clock is later than the rising edge of the reference clock, the up signal is enabled for the time corresponding to the phase difference, and if the phase of the comparison target clock is earlier than the reference clock, only the time corresponding to the phase difference is applied. The down signal is enabled.

The charge pump 32 has an up signal input terminal 321, a down signal input terminal 322, and a charge pump output terminal 323, and an up signal input terminal 321.
, While the down signal input terminal 322 is enabled, discharges a constant charge from the charge pump output terminal 323.

The loop filter 33 is connected to the charge pump output terminal 323 and adjusts the feedback system of the PLL circuit 3. The VCO circuit 34 has a voltage control terminal (VCO input terminal) 341 connected to the loop filter 33, and outputs a clock having a frequency depending on the output voltage of the loop filter 33 from the VCO output terminal 342. The VCO output terminal 342 is connected to the comparison target clock input terminal 312 of the phase comparator 31. The power source of the PLL circuit 3 is always a constant voltage.

Reference numeral 4 is a filter section, which is a VCO circuit 34.
Is connected to the voltage control terminal 341 of the power supply device 5, and the output terminal 42 of the filter unit 4 is connected to the reference voltage terminal 51 of the power supply device 5 and supplies a predetermined power supply voltage according to the voltage value. An external power supply 6 is connected to the external power supply input terminal 50 of the power supply device 5.

FIG. 2 shows a detailed circuit diagram of the VCO circuit 34 of FIG. The VCO circuit 34 is composed of a MOS transistor generated in the same process step as the logic device 1. That is, the voltage of the node 3401 of the MOS transistor and the voltage of the node 3402 are the same as those of the current mirror circuit 3.
43 (bias voltage generation circuit) allows the VCO circuit 3
4 VCO input terminal 341 voltage value. Reference numeral 344 denotes a current control type inverter (hereinafter referred to as an inverter), the source of which is connected to the source of the MOS transistor 3440, the node of which is connected to the node 3401, and the amount of current supplied to the source of the MOS transistor 3420 depending on the voltage value of the node 3401. Are in control.
Similarly, the source of the MOS transistor 3430 is connected, the gate of which is connected to the node 3402, and the node of the node 340.
The voltage value of 2 controls the amount of current supplied to the source of the MOS transistor 3430. The MOS transistors 3420 and 3410 are an inverter circuit.
The inverters 345 and 346 also have the same configuration as the inverter 344, and the inverters 344 to 346 form a loop of a three-stage inverter chain and oscillate, and the output of the inverter 346 becomes the VCO output terminal 342 of the VCO circuit 34. ing.

The relationship between the voltage at the VCO input terminal 341 and the output frequency at the VCO output terminal 342 of the VCO circuit 34 is shown in FIG.
Shown in. As shown in FIG. 3, the input voltage V0 of the VCO circuit
The relationship between (horizontal axis: applied voltage) and output frequency F (vertical axis) is
The slope varies depending on temperature and process fluctuations. Graph (a), (b), (c) a low temperature, ambient temperature, I at elevated temperatures
The relationship between DS and VTH is shown. That is, the absolute value of the drain-source current IDS per unit gate width and gate length which is a good process at a low temperature is high, and the threshold voltage VT is high.
The lower the absolute value of H, the steeper the slope (a).
The slope becomes gentler as the absolute value of the drain-source current IDS per unit gate width and gate length, which is a bad process, becomes higher and the absolute value of the threshold voltage VTH becomes higher (b), (c). . Output frequency F of the VCOC circuit 34
At the same frequency, when the temperature and process are different, when the temperature is high or when the process is bad, the input voltage rises, and when the temperature is low or the process is good, the input voltage falls.

FIG. 4 shows the power supply voltage V and the frequency F of the logic device 1.
It is a characteristic graph of. Even in the characteristic graph of the power supply voltage V (horizontal axis: supply voltage) and the frequency F (vertical axis) of the logic device 1 shown in FIG. 4, the operation stable boundary line is different when the temperature and the process are different, and when the temperature is high, When the process is bad, the operation stability boundary line is gentle (c), when the temperature is low,
When the process is good, the operation stable boundary line is steep (a), (b).

As described above, the voltage VIN of the VCO input terminal 341 of the VCO circuit 34 and the power supply voltage V of the logic device 1 are represented by (Equation 1).

[0019]

[Equation 1]

However, A and B are positive numbers, and C is an arbitrary value. As can be expressed by this (Equation 1), the VCO input terminal 34
It is represented by an increasing function of B of the voltage VIN of 1.

The voltage VI when the PLL circuit 3 is locked
A, B, and C represented by N in (Equation 1) are used as the filter unit 4
So that it becomes (Equation 2) by using a resistance element, a capacitance element, a transistor, and a diode,

[0022]

[Equation 2]

By setting the output to the control voltage of the power supply device 5, the logic device 1 can operate at the lower limit voltage that can operate at an arbitrary frequency.

For example, n-channel TR, IDS = 4
00UA / UM, VTH = 0.5V, p-channel T
It is assumed that the function of the operating frequency and the input voltage of the VCO circuit 34 configured by R, IDS = 200 UA / UM and VTH = -0.5 V is (Equation 3).

[0025]

## EQU00003 ## F = 100 (VIN-0.5) F [MHz], VIN [V] VCO Operating frequency F (vertical axis) of the circuit 34 and input voltage V
A graph of the relationship of (horizontal axis: applied voltage) is shown in FIG.

It is assumed that the operable lower limit frequency of the logic device 1 is a function of the power supply voltage V and is operated by (Equation 4).

[0027]

## EQU00004 ## F.ltoreq.50 (V-0.5) FIG. 6 is a graph showing the relationship between the operable lower limit frequency F (vertical axis) of the logic device 1 and the power supply voltage V (horizontal axis: supply voltage).

The output voltage V (vertical axis: supply voltage) of the power supply device 5 is directly proportional to the reference voltage V (horizontal axis). The output voltage V of the power supply device 5 at this time and the reference voltage V
A graph of the relationship of is shown in FIG. At this time, the filter unit 4 may form (Equation 5).

[0029]

[Equation 5] V ≧ 1/2 VIN Each example of the circuit diagram of the filter unit 4 is shown in FIG. Figure 8
In the case of the circuit diagram of (a), p-channel TR43 and 2
With the resistance elements 44 and 45 alone, the resistance elements are connected in series, the applied voltage of the VCO circuit 34 is connected to the filter unit input terminal 41 on one side, and the p-channel TR 43 is connected on the other side.
Of the p-channel TR is connected, and the gate and drain of the p-channel TR are grounded. In the output of the filter unit 4, the connection point of the same resistance element becomes the filter unit output terminal 42. This filter unit 4 satisfies the expression (5), which is V shown in FIG.
The characteristics of the applied voltage V (horizontal axis) and the output voltage V (vertical axis: reference voltage) of the CO circuit 34 can be realized. In the case of the circuit diagram of FIG. 8B, two resistance elements 44 and 45 are connected in series,
On the other hand, the applied voltage of the VCO circuit 34 is connected to the filter unit input terminal 41, and the output of the filter unit 4 has the connection point of the same resistance element as the filter unit output terminal 42.

As described above, by monitoring the reference voltage of the power supply device described in the first embodiment, the voltage of the logic device 1 becomes the optimum voltage according to the frequency, process and temperature.

In the first embodiment, the phase comparator 31,
The charge pump 32, the loop filter 33, the filter unit 4, and the power supply device 5 may be externally attached to a logic device including a low voltage supply device.

Further, when the VCO circuit in which the relationship between the input voltage and the frequency is expressed by an increasing function as in the first embodiment is used, the output voltage of the power supply device 5 is directly proportional to the control voltage for convenience. However, as long as it has the characteristic of the increasing function expressed by the reference voltage, it is sufficient. In that case, the filter unit 4 and the power supply device 5 may be set to (Equation 6).

[0033]

[Equation 6]

When the VCO circuit in which the relationship between the input voltage and the frequency of the VCO circuit is expressed by a decreasing function is used, the power supply device 5 may be expressed by the decreasing function of the control voltage (Equation 7).

[0035]

[Equation 7]

However, A, B, and C may form the filter unit 4 which can be determined by an arbitrary number.

(Second Embodiment) FIG. 10 is a block diagram showing a structure of a logic device including a low voltage supply device according to a second embodiment of the present invention.

Blocks having the same functions as in FIG. 1 of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

Next, a description will be given of the components different from those in FIG. 1 described above.
The reference voltage terminal 348 of the O circuit 34 is connected, the output terminal 42 of the filter unit 4 is connected to the reference voltage terminal 51 of the power supply device 5, and a predetermined power supply voltage is supplied according to the voltage value. There is.

FIG. 11 is a detailed circuit diagram of the VCO circuit 34 of FIG. The VCOC circuit 34 in FIG. 11 is an operational amplifier OT.
Transistor 3 produced in the same process as A and logic device 1
471 to 473 and a loop of the critical path circuit 3474 of the logic device 1, and the VCO input terminal 3
The current according to the voltage value of 41 is the critical path circuit 347.
It flows to 4. The p-channel transistor 3473 of the circuit 347 can be model-approximated by the parallel connection of the current source and the resistance element R. The smaller the amount of current is, the larger the resistance becomes.
The voltage value at the connection point 3475 decreases. This connection point 347
The voltage value of 5 is equivalent to the minimum required voltage value of the logic device 1. In the filter unit 4, the voltage at the connection point 3475 is smoothed by a capacitor or the like, and the voltage is supplied to the reference voltage terminal 51 of the power supply device 5. Reference voltage terminal 348 of VCO circuit 34
Voltage V (horizontal axis) and the supply voltage V to the logic device 1 (vertical axis)
A graph of the relationship of is shown in FIG.

As described above, by monitoring the reference voltage of the power supply device described in the second embodiment, the voltage of the logic device 1 becomes the optimum voltage according to the frequency, process and temperature.

The circuit 347 is an example, and basically the circuit 347 may have a circuit configuration in which a current proportional to the current flowing in the transistor 3471 flows in the critical path circuit 3474.

Further, the critical path circuit 3474 of the VCO circuit 34 may be composed of an ASIC circuit which can easily change the critical path circuit configuration according to the type of the logic device 1. Since this ASIC circuit can be changed with one mask in the process step like the ROM and the like, the development period can be shortened.

(Third Embodiment) FIG. 13 is a block diagram showing a structure of a logic device including a low voltage supply device according to a third embodiment of the present invention.

Blocks having the same functions as those in FIG. 1 of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

Next, a description will be given of components different from those shown in FIG. 1. Reference numeral 35 denotes an unlock detector of the PLL circuit 3, which has an up signal output terminal 313 of the phase comparator 31.
The down signal output terminal 314 is used as an input, and when any of the input signals exceeds a certain time, the output signal is output from the up signal output terminal 353 to the filter unit 4. The up signal output terminal 353 of the detector 35 is connected to the analog switch unit 46 of the filter unit 4.

The third embodiment of the present invention will be described with reference to FIG. When the PLL circuit 3 is in the initial state or unlocked, the analog switch unit 46 of the filter unit 4 is turned off, and the reference voltage terminal 51 of the power supply device 5 is supplied with the voltage of the external power supply 6 to the logic device 1. The voltage will be When locked, it operates on the principle described in the first and second embodiments.

As described above, according to the third embodiment, when the PLL circuit 3 is unlocked, the voltage itself of the external power supply 6 is applied to the logic device 1.
To prevent the logic device 1 from malfunctioning.

(Fourth Embodiment) FIG. 14 is a block diagram showing a structure of a logic device including a low voltage supply device according to a fourth embodiment of the present invention. This configuration is almost the same as that of the third embodiment, except that the VCO output terminal 342 and the phase comparator 31 are used.
The difference is that the frequency divider 36 is connected between the comparison target clock input terminals 312 to generate a clock obtained by multiplying the input clock 2 and supply the clock to the logic device 1. With the configuration shown in FIG. 14, the PLL circuit 3 can have two functions, that is, the function of operating the logic device 1 at the multiplication of the input clock 2 and the function of supplying the reference voltage of the power supply device 5.

In the fourth embodiment, one PLL circuit can be used for both the multiplication function and low power consumption, and the area of the logic device including the low voltage supply device can be reduced.

(Fifth Embodiment) FIG. 15 is a block diagram showing a structure of a logic device including a low voltage supply device according to a fifth embodiment of the present invention.

The same functional blocks as those in FIG. 1 of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

Next, a description will be given of the names of components different from those in FIG. 1. The VCO input terminal 341 of the VCO circuit 34 is
It is connected to the loop filter 33, and a clock having a frequency that depends on the output voltage of the loop filter 33 is VCO
Output from the output terminal 342. VCO output terminal 342
Is a comparison target clock input terminal 312 of the phase comparator 31.
It is connected to the. The power source of the PLL circuit 3 is always a constant voltage.

Further, the reference voltage terminal 34 of the VCO circuit 34
8 is connected to the filter section input terminal 41 of the filter section 4, and the reference voltage terminal 349 of the VCO circuit 34 is connected to the connection terminal 48 of the filter section 47. The power supply terminal 12 of the logic device 1 including a CPU bus controller timer is connected to the external power supply 6, and the ground terminal 13 of the logic device 1 is grounded externally. The output terminal 42 of the filter unit 4 is connected to the control input terminal 14, and the output terminal 49 of the filter unit 47 is connected to the control input terminal 15.

FIG. 16 is an internal circuit diagram of the logic device 1. The gate of the p-channel transistor 16 is connected to the control input terminal 14, and the source is the power supply terminal 12 (see FIG. 1).
5)), and the drain is connected to the source and the base of the p-channel transistor that constitutes the logic circuit 17. The gate of the n-channel transistor 18 is connected to the control input terminal 15, the source is connected to the ground terminal, and the drain is connected to the source of the n-channel transistor forming the logic circuit 19 and the substrate.

FIG. 17 is a circuit example of the VCO circuit 34 of FIG. 15, in which the critical path circuit 340 of the logic circuit 17 of FIG. 16 is formed into a loop structure and the p-channel transistors of the critical path circuit of the logic circuit 17 are formed. The source and the substrate are connected to the drain of the p-channel transistor 3441, and the p-channel transistor 3441 is connected.
The source and board of 41 are connected to a constant voltage source.

The gate of the p-channel transistor 3441 is connected to the output 3401 of the bias voltage generating circuit 343 which generates the voltage for supplying the current corresponding to the VCO input terminal 341 to the p-channel transistor 3441, and the logic circuit 17 Critical path circuit 340
The source and the base of the n-channel transistor constituting the above are connected to the drain of the n-channel transistor 3431, and the source and the base of the n-channel transistor 3431 are grounded.

The gate of the n-channel transistor 3431 is connected to the output terminal 3402 of the bias voltage generating circuit 343 which generates the voltage for supplying the current corresponding to the VCO input terminal 341 to the n-channel transistor 3431.

The fifth embodiment of the present invention will be described with reference to FIGS. p-channel transistor 3
441 can be model-approximated in parallel with a current source and a resistance element,
The smaller the amount of current, the larger the resistance, and the voltage value at the connection point 3442 between the critical path circuit 340 and the p-channel transistor 3441 which is the current source decreases. The voltage value of the connection point 3442 is equivalent to the minimum necessary voltage value of the logic circuit 17. The filter unit 4 smoothes the voltage of the output terminal 3401 of the bias voltage generation circuit 343 with a capacitor or the like, and supplies the voltage to the control input terminal 14. The n-channel transistor 3431 can be model-approximated in parallel with a current source and a resistance element. The smaller the amount of current, the larger the resistance, and the critical path circuit 340 and the current source n-.
The voltage value of the connection point 3432 of the channel transistor 3431 increases. The voltage value at the connection point 3432 is equivalent to the required upper limit voltage value of the logic circuit 17. In the filter unit 47, the output terminal 3 of the bias voltage generation circuit 343 is
The voltage of 402 is smoothed by a capacitor, and the control input terminal 15
Supply voltage to.

As described above, in the fifth embodiment, the output terminals 3401 and 340 of the bias voltage generating circuit 343 of the VCO circuit are provided.
By connecting 2 to the control voltage terminal of the logic device 1, the logic circuit 17 of the logic device 1 has an optimum voltage according to the frequency, process, and temperature. As a result, the current of the logic device 1 becomes a current amount according to the input clock frequency, and if the frequency of the input clock 2 of the logic device 1 becomes lower, the current amount of the logic device also decreases. Therefore, the power consumption of the logic device can be reduced.

The circuit shown by the bias voltage generation circuit 343 is an example, and basically, the transistor 34
The circuit configuration may be such that a current proportional to the current flowing in 41 flows in the critical path circuit 340.

Further, the critical path circuit 340 of the VCO circuit 34 may be composed of an ASIC circuit that can be easily changed to a critical path circuit configuration according to the type of logic device. Since this ASIC circuit can be changed with one mask in the process step like the ROM and the like, the development period can be shortened.

(Sixth Embodiment) FIG. 18 is a block diagram showing the structure of a logic device including a low voltage supply device according to a sixth embodiment of the present invention, which is the same as FIG. However, the configuration of the logic device 1 is different from that shown in FIG. That is, FIG. 19 is an internal circuit diagram of the logic device 1 of FIG. 18, and the gate of the p-channel transistor 16 is the control input terminal 1
4, the source is connected to the power supply terminal 12, and the drain is connected to the source of the p-channel transistor forming the logic circuit 17. The base of the p-channel transistor that constitutes the logic circuit 17 is connected to the power supply terminal. The gate of the n-channel transistor 18 is connected to the control input terminal 15, the source is connected to the ground terminal, and the drain is connected to the source of the n-channel transistor forming the logic circuit 19. The base of the n-channel transistor forming the logic circuit 19 is connected to the ground terminal.

FIG. 20 is a circuit example of the VCO circuit 34 of FIG. 15, in which the critical path circuit 340 of the logic circuit 17 of FIG. 19 is formed into a loop structure, and the p-channel transistors of the critical path circuit of the logic circuit 17 are formed. The source is connected to the drain of the p-channel transistor 3441, and the base of the p-channel transistor forming the critical path circuit and the source and the base of the p-channel transistor 3441 are connected to a constant voltage source.

The gate of the p-channel transistor 3441 is connected to the output terminal 3401 of the bias voltage generating circuit 343 which generates the voltage for supplying the current corresponding to the VCO input terminal 341 to the p-channel transistor 3441, and the logic circuit. 17 critical path circuit 3
The source of the n-channel transistor that constitutes the n-channel transistor 40 is connected to the drain of the n-channel transistor 3431, and the n-channel transistor that constitutes the critical path circuit 340.
The base of the channel transistor and the source and base of the p-channel transistor 3431 are grounded.

The gate of the n-channel transistor 3431 is connected to the output terminal 3402 of the bias voltage generating circuit 343 which generates the voltage for supplying the current corresponding to the VCO input terminal 341 to the n-channel transistor 3431.

The sixth embodiment of the present invention will be described with reference to FIGS. p-channel transistor 3
441 can be model-approximated in parallel with a current source and a resistance element,
The smaller the amount of current is, the larger the resistance becomes, and the source of the p-channel transistor that constitutes the critical path circuit 340 and the p-channel transistor 344 that is the current source.
The voltage value of the connection point 3442 of 1 decreases. This connection point 34
The voltage value of 42 is equivalent to the minimum necessary voltage value of the logic circuit 17. The filter unit 4 smoothes the voltage of the output terminal 3401 of the bias voltage generation circuit 343 with a capacitor or the like, and supplies the voltage to the control input terminal 14. The n-channel transistor 3431 can be model-approximated by a current source and a resistance element in parallel, and the smaller the amount of current, the larger the resistance.
The voltage value at the connection point 3432 between the source of the n-channel transistor that constitutes the critical path circuit 340 and the p-channel transistor 3431 that is the current source increases. The voltage value at the connection point 3432 is equivalent to the required upper limit voltage value of the logic circuit 17. The filter unit 47 smoothes the voltage of the output terminal 3402 of the bias voltage generation circuit 343 with a capacitor and supplies the voltage to the control input terminal 15.

As described above, by transmitting the output terminals 3401 and 3402 of the bias voltage generating circuit 343 of the VCO circuit to the control voltage terminals 345 and 346 of the logic unit 1, the transistors of the logic circuit 17 of the logic unit 1 are connected. The source has an optimum voltage according to frequency, process, and temperature. In the n-channel transistor, if the base voltage becomes lower than the source voltage, the current flowing between the drain and the source decreases. The p-channel is the opposite. As a result, the current of the logic device 1 becomes a current amount according to the input clock frequency, and if the frequency of the input clock 2 of the logic device becomes low, the current amount of the logic device also decreases. Therefore, the power consumption of the logic device can be reduced.

The circuit shown by the bias voltage generating circuit 343 is an example, and basically, the transistor 34
The circuit configuration may be such that a current proportional to the current flowing in 41 flows in the critical path circuit 340.

Further, the critical path circuit 340 of the VCO circuit 34 may be composed of an ASIC circuit which can easily change the critical path circuit configuration according to the type of logic device. Since this ASIC circuit can be changed with one mask in the process step like the ROM and the like, the development period can be shortened.

[0071]

As described above, the present invention provides a PLL in a logic device including a low voltage supply device such as a microprocessor, a digital signal processor, and a memory.
The circuit incorporates a VCO circuit, and the power supply voltage of a logic device including a low voltage supply device is determined by monitoring the input voltage of the VCO circuit or the voltage in the VCO circuit. This makes it possible to reduce the power consumption of a logic device including a low voltage supply device in a small area.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a logic device including a low voltage supply device according to a first embodiment of the present invention.

2 is a detailed circuit diagram of the VCOC circuit of FIG.

FIG. 3 is a graph showing the relationship between the input voltage and the output frequency of the VCO circuit relating to (Equation 1) in FIG.

FIG. 4 is a graph showing the relationship between the power supply voltage and the frequency of the logic device relating to (Equation 2) in FIG. 1;

5 is a graph showing the relationship between the input voltage and the frequency of the VCO circuit relating to (Equation 3) in FIG.

6 is a graph showing the relationship between the power supply voltage and the frequency of the logic circuit relating to (Equation 4) in FIG. 1;

7 is a graph showing the relationship between the reference voltage and the supply voltage of the power supply device of FIG.

FIG. 8 is a circuit diagram of the filter unit in FIG.

9 is a graph showing the relationship between the input voltage and the output voltage of the filter unit shown in FIG.

FIG. 10 is a block diagram showing a configuration of a logic device including a low voltage supply device according to a second embodiment of the present invention.

11 is a detailed circuit diagram of the VCOC circuit of FIG.

12 is an internal voltage of the VCO circuit of FIG. 10 and the logic device 1;
Graph showing the relationship of the supply voltage of

FIG. 13 is a block diagram showing a configuration of a logic device including a low voltage supply device according to a third embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a logic device including a low voltage supply device according to a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a logic device including a low voltage supply device according to a fifth embodiment of the present invention.

16 is an internal circuit diagram of the logic device of FIG.

FIG. 17 is a VCOC circuit of FIG.

FIG. 18 is a block diagram showing a configuration of a logic device according to a sixth embodiment of the present invention.

FIG. 19 is an internal circuit diagram of the logic device shown in FIG.

20 is a detailed circuit diagram of the VCO shown in FIG.

[Explanation of symbols]

1 Logic device including low voltage supply device 2 input clock 3 PLL circuit 4,47 Filter section 5 power supply 6 External power supply

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 1/26-1/32 H03L 7/06 G06F 1/04

Claims (7)

(57) [Claims] 1. A logic device operating on a clock, comprising:
A power supply unit for supplying a predetermined voltage value at the reference voltage, a PLL circuit for a reference clock the clock, comprises a filter <br/>, the filter is V in the PLL circuit
Applied voltage VIN of the CO circuit and reference voltage V of the logic device
Are formed so as to satisfy the following formula V ≧ A (VIN + C) ^B (A and B are positive numbers , C is an arbitrary value), and VC in the PLL circuit is
A logic device including a low voltage supply device, wherein an applied voltage terminal of a circuit is connected to a reference voltage terminal of the power supply device, and the power supply device supplies the predetermined voltage value to a power supply terminal of the logic device. . 2. A logic device operating on a clock, comprising:
A power supply device that supplies a predetermined voltage value with a reference voltage, a PLL circuit that uses the clock as a reference clock, and a filter, and the filter is V in the PLL circuit .
Applied voltage VIN of the CO circuit and reference voltage V of the logic device
Are formed so as to satisfy the following formula V ≧ A (VIN + C) ^B (A and B are positive numbers , C is an arbitrary value), and VC in the PLL circuit is
The applied voltage terminal of the circuit is connected to the filter, the output of the filter is connected to the reference voltage terminal of the power supply, the output of the power supply is connected to the power supply terminal of the logic device, A logic including a low voltage supply device characterized in that a voltage value of an applied voltage terminal of a VCO circuit in a PLL circuit is smoothed by the filter and the predetermined voltage value is supplied from the power supply device to a power supply terminal of the logic device. apparatus. 3. A clocked logic device comprising:
A power supply device that supplies a predetermined voltage value with a reference voltage, a PLL circuit that uses the clock as a reference clock, and a filter, and the filter is V in the PLL circuit .
Applied voltage VIN of the CO circuit and reference voltage V of the logic device
Are formed so as to satisfy the following formula V ≧ A (VIN + C) ^B (A and B are positive numbers , C is an arbitrary value), and VC in the PLL circuit is
An output voltage terminal of a bias voltage generating circuit of the circuit is connected to the filter, an output of the filter is connected to a reference voltage terminal of a power supply device, an output of the power supply device is connected to a power supply terminal of the logic device, A voltage value of an output voltage terminal of a bias voltage generating circuit of a VCOC circuit in the PLL circuit to the power supply device is smoothed by the filter, and the predetermined voltage value is supplied from the power supply device to a power supply terminal of the logic device. A logic device including a low voltage supply device characterized. 4. The VCO circuit comprises a current source having a current amount corresponding to an applied voltage of the VCO circuit and a loop of a critical path of the logic device connected to the current source, and a bias of the VCO circuit. 4. The output voltage terminal of the voltage generating circuit is connected to a power supply terminal of a critical path of the logic device connected to a current source having a current amount corresponding to the applied voltage of the VCO circuit. A logic device including a low voltage supply device of. 5. The low voltage supply device according to claim 4, wherein the loop circuit of the critical path of the logic device is configured by a loop circuit of the critical path according to the type of the logic device. Logical unit. 6. A clock-operated logic device comprising:
A fixed power supply device, a power supply device that supplies a predetermined voltage value with a reference voltage, a PLL circuit that uses the clock as a reference clock, an unlock detector that outputs an enable signal when the PLL circuit is unlocked, and a filter. 2 inputs 1
A VC in the PLL circuit having an output switch
The applied voltage terminal of the circuit is connected to one of the inputs of the switch, the other input of the switch is connected to the fixed power supply, the output of the switch is connected to the filter, and the output of the filter is Connected to a reference voltage of a power supply, an output of the power supply connected to a power supply terminal of the logic device, an output of the unlock detector connected to a control terminal of the switch, and when the PLL circuit is unlocked, The switch outputs the voltage value of the fixed power supply device and supplies it to the power supply terminal of the logic device by the filter and the power supply device. When the PLL circuit is locked, the switch applies the voltage applied to the VCOC circuit in the PLL circuit. The voltage of the terminal is output, and the filter is the PLL.
The voltage VIN applied to the VCO circuit in the circuit and the reference voltage V of the logic device are formed so as to satisfy the following formula V ≧ A (VIN + C) ^B (A and B are positive numbers , C is an arbitrary value), and A logic device including a low voltage supply device, wherein the predetermined voltage value is supplied to a power supply terminal of the logic device by a filter and the power supply device. 7. A constant voltage at which the logic device operates at the frequency of the clock, until the second clock having the same phase difference and frequency of the clock in the clock-operated logic device is generated. A method for supplying a voltage to a logic device, which comprises: