JP3490759B2 - Absolute encoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder in which an absolute position signal corresponding to a rotation angle is output as a bit code in parallel even when an encoder plate such as a rotary disk is stationary. More specifically, it relates to a synchronous control system for the upper bit signal and the lower bit signal.

[0002]

2. Description of the Related Art An encoder is widely used for detecting the position of an arm of a robot and reads a scale of an encoder plate attached to a rotary shaft of a motor with a detecting element. Position detection methods include incremental type and absolute type. The former reads the position by counting the detection pulses with the origin of the encoder plate or the rotating disk as a reference. The latter detects the position by reading the code on the encoder plate at any position on the rotating disk. For this reason, in the incremental type, when the power is turned off and then restarted, it is necessary to make a maximum of one rotation for the home return operation, whereas in the absolute type, the rotating disk does not move even if the power is turned on again. Since it is possible to read, there is an advantage that the origin return operation becomes unnecessary.

FIG. 4 shows a general structure of a conventional absolute encoder. A plurality of tracks 102 to 105 are concentrically formed on the surface of the rotating disk 101. Each track is composed of a slit pattern bit-coded according to a digital code indicating the absolute position of the rotating disk 101. A light receiving element array 106 is arranged on one surface side of the rotating disk 101, and a light emitting element such as the LED 10 is arranged on the other surface side via a fixed slit 107.
8 are arranged. Light from the LED 108 is transmitted or blocked by the slit pattern on the rotating disk 101, and the light receiving element array 106 outputs a detection signal according to the amount of light received for each track. By processing this detection signal, the absolute position or address of the rotation angle of the disk 101 can be read. That is, this address corresponds to the digital code described above.

Various systems are known as digital codes representing addresses. FIG. 5 shows a slit pattern formed by using a binary coded quaternary number as an example of the digital code. In this pattern diagram, the vertical column indicates the track number and the horizontal column indicates the address. In this example, a track for 4 bits is provided and 2 ⁴ = 16 absolute addresses are represented. 2 assigned to a pair of tracks T ₀ , T ₁
The bits make up the lower four digits of the quaternary. For example, addresses 0 to 3 belonging to the first group can be identified according to the quaternary number of the lower digit. Similarly, the addresses 4 to 7 belonging to the second group can be identified by the quaternary number of the lower digit. The same applies to the third and fourth groups below. On the other hand, a quaternary upper digit is composed of 2 bits assigned to a pair of tracks T ₂ and T ₃ . The first to fourth sets can be identified by the quaternary number of the higher digits. Binary quaternary code can be converted into pure binary code by simple logical operation. For example, the bit signal obtained from the track T ₀ shown in FIG. 5 is P ₀ , the bit signal obtained from the track T ₁ is P ₁ , the bit signal obtained from the track T ₂ is P _2, and the bit signal obtained from the track T _3. Bit signal is P
_{If it is 3} , the first bit or the least significant bit of the pure binary code is obtained by the exclusive OR of P ₀ and P ₁ , and the second bit
The bit is equal to P ₀ , the third bit is given by the exclusive OR of P ₂ and P ₃ , and the fourth or most significant bit is equal to P ₂ .

FIG. 6 shows two types of light receiving element arrangements for reading a binary coded quaternary code pattern. In the light-receiving element array 110 on the left side, individual light-receiving elements A corresponding to four tracks are provided.
_{0 to} A ₃ are arranged in parallel. On the other hand, in the light receiving element array 111 on the right side, a pair of light receiving elements A ₀ and A ₁ are arranged along the track T ₁ with a phase difference of 90 ° with respect to the slit pattern. This pair of light receiving elements A ₀ , A
₁ can read the lower 4 digit number. Similarly, a pair of light receiving elements A ₂ and A ₃ are arranged along the track T ₃ with a phase difference of 90 °, and the upper digit quaternary number can be read. In this way, the tracks T ₀ and T ₂ are unnecessary and the number of tracks can be halved. In order to facilitate understanding of this point, a slight supplement will be given with reference to FIG. 5 again. A pair of trucks T
₀ and T ₁ each have a repetitive slit pattern having the same cycle and a phase difference of 90 °. Therefore, as shown in FIG. 6, by arranging the pair of light receiving elements A ₀ and A ₁ with their phases shifted by 90 °, all the information contained in the tracks T ₀ and T ₁ can be read. That is, four combinations of bright and bright, bright and dark, dark and bright, and dark and dark are projected on the light receiving elements A ₀ and A ₁ of the light receiving element array 111, and the quaternary information can be read. Similarly, the tracks T ₂ and T ₃ in FIG. 5 each have a repeating slit pattern in which the phases are shifted by 90 ° in the same cycle. Therefore, the upper digit quaternary number is set by the arrangement shown in the light receiving element array 111 in FIG. Can be read. Furthermore, the light receiving element array 11 is utilized by utilizing the fact that the slit pattern is repeated.
By arranging a plurality of 1's along the track row, a sufficient amount of received light can be secured.

[0006]

As described above, the number of tracks can be reduced by half by using the binary coded quaternary code pattern. However, when changing from one address to another, changes between the light and dark parts may occur at two or more locations simultaneously in a plurality of tracks. It is difficult to detect the respective changes at exactly the same time, and there is a drawback that a read error occurs due to a timing shift. In order to eliminate a read error, a synchronous control technique for a high-order bit signal and a low-order bit signal has been proposed, and is disclosed in, for example, PCT International Application Publication No. WO93 / 21499. According to this method, first, a pair of upper detection signals obtained from the upper bit track are compared with each other to obtain an upper comparison signal. Further, a pair of lower detection signals obtained from the lower bit track are compared to obtain a lower comparison signal. The upper detection signal and the lower comparison signal are logically processed to obtain a synchronization signal. The synchronization signal and the upper detection signal are added at a predetermined ratio to obtain synchronized upper intermediate signals having mutually opposite phases. Finally, a pair of upper intermediate signals are compared with each other to generate an upper bit signal. As described above, in the conventional synchronization system, the comparators are required for the comparison processing of the upper detection signal and the comparison processing of the upper intermediate signal, respectively, which complicates the circuit configuration.

[0007]

SUMMARY OF THE INVENTION In view of the above problems of the prior art, it is an object of the present invention to provide an efficient and simplified synchronization control system for high-order bit signals and low-order bit signals. The following measures have been taken in order to achieve this object. That is, the absolute encoder according to the present invention has a moving body, a light source section, a light receiving section, and a processing circuit as a basic configuration. A track group consisting of a plurality of slit patterns bit-coded according to a digital code indicating an absolute position is provided in parallel in the moving body from the upper bit to the lower bit. The light source unit illuminates the moving body. The light receiving section receives the illumination light through the slit pattern and outputs a detection signal for each track. The processing circuit processes the detection signal to generate a bit reproduction signal and reads the absolute position of the moving body. This processing circuit has an arithmetic means and arithmetically processes the lower detection signal obtained from the lower bit track and the upper detection signal obtained from the upper bit track to synchronize with the rising or falling of the lower bit reproduction signal. Generate a high-order bit reproduction signal. As a feature of the present invention, the arithmetic means includes a logic means, an addition means, and an output means. The logic means performs a logical operation process on a lower bit reproduction signal and a signal obtained by feeding back the upper bit reproduction signal, and outputs a rectangular pulse of each rectangular pulse included in the upper bit reproduction signal.
Matches to the center part and has a rising or falling edge
Generate a signal that Adding means adds processing the signal and the upper detection signal generated by said logic means at a predetermined ratio.
The output means generates a synchronized high-order bit reproduction signal based on the added signal.

[0008]

According to the present invention, the lower bit reproduction signal and the signal obtained by feeding back the upper bit reproduction signal are logically processed to generate a signal required for synchronization. Using this synchronization signal, the upper detection signal is subjected to addition processing and comparison processing, and an upper bit reproduction signal synchronized with the rising or falling of the lower bit reproduction signal is output. As described above, according to the present invention, since the high-order bit reproduction signal is fed back for synchronization, the processing circuit configuration is efficiently simplified and the number of parts can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first embodiment of an absolute encoder according to the present invention. (A) shows two tracks T ₀ and T ₁ provided along the moving direction of a moving body such as a rotating disk. Here, a slit pattern bit-encoded according to the binary coded binary code is adopted, and the track T ₀ represents the lower digit and the track T ₁ represents the upper digit. The light receiving element array 1 is arranged corresponding to the track T ₀ . In the light receiving element array 1, a pair of light receiving regions A ⁺ ₁ and A ⁺ ₀ whose phases are shifted from each other by 90 ° are formed. Also a pair of phases other shifted 90 ° from each other light receiving regions A ^-
₁ and A ^- ₀ are also formed. These pairs are in the opposite phase relation to each other, and + and-symbols are used to represent them. The light-receiving element arrays 2 and 3 having the same structure are also arranged in accordance with the light-dark slit pattern period of the track T ₀ and form a light-receiving portion. Thus, by using a plurality of light receiving element arrays, a sufficient amount of received light can be secured. On the other hand, the upper digit track T ₁ is composed of a bright and dark slit pattern having a period four times that of T ₀ . The light receiving element array 4 is arranged corresponding to this cycle. The array 4 includes a pair of light receiving regions A ⁺ ₃ and A ⁺ ₂ whose phases are shifted from each other by 90 °, and a pair of other light receiving regions A ^- _{3 which} are also shifted from each other by 90 °.
A ^- ₂ and are included. These pairs are in phase with each other
80 ° off. In addition, the span of each light receiving region, that is, the width along the track direction is equal to one cycle of the lower digit track T ₀ . With this setting, the maximum permissible width with respect to the slit pattern pitch error between tracks can be obtained.

FIG. 1B shows a processing circuit connected to the light receiving element arrays 1 and 4 shown in FIG. The detection signal output from each light receiving region is input to this processing circuit. In order to facilitate understanding, the detection signal is indicated by the same reference numeral as the reference numeral attached to the light receiving area. This processing circuit arithmetically processes the detection signals A ⁺ _{0 to} A ^- ₃ and outputs 2
Bit reproduction signals P ₀ , P ₁ , P according to the evolutionary quaternary code
₂ and P ₃ are generated. This processing circuit includes a calculating means, and a lower detection signal (for example, A ⁺ ₀ , A ^- ₀ ) obtained from the lower bit track T ₀ and an upper detection signal A ⁺ obtained from the upper bit track T _{1. 2} ~A ^-
₃ is arithmetically processed to generate upper bit reproduction signals P ₂ and P ₃ which are synchronized with the rising or falling of the lower bit reproduction signal (eg P ₀ ). This calculation means is shown in FIG.
, A plurality of comparators or comparators (CMP) 5 to 8 connected to each other, and a pair of exclusive OR circuits (XO
R) 9, 10 and a pair of inverting circuits (MOT) 11 and 1
It is composed of two and four constant-magnification circuits (× K) 13 to 16 and four addition circuits (+) 17 to 20. This computing means includes a pair of lower detection signals (eg, A ⁺
₀ , A ^- ₀ ) is compared and processed (that is, lower bit reproduction signal P ₀ ) and one upper bit reproduction signal (for example, P ₃ ).
It includes a logic unit (for example, the exclusive OR circuit 10) that performs a logical operation process on the signal obtained by feeding back the signal. Further, it includes addition means (for example, the constant-magnification circuit 16 and addition circuit 17) for performing addition processing of the signal subjected to the logical operation processing and the higher-order detection signal (for example, A ⁺ ₂ ) at a predetermined ratio (K). Further, it includes an output means (for example, a comparator 7) for comparing the signal SA ⁺ ₂ subjected to the addition processing and its opposite phase signal SA ^- ₂ and generating the other synchronized higher-order bit reproduction signal (for example P ₂ ). I'm out. The one higher-order bit reproduction signal P ₃ that is fed back is also generated by the output means (comparator 8).

Next, the operation of the absolute encoder shown in FIG. 1 will be described in detail with reference to the waveform chart of FIG. The waveform (a) is the lower detection signal A which has an opposite phase relation to each other.
^- shows a _0, A ⁺ _0. It has a relatively steep rise and fall with the passage of the light-dark slit pattern. The waveform (b) shows another pair of lower detection signals A ^- ₁ and A ⁺ ₁ which are in opposite phase to each other. This waveform (b) is
90 ° out of phase with the waveform (a). The waveform (c) has lower detection signals A ⁺ ₀ and A which are in opposite phase to each other.
^- lower bit reproduction signal P ₀ of the direct least digits represent comparative processed signal by the comparator 6 ₀ is obtained. The waveform (d) represents a signal obtained by comparing and processing another pair of lower detection signals A ⁺ ₁ and A ^- ₁ which are in opposite phase with each other by the comparator 5, and directly represents the lower bit reproduction signal P of the second digit.
You get ₁ . These pair of lower bit reproduction signals P ₀ ,
Both P ₁ are rectangular waves and their phases are shifted by 90 °.

[0012] Waveform (e) is opposite phases of the pair of upper detection signal A ^- shows a _2, A ⁺ _2. It shows a relatively gentle rise and fall as it passes through the bright and dark slit pattern of the upper track T ₂ . The degree of this inclination is related to the span of each light receiving region included in the light receiving element array 4. The longer the span, the gentler the slope. The waveform (f) shows another pair of upper detection signals A ^- ₃ and A ⁺ ₃ which are in opposite phase to each other. Similarly, while showing a gentle rise and fall, the phase is shifted by 90 ° from the waveform (e). The waveform (g) represents one upper bit reproduction signal P ₃ and is used as a feedback signal for generating the other upper bit reproduction signal P ₂ . The most significant bit reproduction signal P ₃ is generated by processing the upper detection signals A ⁺ ₃ and A ⁻ ₃ which are in the opposite phase relationship with each other by the adders 19 and 20 and then comparing them with each other by the comparator 8.

A waveform (h) shows a waveform obtained by processing the lower bit reproduction signal P ₀ and one of the fed back upper bit reproduction signals P ₃ by the exclusive OR circuit 10. This waveform has a steep rise or fall in alignment with the central portion of each rectangular pulse included in the higher-order bit reproduction signal P ₃ , and is used for the synchronization processing of the other higher-order reproduction signal P ₂ . The waveform (i) is a signal SA ⁺ obtained by adding the signal obtained by multiplying the signal P ₀ XORP ₃ that has been subjected to the exclusive OR processing by the coefficient K with the coefficient K and the higher detection signal A ⁺ _{2. 2} is shown. Further, a signal in multiplied by the coefficient K by further doubler circuit 15 an inverted signal of P ₀ XORP ₃ obtained through the inversion circuit 12, the higher the detection signal A ^- obtained by adding treated with ₂ and the adder 18 The resulting signal SA ^- ₂ is shown. The pair of signals SA ⁺ ₂ described above,
SA ^- ₂ has an opposite phase relation to each other. These signals SA
⁺ _2, SA ^- ₂ is the step S of alignment with the central portion of each rectangular pulses contained in the upper bit reproduction signal P ₃ a predetermined height is occurring. This height is determined by the coefficient K, and when the value is 0.5, the condition that the reading error is least likely to occur is obtained.

The waveform (j) is the signal S thus obtained.
A ⁺ _2, SA ^- ₂ a represents a comparison signal by the comparator 7 and the other upper bit reproduction signal P ₂ is obtained. The upper bit reproduction signal P ₂ of the third digit rises at the step S shown by the waveform (i). This rising is completely synchronized with the falling of the lower bit reproduction signal P ₀ . At this time, by setting the inclination of the inclined portion R to a desired value, the maximum tolerance for reading errors can be obtained. As described above, this inclination degree is optimized when the span of the light receiving area for the upper track is made equal to the light / dark slit pattern period of the lower track. In this case, an error corresponding to the lower half cycle is allowed for the upper track.

The higher-order bit reproduction signal P ₂ of the third digit thus obtained is fed back and used for the synchronization processing of the higher-order bit reproduction signal P ₃ of the fourth digit described above. That is, the returned upper bit reproduction signal P ₂ and the least significant bit reproduction signal P ₀ are mutually exclusive ORed by the exclusive OR circuit 9. The result is the inverting circuit 11 and the constant-magnification circuit 14.
Is added to the upper detection signal A ⁺ ₃ by the adder circuit 19 via the adder circuit 20 and is also added to the upper detection signal A ⁻ ₃ by the adder circuit 20 via the constant-magnification circuit 13. These paired addition results are compared with each other by the above-mentioned comparator 8 to obtain the higher-order bit reproduction signal P ₃ of the fourth digit.

As can be understood from the above description, in the present invention, one upper bit reproduction signal P ₃ is fed back and subjected to exclusive OR processing with the lower bit reproduction signal, and the other upper bit reproduction signal P ₂ is synchronized. It is used for the chemical treatment. The high-order bit reproduction signal P ₂ thus synchronized is similarly fed back, subjected to exclusive OR processing with the low-order bit reproduction signal, and used for the synchronization processing of the high-order bit reproduction signal P ₃ . Such cross connection stabilizes the operation of the synchronization processing circuit shown in FIG. 1 and simplifies the circuit configuration.

In the first embodiment shown in FIG. 1, four light receiving regions are provided in the light receiving element array 4 in order to obtain in-phase and anti-phase upper detection signals. However, the two light receiving regions that output the opposite phase are not always necessary and can be omitted. It is preferable to use a processing circuit that does not require an anti-phase detection signal in order to downsize and reduce the number of elements in the upper track in which the allowable range of error is wide. Figure 3
Shown in. Is basically the same structure as the circuit shown in FIG. 1 (B), reverse-phase high-order detection signals A ^- _2, A ^- is used a predetermined reference voltage Vref instead of _3.

In the above embodiment, an example in which four bit reproduction signals P _{0 to} P ₃ are obtained with two tracks has been shown, but the present invention is not limited to this, and three or more tracks are used. It can also be provided. For example, the bit reproduction signal P ₂ (or P ₃ ) of the second track is used as the lower bit reproduction signal in order to generate the upper bit reproduction signals P ₄ and P ₅ of the third track, and the upper bit reproduction signal P ₂ (or P ₃ ) is synchronized with this signal. The detection signals A ₄ and A ₅ may be arithmetically processed. Similarly, for the subsequent tracks, all tracks can be synchronized with the least significant bit reproduction signal by synchronizing with one lower track.

[0019]

As described above, according to the present invention, when an upper bit reproduction signal synchronized with a lower bit reproduction signal is generated, the upper bit reproduction signal is fed back and logically processed with the lower bit reproduction signal. And is used for the synchronization processing of the high-order bit reproduction signal. With this configuration, it is possible to effectively simplify the synchronization processing circuit and contribute to a reduction in the number of parts.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a first embodiment of an absolute encoder according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the absolute encoder shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of an absolute encoder according to the present invention.

FIG. 4 is a perspective view showing a conventional absolute encoder.

FIG. 5 is a slit pattern diagram according to a binary coded quaternary code.

FIG. 6 is a schematic view showing a light receiving area pattern applied to a slit pattern according to a binary coded quaternary code.

[Explanation of symbols]

1 Light receiving element array 2 Light receiving element array 3 Light receiving element array 4 Light receiving element array 5 comparator 6 comparator 7 comparator 8 comparator 9 Exclusive OR circuit 10 Exclusive OR circuit 11 Inversion circuit 12 Inversion circuit 13 constant rate circuit 14 constant rate circuit 15 constant rate circuit 16 constant rate circuit 17 Adder circuit 18 Adder circuit 19 adder circuit 20 adder circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References International Publication 93/021499 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01D 5/00-5/62

Claims (6)

(57) [Claims] 1. A moving body provided with a track group consisting of a plurality of bit-encoded slit patterns arranged in parallel from a high-order bit to a low-order bit in accordance with a digital code indicating an absolute position, and the moving body is illuminated. A light source section, a light receiving section that receives illumination light through the slit pattern and outputs a detection signal for each track, and a processing circuit that processes the detection signal to generate a bit reproduction signal and reads the absolute position of the moving body. In the absolute encoder consisting of, the processing circuit arithmetically processes the lower detection signal obtained from the lower bit track and the upper detection signal obtained from the upper bit track, and synchronizes with the rising or falling of the lower bit reproduction signal. The arithmetic means has an arithmetic means for generating an upper bit reproduction signal, and the arithmetic means comprises a lower bit reproduction signal and an upper bit reproduction signal. And a signal obtained by feedback by logical operation upper
In the central part of each rectangular pulse included in the bit reproduction signal
Generates a signal with matching rising and falling edges.
And logic means for forming, adding means for adding processing the signal and the upper detection signal generated by said logic means at a predetermined rate, the output for generating a high-order bit reproduction signal synchronized based on the addition processing signal An absolute encoder characterized by being composed of means. 2. The absolute encoder according to claim 1, wherein the output means compares the added signal with a constant voltage signal. 3. A track including a slit pattern which is quaternary coded according to a binary coded quaternary digital code, wherein the light receiving section is arranged along the track and corresponds to the quaternary coded slit pattern. The absolute encoder according to claim 1, comprising at least a pair of light receiving regions. 4. The absolute encoder according to claim 3, wherein the light receiving unit has a light receiving area for the upper bit track having a span corresponding to one cycle length of the slit pattern of the lower bit track. 5. The absolute encoder according to claim 3, wherein the light receiving section has a light receiving area for outputting in-phase and anti-phase detection signals for the upper bit track. 6. The absolute encoder according to claim 3, wherein the light receiving section has a light receiving area for outputting only in-phase detection signals for the upper bit track.