JP3459113B2 - Absolute encoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder in which an absolute position signal corresponding to a rotation angle is output in parallel as a bit code even when an encoder plate such as a rotating disk is stationary.

[0002]

2. Description of the Related Art An encoder is widely used for detecting the position of a robot arm, and reads a scale of an encoder plate attached to a rotary shaft of a motor by a light receiving element. Position detection methods include incremental type and absolute type. The former reads the position by counting the detection pulses with the origin of the encoder plate or the rotating disk as a reference. The latter detects the position by reading the code on the encoder plate at any position on the rotating disk. For this reason, in the incremental type, when the power is turned off and then restarted, it is necessary to make a maximum of one rotation for the origin return operation, whereas in the absolute type, the position is read without moving the rotating disk even if the power is turned on again. This has the advantage that the origin return operation is unnecessary.

FIG. 12 shows a general structure of a conventional absolute encoder. A plurality of tracks 102 to 105 are concentrically formed on the surface of the rotating disk 101. Each track is composed of a slit pattern bit-coded according to a digital code indicating the absolute position of the rotating disk 101. A light-receiving element array 106 is arranged on one surface side of the rotating disk 101, and a light-emitting element such as LED 1 is arranged on the other surface side via a fixed slit 107.
08 are arranged. Light from the LED 108 is transmitted or blocked by the slit pattern on the rotating disk 101, and the light receiving element array 106 outputs a detection signal according to the amount of light received for each track. By processing this detection signal, the absolute position or address of the rotation angle of the disk 101 can be read. That is, this address corresponds to the digital code described above.

Various systems are known as digital codes representing addresses. FIG. 13 shows a slit pattern formed according to a pure binary method as an example of a digital code. In this pattern diagram, the vertical column indicates the track number and the horizontal column indicates the address. The slit pattern of each track is 2
It is value-encoded and consists of bright and dark areas. In this example, a track for 4 bits is provided, and 2 ⁴ = 16 absolute addresses are represented. Such a pure binary code is basic in digital processing. However,
When changing from one address to another, the change between the light and dark parts may occur at two or more locations simultaneously in a plurality of tracks. It is difficult to detect the respective changes at exactly the same time, and there is a drawback that a read error occurs due to a timing shift.

The gray binary code shown in FIG. 14 improves on this drawback. As you can see from the pattern diagram, net 2
Unlike the binary code pattern, since there is a characteristic that a change in address always causes a change in brightness and darkness only in one track, a reading error hardly occurs.
However, as with the pure binary code, the gray code requires the same number of tracks as the number of bits or digits. Therefore, if the number of bits is increased for the purpose of increasing the number of addresses for higher resolution, there is a drawback that the absolute encoder is hindered from being downsized because many tracks are arranged in parallel in the radial direction of the rotary disk.

FIG. 15 shows a binary coded quaternary code pattern capable of halving the number of tracks. Two bits assigned to a pair of tracks 0 and 1 form a quaternary lower digit. For example, addresses 0 to 3 belonging to the first group can be identified according to the quaternary number of the lower digit. Similarly, the addresses 4 to 7 belonging to the second group can be identified by the quaternary number of the lower digit. Below 3rd group, 4th
The same applies to the sets. On the other hand, the 2-bit assigned to the pair of tracks 2 and 3 constitutes a quaternary upper digit.
The first to fourth sets can be identified by the quaternary number of the higher digits. Binary quaternary code can be converted into pure binary code by simple logical operation.

FIG. 16 shows two types of light receiving element arrangements for reading a binary coded quaternary code pattern. In the light receiving element array 110 on the left side, the individual light receiving elements are arranged in parallel corresponding to four tracks. On the other hand, the light receiving element array 1 on the right side
In 11, the pair of light receiving elements are arranged along the track 1 with a phase difference of 90 ° with respect to the corresponding slit pattern. A quaternary number in the lower digit can be read by the pair of light receiving elements. Similarly, a pair of light receiving elements are arranged along the track 3 with a phase difference of 90 °, and the upper digit quaternary number can be read. In this way, the tracks 0 and 2 are unnecessary and the number can be reduced by half. To facilitate understanding of this point, a slight supplement will be given with reference to FIG. 15 again. Each of the pair of tracks 0 and 1 has a repetitive slit pattern having the same cycle and a phase difference of 90 °. Therefore, as shown in FIG.
All the information contained in tracks 0 and 1 can be read by arranging them with the phases shifted by just. That is, the light receiving elements 0 and 1 of the light receiving element array 111 are bright and bright, bright and dark, dark and bright,
Four combinations of dark and dark are projected, and the quaternary information can be read. Similarly, tracks 2 and 3 in FIG. 15 each have a repetitive slit pattern with the same cycle and a phase shift of 90 °, so that the upper digit quaternary number can be read by the arrangement shown in the light receiving element array 111 in FIG.

[0008]

[Problems to be Solved by the Invention] As described above, binary evolution 4
The number of tracks can be halved by using the hexadecimal code pattern. In other words, two bit signals can be obtained from one track. However, if the number of bits is increased for the purpose of increasing the number of addresses for higher resolution, the number of tracks will increase to a considerable extent, and the absolute encoder cannot be increased in size and cost, which is insufficient. In view of this point, the present invention aims to generate more bit signals from one track. By the way, unlike the gray code pattern described above, the binary coded quaternary code pattern described above is a case where the lightness and darkness change simultaneously among a plurality of tracks. It is difficult to detect each change at exactly the same time, and a read error occurs due to a timing shift. In view of this point, it is an object of the present invention to synchronize a lower track and an upper track to eliminate a read error.

[0009]

[Means for Solving the Problems] In order to solve the above-mentioned problems of the prior art and to achieve the object of the present invention, the following measures were taken. That is, the absolute encoder according to the present invention has a moving body, a light receiving element, and a processing circuit as a basic configuration. Tracks having bright and dark slit patterns are arranged in parallel on the moving body. The light receiving element receives the illumination light through the bright and dark slit pattern and outputs a detection signal for each track. The processing circuit processes the detection signal to generate a bit signal and reads the position of the moving body. As a feature of the present invention, the processing circuit has an input unit, a comparison operation unit, and a logic operation unit. The input unit uses the detection signal to input a plurality of chevron signals having an equal period and a phase shift. The comparison operation unit compares the plurality of chevron signals with each other to generate a plurality of rectangular signals with a phase shift. The logical operation unit logically processes the plurality of rectangular signals and outputs at least three bit signals for one track. Furthermore, before
The processing circuit is a modulation processing between the input unit and the comparison operation unit.
Other processing circuit corresponding to the lower track
The plurality of chevron signals in synchronization with the periodic signal transferred from
Modulates and synchronizes low-order bit signal and high-order bit signal
It This modulation processing section has a logic means and an addition means.
It The logic means outputs the rectangular signal fed back from the comparison operation unit and the rectangular signal
Form a synchronization signal by logically operating the periodic signal with each other
It The adding means sets the synchronization signal and each chevron signal at a predetermined ratio.
To form a modulated chevron signal.

[0010]

According to one aspect of the present invention, the input unit has an adder / subtractor, and the trapezoidal detection signals having a phase difference of 90 ° are subjected to an addition / subtraction process to form a chevron signal.
Alternatively, a chevron-shaped detection signal having a phase difference of 90 ° can be used as it is as a chevron-shaped signal. According to another aspect, the input unit includes inverting means that inverts the detection signal to form a negative phase signal, and uses the detection signal and the negative phase signal to generate the plurality of chevron signals.

The light-dark slit pattern formed on the moving body has a gradual pattern in which the transmittance gradually changes from dark to light along the track direction, for example, to enable the slope formation of a mountain-shaped signal. There is. In this gradual pattern, for example, the dark portions and the light portions subdivided along the track direction are alternately arranged, and the ratio of the dark portions and the light portions changes stepwise. Alternatively, this gradual pattern may be one in which the density continuously changes from dark to light along the track direction. Furthermore, the gradual pattern may have a shape in which a boundary line that divides a dark portion and a light portion is oblique to the track direction. In the case of a moving body that moves linearly, the boundary line is an inclined straight line formed on a linear track. Further, when the moving body is rotationally displaced, the boundary line is composed of spirals formed on a circular track.

[0013]

According to the present invention, the light receiving elements are appropriately arranged for one of the tracks arranged in parallel to obtain, for example, four chevron signals whose phases are shifted by 90 ° from each other. The four chevron signals are compared with each other to generate four rectangular signals whose phases are shifted by 90 °. It is possible to logically process these four rectangular signals and output three bit signals for one track. Alternatively, it is also possible to take out eight chevron signals whose phases are shifted from each other by 45 °, perform similar comparison processing and logical processing, and output four bit signals per one track. . Also, each chevron signal is modulated in synchronization with the periodic signal transferred from the lower track,
The lower bit signal and the higher bit signal are synchronized. Specifically, the rectangular signal fed back from the comparison operation unit on the upper track side and the periodic signal on the lower track side are logically processed to form a synchronization signal. The synchronization signal and each mountain-shaped signal of the upper track are added at a predetermined ratio to form a modulated mountain-shaped signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic diagram showing a first embodiment of an absolute encoder according to the present invention. This absolute encoder has a moving body in which tracks having light and dark slit patterns are arranged in parallel. (A) is 1
Only the track T of the book is shown. As indicated by the arrow, this track T is displaced in the linear direction. Instead of this, it is also possible to employ a moving body having a track that is rotationally displaced. Corresponding to one track T, four light receiving elements (A
1, A2, A3, A4) are arranged, the illumination light is received through the bright and dark slit patterns, and a detection signal is output for each track. In this example, each of the light receiving elements A1 to A4 has a length dimension in the track direction which corresponds to half of one cycle of the bright and dark slit pattern. Further, the light receiving elements A1, A2, A3, A4
Are arranged with their phases sequentially shifted by 90 °.

(B) represents the time change of the output of the light receiving element, and each of the light receiving elements A1 to A4 outputs a mountain-shaped signal whose phase is shifted by 90 °. Hereinafter, in the present specification, in order to facilitate understanding, the detection signals corresponding to the light receiving elements are represented by the same reference numerals.

(C) represents a processing circuit connected to the light receiving element, which processes the detection signal to generate a bit signal and reads the position of the moving body. As illustrated, the processing circuit includes an input unit 1, a comparison operation unit 2, and a logic operation unit 3.
The input unit 1 inputs a plurality of chevron signals having the same period and different phases by using the detection signal. In this example, the four detection signals A1, A2, A3 and A4 originally having a mountain-shaped waveform are directly input to form a mountain-shaped signal. Therefore, here, reference numerals A1, A2, A3, A corresponding to each chevron signal are also used.
I will attach 4. The comparison calculation unit 2 includes four comparators (C
MP1, CMP2, CMP3, CMP4) are included, and the angle signals A1 to A4 are compared with each other to have a phase of 9
Four rectangular signals shifted by 0 ° are generated. The logical operation unit 3 includes three exclusive OR devices (XOR1, XOR2, XOR
3), one NOR circuit (NOR1) and one NOR circuit (NOT1). The four rectangular signals described above are logically processed with each other to generate three tracks per track T.
The individual bit signals P1, P2 and P3 are output.

Next, the operation of the processing circuit shown in FIG. 1C will be described in detail with reference to FIG. As shown in the figure, the phases of the chevron signals A1, A2, A3 and A4 are sequentially shifted by 90 °. A first rectangular signal (h) is obtained when C1 compares A1 and A4 with each other. Similarly CMP
When A1 and A3 are compared with each other in 2, a second rectangular signal (i) is obtained. A third rectangular signal (j) is obtained by comparing A4 and A3 with CMP3. CMP
A fourth rectangular signal (k) is obtained by comparing A4 and A2 with each other at 4. The phases of the four rectangular signals are sequentially shifted by 90 °. The first intermediate signal (1) is obtained by performing the exclusive OR processing of the first rectangular signal (h) and the second rectangular signal (i) with XOR1. Also, the second intermediate signal (m) is obtained by subjecting the third rectangular signal (j) and the fourth rectangular signal (k) to exclusive OR processing by XOR2. N the first intermediate signal (l) and the second intermediate signal (m)
The first bit signal (lower bit signal) P1 is obtained by performing a NOR operation with OR1. Further, when the second rectangular signal (i) and the fourth rectangular signal (k) are subjected to exclusive OR processing by XOR3, the second bit signal (intermediate bit signal) P2
Is obtained. Finally, if the second rectangular signal (i) is negated by NOT1, the third bit signal (upper bit signal) P3
Is obtained. In this way, it becomes possible to generate three bit signals P1 to P3 from one track T.

FIG. 3 is a block diagram showing a processing circuit included in the second embodiment of the absolute encoder according to the present invention. Basically, it has the same configuration as that of the processing circuit shown in FIG. 1C, and corresponding parts are given corresponding reference numerals to facilitate understanding. The difference is that the modulation processing unit 4 is interposed between the input unit 1 and the comparison operation unit 2, and the lower-order track (one lower than the track T shown in FIG. 1A). 4) in synchronization with the periodic signal (a) transferred from another processing circuit corresponding to
The individual chevron signals A1, A2, A3, A4 are modulated to synchronize the lower bit signal and the upper bit signal (bit signal corresponding to the track T). This modulation processing unit 4 is 2
Negators (NOT2, NOT3), two exclusive ORs (XOR4, XOR5), four multipliers (MPL
1, MPL2, MPL3, MPL4), and four adders (ADD1, ADD2, ADD3, ADD4). The coefficient of the four multipliers is represented by K. The pair of XOR4 and XOR5 constitutes a logic means, and the rectangular signals (i) and (k) fed back from the comparison operation unit 2 are used.
And the periodic signal (a) from the lower track are mutually exclusive ORed to form the synchronization signals (b) and (c). Also NOT2, NOT3, MPL1, MPL2, MP
L3, MPL4, ADD1, ADD2, ADD3, AD
D4 constitutes an adding means, and the synchronizing signal (b),
(C) and the respective chevron signals A1, A2, A3 and A4 are added at a predetermined ratio to obtain four modulated chevron signals (d),
(E), (f), and (g) are formed. These four modulated chevron signals are sequentially processed by the comparison operation unit 2 and the logic operation unit 3, and three bit signals P1, P2, P3 are obtained. These three upper bit signals P1 to P3 are synchronized with the periodic signal (a) transferred from the lower track. On the other hand, the rectangular signal (i) output from the CMP2 included in the comparison operation unit 2 is transferred to the upper track side as another periodic signal. In this way, it is possible to completely synchronize all the tracks in parallel.

FIG. 4 is a timing chart for explaining the operation of the processing circuit shown in FIG. As shown in the figure, the periodic signal (a) transferred from the lower track is a rectangular wave having a predetermined period. On the other hand, four chevron signals A1 and A
2, A3 and A4 all have a cycle that is eight times as long as the cycle signal (a), and their phases are sequentially shifted by 90 °. First, the first synchronization signal (b) is obtained by mutually exclusive ORing the periodic signal (a) and the rectangular signal (k) fed back from the CMP4 by the XOR4. The first synchronization signal (b) has a rising edge or a falling edge synchronized with the rising edge or the falling edge of the periodic signal (a). The rectangular signal (i) fed back from the CMP 2 and the periodic signal (a) are subjected to exclusive OR processing using another XOR 5 to form a second synchronization signal (c).
The second synchronization signal (c) also includes a rising edge and a falling edge synchronized with the periodic signal (a). Next, the first synchronization signal (b) is negated by NOT2 and MPL
When it is 1, the multiplication process is performed K times. This result and Yamagata signal A1
DD1 performs addition processing on each other to form a corresponding modulated chevron signal (d). That is, the synchronization signal and the original chevron signal are added at a predetermined ratio (K) to obtain a modulated chevron signal. This modulated chevron signal (d) is a periodic signal (a)
Includes a step that is synchronized with. Similarly, the second synchronization signal (c) is negated by NOT3 and multiplied by K by MPL2. This result and the original chevron signal A2 are added together by ADD2 to form a corresponding modulated chevron signal (e). The modulated chevron signal (e) also includes a step synchronized with the periodic signal (a). Further, the first synchronizing signal (b) is multiplied by K in MPL3, and then added to the mountain-shaped signal A3 in ADD3 to form a corresponding modulated mountain-shaped signal (f). Further, the second synchronizing signal (c) is multiplied by K in MPL4 and then added to the remaining mountain-shaped signal A4 in ADD4 to form a corresponding modulated mountain-shaped signal (g).

Next, in the comparison operation section 2, the modulated chevron signals (d) and (g) are compared with each other by the CMP 1 and the first rectangular signal (h) is output. The pair of modulated chevron signals (d) and (g) intersect at exactly the stepped portion, and even if some amplitude fluctuation or phase shift occurs, there is no problem in CM
The output of P1 is inverted. Therefore, the rising and falling edges of the rectangular signal (h) are completely synchronized with the periodic signal (a). Similarly, the second rectangular signal (i) is obtained by comparing the pair of modulated chevron signals (d) and (f) with CMP2. As mentioned above, this rectangular signal (i)
Is fed back to the modulation processing unit 4 side. The third rectangular signal (j) is obtained by comparing the pair of modulated chevron signals (g) and (f) with each other in CMP3. The CMP 4 compares the pair of modulated chevron signals (g) and (e) with each other to form a fourth rectangular signal (k). As described above, this fourth rectangular signal (k) is fed back to the modulation processing section 4. Which comparator (CMP1, CMP2, CMP3, C
Even in MP4), they intersect each other at exactly 90 steps.
The phase-modulated or anti-phase modulated chevron signals are compared with each other and synchronized with the periodic signal (a). The four rectangular signals (h) obtained in this way
(K) is logically processed by the logical operation unit 3 as in the embodiment of FIG. 1, and three bit signals P1, P2 and P3 are obtained. The first bit signal P1 has a period twice that of the periodic signal (a), the second bit signal P2 has a period four times that of the periodic signal (a), and
The bit signal P3 has a cycle of 8 times. Each of them consists of a rectangular pulse train synchronized with the rising or falling of the periodic signal (a).

FIG. 5 shows a concrete configuration example of the absolute encoder according to the present invention. Four tracks T0, T1, T2, T are arranged in parallel from the lower order to the upper order.
3 is formed in the moving body, and 9 bit signals from P0 to P8 are obtained. That is, a position resolution having 2 ⁹ addresses can be obtained. As shown in the figure, a set of light receiving elements A1, a set of light receiving elements A2, and a light receiving element A are associated with the lowest track T0.
Three sets are arranged. By using a plurality of light receiving elements (four in this example) for each set, the amount of received light is increased. All of A1, A2 and A3 have a dimension in the track direction corresponding to a quarter of the bright-dark slit pattern period, which is narrower than the example shown in FIG.
Therefore, the detection signals output from A1, A2, and A3 are trapezoidal instead of mountain-shaped. The pair of A1 and the pair of A2 are out of phase with each other by 90 °, and the pair of A1 and the pair of A3 have a phase difference of 18 °.
It is 0 ° off. Three light receiving elements A4, A5, A6 are arranged corresponding to the second lowest track T1. Each of the light receiving elements has a longitudinal dimension in the track direction which corresponds to a quarter of the cycle of the bright and dark slit pattern, and similarly a trapezoidal detection signal is output. The phases of A4 and A5 are shifted by 90 °, and the phases of A4 and A6 are shifted by 180 °. The light-dark slit pattern provided on the next track T2 has a gradual pattern in which the transmittance gradually changes from dark to light along the track direction, and the corresponding light-receiving element A7 has a trapezoidal shape including a slope. A detection signal can be output. In this example, in this gradual pattern, the boundary line that divides the dark portion and the light portion is oblique to the track direction. This boundary line is an oblique straight line formed on the straight track T2. The last track T3 has a bright / dark slit pattern whose phase is shifted by 90 ° with respect to T2.
The corresponding light receiving element A8 is arranged in the same phase as A7.
The cycle of the light-dark slit pattern formed at T2 and T3 is eight times as long as that of the light-dark slit pattern formed at T1. Note that, for ease of illustration, T2 and T3 are displayed in a reduced scale of 1/4 in the track direction.

FIG. 6 shows the light receiving elements A1 and A shown in FIG.
2 shows waveforms of detection signals output from A3. As described above, the detection signals are all trapezoidal waves. The trapezoidal detection signals A1 and A2 are out of phase with each other by 90 °, and A1 and A3 are out of phase with each other by 180 °. By performing a subtraction process between the pair of detection signals A1 and A2, a first chevron signal A1-A2 is obtained, and by performing a subtraction process between A2 and A3, a second chevron signal A2 is obtained.
-A3 is obtained, the third chevron signal A2-A1 is obtained by performing the subtraction process between A2 and A1, and the fourth chevron signal A3-A2 is obtained by performing the subtraction process of A3 and A2. To be These four chevron signals have the same period and the phases are sequentially shifted by 90 °, and correspond to the chevron signals A1, A2, A3, and A4 shown in FIG. Although the mountain-shaped signal is formed by the subtraction processing of the trapezoidal detection signal here, it is generally possible to obtain the mountain-shaped signal by performing an appropriate addition / subtraction processing.

FIG. 7 shows a processing circuit configuration provided corresponding to the track arrangement structure shown in FIG. As shown in the figure, a first stage processing circuit is provided corresponding to the track T0 and outputs three bit signals P0, P1 and P2. Since this processing circuit corresponds to the lowest track T0, there is no need to perform synchronization processing. Therefore, basically, the processing circuit configuration shown in FIG. 1C is adopted, and corresponding parts are given corresponding reference numerals to facilitate understanding. However, for the input unit 1, four subtractors (SB
The difference is that T1, SBT2, SBT3, SBT4) are included. As can be easily understood by referring to FIG.
The SBT1 subtracts the trapezoidal detection signals A1 and A2 and
Mountain-shaped signals A1-A2 are obtained. Similarly, the second chevron signal A2-A3 is obtained by SBT2, the third chevron signal A2-A1 is obtained by SBT3, and the fourth chevron signal A3-A2 is obtained by SBT4. In this way, S
BT1 to SBT4 constitute addition / subtraction means, and 90 °
The trapezoidal detection signals A1, A2 and A3 having the phase difference of 1 are added / subtracted to each other to form first to fourth chevron signals.

A second stage processing circuit is provided corresponding to the second track T2 shown in FIG. This processing circuit is basically the same as the circuit configuration shown in FIG. 3, and includes a modulation processing unit 4 for synchronization. The input unit 1 has a configuration including SBT1 to SBT4 as in the case of the processing circuit of the first stage. The processing circuit of the second stage processes the trapezoidal detection signals A4, A5, A6 and outputs three bit signals P3, P4, P5. The rectangular signal output from CMP2 included in the processing circuit of the first stage is accepted as a periodic signal, and four chevron signals are modulated, and P3 to P5 and P3
0 to P2 are synchronized. That is, since the modulated chevron signal has a step that is synchronized with the periodic signal transferred from the lower track, even if the phase or voltage level of the detection signal changes, if it crosses within the step, a read error will occur. I won't.

A third stage processing circuit is provided corresponding to the pair of tracks T2 and T3 shown in FIG. This processing circuit basically has the same configuration as the processing circuit of the second stage. However, for the input unit 1, the inverter INV
It is different in that it is equipped with. The inverter INV inverts the detection signal A7 to form a reverse phase signal. With this configuration, the detection signals A7 and A8 are processed and three bit signals P6 to P8 are output. Based on the periodic signal transferred from the CMP2 included in the second-stage processing circuit, synchronization processing is performed to synchronize P6 to P8 and P3 to P5. In the uppermost track, the light receiving elements A7 and A8 are
If A is the same as A1 to A6, a light receiving dimension having a length of 1/4 of the bright and dark slit pattern period is required, which is large. Therefore, as shown in FIG. 5, the light-dark slit pattern is made to be a progressive pattern, whereby the light receiving elements A7 and A8 can be downsized and a trapezoidal detection signal can be output. At this time, the edge portion of the trapezoidal waveform is rounded within the range of the length dimension of the light receiving element, but there is no problem as long as it does not reach the step of the modulated chevron signal.

FIG. 8 shows another example of the progressive pattern.
This example is characterized in that the boundary line that divides the bright part and the dark part is composed of two lines oblique to the track direction.

FIG. 9 is a schematic view showing another example of the progressive pattern. In this example, in the progressive pattern, the dark parts and the light parts, which are subdivided along the track direction, are alternately arranged, and the ratio of the dark parts and the light parts changes stepwise. Such a gradual pattern can be applied to a reflective slit as well as a transmissive slit.

FIG. 10 shows another example of the progressive pattern. In this example, the gradual pattern is characterized in that the density continuously changes from dark to light along the track direction.

Each of the progressive patterns shown in FIGS. 8 to 10 is formed on a linear track. On the other hand, FIG. 11 is characterized in that the boundary line that divides the bright portion and the dark portion into two is a spiral formed in a circular track. In order for the waveform of the detection signal to be output to be linear with respect to the movement amount when this spiral portion passes through the light receiving region, it is necessary to satisfy the relationship shown in the following Expression 2. However, R represents a radius, a is a constant, and θ is a rotation angle based on the start point of the spiral winding.

[Equation 2] The proof will be given below with reference to FIG. From FIG. 11, the area ΔS of the shaded portion sandwiched between φ and φ + Δφ is given by the following mathematical formula 3.

[Equation 3] Assuming that the widening dimension of the light receiving region is α, the area S of the transmitted light to the light receiving region can be obtained by integrating Equation 3 above. The result is shown in Equation 4 below.

[Equation 4] Therefore, from the above formula 4, since S is proportional to φ, the waveform becomes linear.

[0030]

As described above, according to the present invention, a plurality of chevron signals having the same period and phase shifts are input using the detection signal output from the light receiving element. A plurality of chevron signals are compared with each other to generate a plurality of rectangular signals whose phases are shifted. A plurality of rectangular signals are logically processed to output at least three bit signals for one track.
Therefore, it is possible to obtain at least one extra bit signal per track as compared with the conventional one, and it is possible to contribute to downsizing and cost reduction of the absolute encoder. Further, the mountain-shaped signal is modulated in synchronization with the periodic signal transferred from the lower track side to synchronize the lower bit signal and the upper bit signal. This allows
It is possible to prevent the reading error between the parallel tracks.

[Brief description of drawings]

FIG. 1 is a slit pattern diagram, a detection signal waveform diagram, and a circuit configuration diagram showing a first embodiment of an absolute encoder according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the absolute encoder according to the first embodiment shown in FIG.

FIG. 3 is a circuit block diagram showing a second embodiment of the absolute encoder according to the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the second embodiment shown in FIG.

FIG. 5 is a track arrangement diagram showing a specific configuration example of an absolute encoder according to the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the specific example shown in FIG.

7 is a block diagram showing a configuration of a processing circuit incorporated in the specific example shown in FIG.

FIG. 8 is a schematic diagram showing an example of a bright-dark slit pattern formed on a track.

FIG. 9 is a schematic diagram showing another example of the slit pattern.

FIG. 10 is a schematic diagram showing another example of the slit pattern.

FIG. 11 is a schematic view showing still another example of the slit pattern.

FIG. 12 is a perspective view showing a conventional absolute encoder.

FIG. 13 is a slit pattern diagram according to a pure binary code.

FIG. 14 is a slit pattern diagram according to the Gray code.

FIG. 15 is a slit pattern diagram according to a binary coded quaternary code.

FIG. 16 is a schematic diagram showing a light receiving area pattern applied to a slit pattern according to a binary coded quaternary code.

[Explanation of symbols]

1 Input section 2 Comparison calculation part 3 Logical operation section 4 Modulation processing unit

Continuation of the front page (56) Reference JP 61-23914 (JP, A) JP 62-278408 (JP, A) JP 52-108155 (JP, A) JP 59-136614 (JP , A) JP-A-63-168504 (JP, A) SAI 54-92751 (JP, U) SEI 1-67519 (JP, U) JP 60-48686 (JP, B1) International publication 93 / 021499 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01D 5/00-5/62 G01B ⁷ /00-7/34 G01P 1/00-3/80

Claims (10)

(57) [Claims] 1. A moving body in which tracks having light and dark slit patterns are arranged in parallel, a light receiving element which receives illumination light through the light and dark slit patterns and outputs a detection signal for each track, and the detection signals are processed. In the absolute encoder including a processing circuit for generating a bit signal to read the position of the moving body, the processing circuit uses the detection signal to input a plurality of mountain-shaped signals that are equi-periodic and out of phase with each other. And a comparison operation unit for comparing the plurality of chevron signals with each other to generate a plurality of rectangular signals out of phase, and at least three bits for one track by logically processing the plurality of rectangular signals with each other. possess a logical operation unit for outputting a signal, further wherein the processing circuit between the input and the comparison operation unit
The modulation processing unit is included in the
In synchronization with the periodic signal transferred from the processing circuit of
Modulates the Yamagata signal and outputs the lower bit signal and the upper bit signal.
Of the rectangular signal fed back from the comparison calculation unit.
And the periodic signal are logically processed together to form a synchronization signal.
Logic means for controlling the synchronization signal and each chevron signal at a predetermined
Adder that performs addition processing to form a modulated chevron signal
An absolute encoder characterized by having steps . 2. The input unit has addition / subtraction means for forming a chevron signal by adding or subtracting trapezoidal detection signals having a phase difference of 90 ° to each other.
Absolute encoder described. 3. The input unit includes inverting means for inverting a detection signal to form a negative phase signal, and generating the plurality of chevron signals by using the detection signal and the negative phase signal. The absolute encoder according to claim 1. 4. The light-dark slit pattern has a gradual pattern in which the transmittance gradually changes from dark to light along the track direction, and enables the slope formation of a chevron signal. The absolute encoder according to claim 1. 5. The progressive pattern has alternating dark and light portions subdivided along the track direction,
The absolute encoder according to claim 4, wherein the ratio of the dark portion and the bright portion is changed stepwise. 6. The absolute encoder according to claim 4 , wherein the gradual pattern has a density that continuously changes from dark to light along the track direction. 7. The absolute encoder according to claim 4 , wherein in the progressive pattern, a boundary line that divides a dark portion and a bright portion is oblique to the track direction. 8. The absolute encoder according to claim 7 , wherein the boundary line is an inclined straight line formed on a straight track. 9. The absolute encoder according to claim 7 , wherein the boundary line is a spiral winding formed in a circular track. 10. The absolute encoder according to claim 9 , wherein the spiral winding is represented by the following mathematical formula. [Equation 1]