JP3487337B2 - Memory inspection method, information storage medium, data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory inspection method for inspecting one common memory shared by a plurality of processor units, a data processing device and a processor unit in which one common memory is shared by a plurality of processor units. The present invention relates to an information storage medium in which programs for executing various processing operations are stored as software.

[0002]

2. Description of the Related Art At present, data processing devices having various structures are used in various fields, for example, there are data processing devices having a plurality of processor units. Further, in such a data processing device, there is also one in which each of the plurality of processor units individually occupies an individual memory, and the plurality of processor units share one common memory.

Such a data processing apparatus can function like a client server system in which a plurality of workstations are connected to a single host computer, and a plurality of processor units are stored in their individual memories. Each program or processing data can perform its own data processing, and a plurality of processor units can share various data via a common memory.

In such a data processing device, for example,
The common memory may be inspected at the time of inspection immediately before shipment or at the time of system maintenance. In that case, the inspection data is written from one of the plurality of processor units to the common memory and then read.

However, in the above-described data processing apparatus, a plurality of processor units generally access the common memory asynchronously without being aware of each other, so that one processor unit is executing the memory test. Then, another processor unit may write data to the common memory.

In this case, since an error occurs in the memory inspection, when executing the memory inspection by one processor unit as described above, the other processor units are forcibly stopped manually.

[0007]

In the data processing apparatus as described above, it is possible to inspect one common memory shared by a plurality of processor units. But,
As described above, when one processor unit executes the memory check, it is necessary to manually stop the other processor units, which complicates the work and hinders the productivity of the data processing device.

In particular, when the processor unit is manually stopped in this way, it is also necessary to manually restore the stopped processor unit after completion of the memory inspection.
For this reason, the work is extremely complicated, and there is a concern that the memory inspection of the data processing device will be terminated while forgetting to restore the processor unit.

For example, when one of the plurality of processor units executes the memory check, it is possible to add a dedicated circuit for forcibly stopping the other processor units. However, this is not preferable because it is necessary to add a dedicated control line or the like to the data processing device, which increases the circuit scale.

The present invention has been made in view of the above problems, and a memory inspection method and a plurality of processors capable of easily and reliably inspecting one common memory shared by a plurality of processor units. A data processing device capable of easily and reliably inspecting one common memory shared by the units, information in which a program for causing the processor unit to execute the processing operation of the memory inspection method of the present invention is stored as software. It is intended to provide at least one of a storage medium.

[0011]

The information storage medium of the present invention stores information in which a plurality of processor units sharing a single common memory having a work area and a management area can read software. A storage medium, the processor unit being connected to the common memory.
The processor unit determines whether the knit is plural or single.
However, there is only one processor unit of its own.
If it is determined that the above, a normal memory inspection is executed and
If the processor unit has a plurality of processor units,
When it is judged, one of the processor units for executing the memory inspection of writing the inspection data in the working area of the common memory and then reading the data is selected, and the one processor unit is written in the management area of the common memory. The write prohibition request is written into the data, and the write inhibit request written in the management area of the common memory is read out to all the processor units which do not execute the memory inspection. Setting the read data write of the processor unit to a prohibited state; causing the processor unit, which has completed the setting of the prohibited state, to write a setting completion notification to the management area of the common memory; The setting completion notification written in the management area is used to execute the memory check. Causing the processor unit to read data, causing the processor unit that has read the setting completion notification to perform memory inspection of the working area of the common memory, and managing the common memory from the processor unit that has completed this memory inspection To write data to the prohibition release request, to cause the processor unit whose data writing is prohibited to read the prohibition release request written to the management area of the common memory, and to read the prohibition release request to data. Also, a program for causing the processor unit to execute the data write prohibition state of the processor unit is stored.

Therefore, when a program stored in the information storage medium of the present invention is read by a plurality of processor units and the corresponding processing operation is executed, the plurality of processor units perform a memory check in a work area of a common memory. One processor unit that executes the above is selected, and the write prohibition request is written into the management area of the common memory from this one processor unit. The write prohibition request written in the management area of the common memory is read out to all the processor units that do not perform the memory inspection, and the data write of the processor unit that has read this write prohibition request is prohibited. Let it set. The setting completion notification written in the management area of the common memory is written from the processor unit in which the setting of the prohibited state is completed, and the setting completion notification written in the management area of the common memory is executed by the processor unit that executes the memory inspection. Read data. The processor unit that has read this setting completion notification data is caused to execute a memory inspection of the working area of the common memory, and the processor unit that has completed this memory inspection data-writes the prohibition release request to the management area of the common memory. The prohibition release request written in the management area of the common memory is read by the processor unit whose data writing is prohibited, and the prohibition request of the processor unit that read the data is released from the data writing prohibited state. . Therefore, when one of the plurality of processor units performs the memory check on the work area of the common memory, the other processor units do not write data to the work area of the common memory from the beginning to the end.

One data processing apparatus according to the present invention comprises a common memory having a work area and a management area,
A data processing device comprising: a plurality of processor units sharing the common memory, wherein a memory test is performed by writing test data in a work area of the common memory and then reading the data. Processor selecting means for selecting one of the processor units; prohibition request writing means for writing a write prohibition request to the management area of the common memory from one processor unit selected by the processor selecting means; A prohibition request reading means for reading out the write prohibition request written in the management area of the common memory to all of the processor units which do not execute the memory inspection, and the data write of the processor unit which has read out the write prohibition request. Prohibition setting means for setting the lock state to the prohibition state, and Setting completion writing means for writing a setting completion notification from the satellite unit to the management area of the common memory, and to the processor unit for executing the memory inspection of the setting completion notification written to the management area of the common memory. Setting completion reading means for reading data, inspection execution means for causing the processor unit that has read the setting completion notification to perform memory inspection, and a prohibition release request from the processor unit that has completed the memory inspection to the management area of the common memory. Release request writing means for writing data, release request reading means for causing the processor unit in the data write prohibited state to read the prohibition release request written in the management area of the common memory, and prohibition release request Of the processor unit that has read the data from the And setting cancellation unit that has provided the said processor unit, first
To the processor unit connected to the common memory.
The processor unit according to whether the unit number is plural or singular.
When it judges that there is only one of its own, normal memory
Performing an inspection and determining that the processor units are plural
If judged, the processor selection means is a single processor.
Select the unit .

Therefore, in the memory inspection method by the data processing device of the present invention, the processor selecting means selects one processor unit for executing the memory inspection in the work area of the common memory. The prohibition request writing means causes the write prohibition request data to be written in the management area of the common memory. The write-prohibition request written in the management area of the common memory is read out by the prohibition request reading means to all the processor units that do not execute the memory inspection. The writing prohibition setting means sets the prohibition state. Then, since the setting completion writing means writes the setting completion notification to the management area of the common memory from the processor unit in which the setting of the prohibited state is completed, the setting completion notification written in the management area of the common memory is written. The setting completion reading means causes the processor unit that executes the memory check to read the data. The inspection execution means causes the processor unit that has read this setting completion notification to execute the memory inspection. Therefore, the release request writing means writes the prohibition release request from the processor unit that has completed the memory inspection to the management area of the common memory. Let The prohibition cancellation request written in the management area of the common memory is read out by the cancellation request reading means to the processor unit whose data writing is prohibited. The setting canceling means cancels the prohibition state of. Therefore, when one of the multiple processor units performs a memory test on the working area of the common memory,
From the beginning to the end, another processor unit does not execute data writing in the work area of the common memory.

In the data processing apparatus as described above, release completion writing means for causing the processor unit that has released the data write prohibition state to write a release completion notification to the management area of the common memory, and the common memory. Release completion reading means for causing the processor unit that executes the memory inspection to read the release completion notification written in the management area of the data, and the end of inspection for ending the memory inspection for the processor unit that has read the release completion notification. It is also possible to have means.

In this case, the release completion writing means writes data to the management area of the common memory from the processor unit that has released the data write prohibition state, and the data is written to the management area of the common memory. The release completion read means causes the processor unit that executes the memory inspection to read the release completion notification. Since the inspection termination means terminates the memory inspection of the processor unit that has read this release completion notification data, when the memory inspection by one processor unit is completed, the data writing of the other processor unit that does not execute the memory inspection is surely performed. Will be returned to.

In the data processing apparatus as described above, it is also possible to provide an inspection control means for sequentially executing the memory inspection one by one in all of the plurality of processor units. In this case, the inspection control means sequentially executes the memory inspection one by one in all of the plurality of processor units, so that the memory inspection is sequentially executed in all the processor units.

Another data processing apparatus of the present invention is a common memory having a work area and a management area,
A data processing device comprising: a plurality of processor units sharing the common memory; and a plurality of individual memories individually occupied by the plurality of processor units, wherein The program of the information storage medium is stored.

Therefore, in the memory inspection method by the data processing device of the present invention, when one of the plurality of processor units executes the memory inspection on the work area of the common memory,
From the beginning to the end, another processor unit does not execute data writing in the work area of the common memory.

The various means referred to in the present invention may be formed so as to realize their functions. For example, dedicated hardware for generating a predetermined function, a processor to which a predetermined function is given by a program. The unit, a predetermined function realized in the processor unit by the program, a combination thereof, and the like are allowed.

The information storage medium referred to in the present invention may be hardware in which a program for causing the processor unit to execute various processes is stored in advance as software, for example, the processor unit is part. A ROM (Read Only Memory) or HDD (Hard Disc Drive) fixed to the device, a CD-ROM or an F that is removably loaded into the device including a processor unit
Allow D, etc.

The processor unit referred to in the present invention may be any device capable of reading a program consisting of software and executing a corresponding processing operation.
Mainly a CPU (Central Processing Unit), a ROM, a RAM (Random Access Memory), an I / F (Int)
erface) and other devices are connected as necessary. Making the processor unit execute various operations corresponding to software in the present invention also allows the processor unit to perform operation control of various devices.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. 1 is a schematic diagram showing a logical structure of a data processing device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a physical structure, and FIG. 3 shows a main routine of a memory inspection method according to the present embodiment. FIG. 4 is a flowchart showing a subroutine of the processor unit that executes the memory inspection, and FIG. 5 is a flowchart showing a subroutine of the processor unit that does not execute the memory inspection.

The data processing apparatus 100 of this embodiment is
As shown in FIGS. 1 and 2, one common memory 20
0, first and second processor units 300 and 400, first and second individual memories 500 and 60 which are information storage media
It has hardware such as 0.

First and second processor units 300, 4
00 is connected to one common memory 200 by dedicated system buses 301 and 401, and is also individually connected to the first and second individual memories 500 and 600 by dedicated system buses 302 and 402.

Therefore, in the data processing apparatus 100 of the present embodiment, one common memory 200 is shared by the first and second processor units 300 and 400, and the first and second individual memories 500 and 600 are shared. Are individually occupied by the first and second processor units 300 and 400.

One common memory 200 is, for example, DR
It is composed of AM (Dynamic Random Access Memory), and has a work area 201 and a management area 202. The work area 201 includes the first and second processor units 30.
The management area 202 temporarily stores processing data shared by the 0, 400, and the management area 202 includes the first and second processor units 30.
It temporarily holds notification data and the like for 0,400 to mutually communicate.

The first and second individual memories 500 and 600 are
For example, it is composed of a flash memory, and software such as a control program for the first and second processor units 300 and 400 is installed in advance, and also temporarily holds setting flags for the operation modes of the processor units 300 and 400.

First and second processor units 300, 4
Reference numeral 00 denotes, for example, a so-called one-chip microcomputer, which executes various processing operations corresponding to a control program installed in the dedicated individual memories 500 and 600, a temporarily stored setting flag, and the like.

As described above, the first and second processor units 300 and 400 execute various processing operations corresponding to the control programs for the memory inspection of the individual memories 500 and 600, whereby the data processing apparatus of the present embodiment is executed. In 100, various means are logically realized as various functions as shown in FIG.

That is, the first processor unit 300
Includes processor selection means 311 and prohibition request writing means 3
12, setting completion reading means 313, inspection execution means 314,
Various units such as the release request writing unit 315, the release completion reading unit 316, the inspection ending unit 317, and the inspection control unit 318 are logically realized as various functions.

On the other hand, in the second processor unit 400, a prohibition request reading means 411, a prohibition setting means 412, a setting completion writing means 413, a cancellation request reading means 414, a setting cancellation means 415, a cancellation completion writing means 416, Various means such as are logically realized as various functions.

In other words, the processor selection means 311 causes the first processor unit 300 to execute a predetermined processing operation in response to the memory inspection program held in the first individual memory 500, thereby causing the common memory 200 to operate.
The first processor unit 300 is selected as one of the processor units 300, 400 that executes the memory inspection in the work area 201.

That is, the data processing device 1 of the present embodiment
00, the two processor units 30 as described above.
The first and second ranks are preset to 0 and 400, and the ranks of these processor units 300 and 400 are described in the individual memories 500 and 600 as data.

Therefore, the processor unit 30 is associated with the memory inspection program for the individual memories 500 and 600.
When 0,400 performs the memory check, the first processor unit 3 is the first to perform the memory check.
A memory inspection program for the individual memories 500 and 600 is described so that 00 is selected.

The prohibition request writing means 312 is selected by the processor selecting means 311 when the first processor unit 300 accesses the common memory 200 corresponding to the memory inspection program of the first individual memory 500. The write prohibition request is written in the management area 202 of the common memory 200 from one processor unit 300.

The prohibition request reading means 411 of the second processor unit 400 is the second processor unit 400.
Accesses the common memory 200 in accordance with the memory inspection program of the second individual memory 600, so that the second processor unit 40 that does not execute the memory inspection for the write inhibit request written in the management area 202.
Let 0 read the data.

More specifically, in the data processing device 100 of the present embodiment, each processor unit 300, 40.
When 0 is the normal state, the management area 202 of the common memory 200
Since the setting data of the second processor unit 400 that does not perform the memory check is periodically read out, the management area 20 of the common memory 200 is used as a regular normal operation.
Data is read from the write inhibit request from 2.

The prohibition setting means 412 causes the second processor unit 400 to set the operation mode setting flag in the second individual memory 600 as data, and when the write prohibition request is read out, the second processor unit 412 is read. 40
Data write of 0 is prohibited.

The setting completion writing unit 413 accesses the common memory 200 by the second processor unit 400 corresponding to the memory inspection program of the second individual memory 600, and the second setting unit 413 completes the setting of the prohibited state. The processor unit 400 causes the setting completion notification to be written in the management area 202 of the common memory 200.

The setting completion reading means 313 of the first processor unit 300 is the first processor unit 300.
Accesses the common memory 200 in accordance with the memory inspection program of the first individual memory 500 to read the setting completion notification written in the management area 202 of the common memory 200 to the first processor unit 300. Let

When the first processor unit 300 data-reads the setting completion notice as described above, the test execution means 314 causes the first processor unit 300 to execute the memory test. Since this memory inspection is executed in the same manner as the conventional one corresponding to the memory inspection program of the first individual memory 500, the work area 20 of the common memory 200 is
1 is executed as an operation of writing the inspection data into the data and then reading the data.

When the memory inspection by the first processor unit 300 is completed, the release request writing means 315 moves from the first processor unit 300 to the common memory 20.
The prohibition cancellation request is written in the management area 202 of 0.

The release request reading means 414 of the second processor unit 400 is the management area 2 of the common memory 200.
02, the second processor unit 400 is caused to read out the prohibition release request written in the data 02, and the setting release means 41
When the prohibition cancel request is read out, the data 5 cancels the prohibition state of data writing of the second processor unit 400.

The release completion writing means 416 causes the release completion notice to be written in the management area 202 of the common memory 200 from the second processor unit 400 that has released the data write prohibition state, and the first processor unit 300. The cancellation completion reading means 316 causes the first processor unit 300 to read the cancellation completion notification written in the management area 202 of the common memory 200.

The inspection terminating means 317 terminates the memory inspection by the first processor unit 300 which has read the release completion notice, and the inspection control means 318 terminates the memory inspection by the first processor unit 300. The same memory inspection is performed by the second processor unit 40.
Start with 0.

More specifically, the two processor units 300 and 400 have the first and second ranks set in advance as described above. 300 executes the memory check, and when this is completed, the second processor unit 400 executes the memory check.

That is, the first and second processor units 3
00 and 400 are formed in the same structure although the order is set, and the memory inspection program of the first and second individual memories 500 and 600 is also a parameter of the order of the first and second processor units 300 and 400. Although the data is set, the description contents of the installed memory inspection program are the same.

The various means as described above are realized by using various kinds of hardware as necessary, but the main body thereof corresponds to the software installed in the individual memories 500 and 600, which are information storage media, and the hardware is used. This is realized by the functions of the first and second processor units 300 and 400 that are wear.

Such software may, for example, sequentially select one of the first and second processor units 300 and 400 to execute a memory check, and select a common memory from one of the selected processor units 300 (400). The write-protection request is written in the management area 202 of the common memory 200.
02, the processor unit 400 (300) which does not execute the memory check is caused to read the write prohibition request, and the processor unit 400 (300) which has read the write prohibition request performs the data write. Setting the prohibition state, causing the second processor unit 400 (300), which has completed the setting of the prohibition state, to write a setting completion notification to the management area 202 of the common memory 200, and managing the common memory 200. Area 202
Causing the processor unit 300 (400) that executes the memory check to read the setting completion notification written in the data, and causing the processor unit 300 (400) that has read the setting completion notification to perform the memory check. , The management area 20 of the common memory 200 from the processor unit 300 (400) that has completed this memory inspection
2 to cause the processor unit 400 (300) that does not execute the memory inspection to read the prohibition cancellation request written in the management area 202 of the common memory 200. The processor unit 400 (30 that read the request data)
0) The data write prohibition state is canceled, and the processor unit 40 that has released the data write prohibition state
0 (300) causes the release completion notice to be written in the management area 202 of the common memory 200 as data, and the release completion notice written in the management area 202 of the common memory 200 performs the memory test.
(400) read the data, terminate the memory inspection by the processor unit 300 (400) that has read the release completion notification, and execute the same memory inspection as the other processor units 4 when the memory inspection is completed.
It is stored in the individual memories 500 and 600 as a memory inspection program for causing the first and second processor units 300 and 400 to execute processing operations such as starting at 00.

In the configuration as described above, first, in the data processing device 100 of this embodiment, the first and second processor units 300 and 400 normally occupy the first and second individual memories 500 and 600, respectively. Therefore, the first and second processor units 300 and 400 individually execute data processing corresponding to the control programs and setting data mounted in the individual memories 500 and 600.

These first and second processor units 30
Since 0 and 400 share one common memory 200, for example, mutual statuses can be notified via the management area 202, and various processing data to be shared can be read into the work area 201. can do.

In the data processing device 100 of the present embodiment, as shown in FIG. 5, the first and second processor units 300 and 400 normally execute various processes as described above (step S2). ), For example, when a memory inspection start request is input as data to the data processing device 100 by a predetermined operation, the first processor unit 3 is correspondingly responded to this.
00 will start the memory inspection (step S
1).

In that case, the first processor unit 30
0 reads out the memory inspection control program from the first individual memory 500, and first determines whether the processor unit existing in the data processing device 100 is plural or single.
(Step S3). That is, the memory inspection program according to the present embodiment is written so as to correspond to both a single processor unit 300 and the like existing in the data processing device 100 and a plurality of processor units 300 and the like. If it is judged that there is only one,
The usual memory inspection as usual is executed (step S4).

On the other hand, when it is determined that there are a plurality of processor units 300 and 400 existing in the data processing device 100 (step S3), the first processor unit 300 itself is the first one to execute the memory check. Is selected (step S5), the processor unit 300,
A dedicated memory inspection corresponding to the plurality of 400 is executed (step S6).

That is, as shown in FIGS. 1 and 4, the first processor unit 300, which has selected itself as one for executing the memory check, issues a write prohibition request to a predetermined address in the management area 202 of the common memory 200. Data is written with a predetermined code such as "55" (step T1). When this data writing is completed, the management area 2 of the common memory 200
It is monitored whether the setting completion notification including a predetermined code such as "CC" can be read out from the predetermined address 02 (step T4).

The management area 20 of the common memory 200
When the setting completion notification cannot be read out even if the predetermined allowable time has passed after the write-protection request was written in 2
(Steps T1 to T4), first processor unit 30
0 determines that an error has occurred and ends the processing operation.

The second processor unit 400 executes the normal processing operation without paying attention to the processing operation of the first processor unit 300 as described above (step E6). Common memory 20
The write data in the management area 202 of 0 is periodically read (steps E1 to E4).

Therefore, when the write prohibition request is read from the management area 202 of the common memory 200 in the regular operation in this normal state (step E4), the second processor unit 400 determines that the work area of the common memory 200 is the same. 201
It is confirmed whether or not it is possible to set the own data writing to the (step E5).

For example, since it is not possible to set the data writing to the prohibited state while other processing is continued, in this case, the state is returned to the state in which other processing is executed (step E6), but if possible, the processing itself. The data writing is set to the prohibited state (step E7).

As described above, the second processor unit 400, which sets the data writing to the work area 201 of the common memory 200 in the prohibited state, writes the setting completion notification to the management area 202 of the common memory 200 (step E
8) Monitor whether the prohibition cancellation request can be read out of data from this management area 202 for a predetermined time (step E9-).
E12).

The first processor unit 300 monitors whether or not the setting completion notification can be read out from the management area 202 of the common memory 200 after writing the write-inhibit request as described above (step T1). (Step T4), if the setting completion notification cannot be read out in data even after the lapse of a predetermined allowable time, it is determined that an error has occurred (Steps T2 and T3).

On the other hand, when the setting completion notice written by the second processor unit 400 as described above is read out (step T4), the inspection data is written in the work area 201 of the common memory 200, and then the data is written. A memory check to be read is executed (steps T5 to T7).

At this time, the second processor unit 40
0 indicates that the data writing to the work area 201 of the common memory 200 is prohibited (step E7).
No error occurs in the memory check of 00.

Then, the first processor unit 300 which has completed the memory inspection (step T7), the common memory 2
00 is written in a predetermined address of the management area 202 of 00 with a predetermined code such as “AA” (step T8), and when this data writing is completed, the common memory 200
It is monitored up to a permissible time whether or not a cancellation completion notification of a predetermined code such as "C4" can be read from a predetermined address of the management area 202 of the above (steps T9 to T11).

On the other hand, the second processor unit 400
After writing the setting completion notification as described above,
(Step E7), management area 202 of common memory 200
Since it is monitored whether or not the prohibition cancellation request can be read out from the data (steps E9 to E12), when the data is read out, the setting of the prohibition state of the own data writing is canceled (steps E10 and E13).

The second processor unit 400
Even if the prohibition cancellation request is not read out, the setting of the prohibition state of its own data writing is canceled when a predetermined allowable time elapses (steps E12 and E13). In this way, the second processor unit 400 that has restored the data writing to the work area 201 of the common memory 200 to the normal state after data writing the cancellation completion notification to the management area 202 of the common memory 200. Return (Step E1)
4).

As described above, the first processor unit 300 can write the prohibition cancellation request in the management area 202 of the common memory 200 (step T8), and then read the cancellation completion notification from the management area 202. Since it is being monitored (steps T9 to T11), when the release completion notice is read out, the normal state is restored.

However, the data processing apparatus 1 of the present embodiment
In 00, as shown in FIG. 3, the memory inspection is executed in all of the plurality of processor units 300 and 400.
(Steps S5 to 7) When the memory inspection in the first processor unit 300 is completed as described above, the memory inspection in the second processor unit 400 is similarly executed.

The data processing apparatus 100 of this embodiment is
As described above, in the structure in which one common memory 200 is shared by a plurality of processor units 300 and 400, the work area 201 of one common memory 200 can be sequentially inspected by the plurality of processor units 300 and 400. it can.

In that case, the first and second processor units 300, 400 are provided in the work area 201 of the common memory 200.
When one executes the memory check, the other processor units 300 and 400 do not write data to the work area 201 of the common memory 200 from the beginning to the end, so that the memory check should be executed without error. You can

In addition, since the data write prohibition setting of the processor units 300 and 400 which does not execute the memory inspection is automatically executed, the complicated operation of manually setting this is not necessary, and the processor units 300 and 400 are not required to be manually set. The memory test is not terminated without forgetting to recover.

Furthermore, a plurality of processor units 30
One of the memory checks of 0,400 does not execute the memory check, and the other requests the setting of prohibition of its own data writing via the management area 202 of the common memory 200.
It is not necessary to add a circuit or the like to the data processing device 100 to forcibly stop the operation of the processor units 300 and 400 from the outside.

Further, the processor units 300, 400, which have been requested to set prohibition of data writing, set the data writing by themselves while confirming their own states. Will not be forcibly stopped from the outside and an error will not occur.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are allowed without departing from the gist thereof. For example, in the above embodiment, the processor unit 30
Although it is illustrated that the number of 0,400 is two, the number of three or more is also possible.

Further, in the above embodiment, the individual memories 500, 6
00 according to the memory inspection program stored as software in the first and second processor units 30
By operating 0,400, the data processing device 10
It has been illustrated that various means are logically realized as various functions of 0. However, each of these various means can be formed as unique hardware, and a part of them can be stored as software in the individual memories 500 and 600 and a part of them can be formed as hardware. .

[0077]

Since the present invention is constructed as described above, it has the following effects.

When a program stored in the information storage medium of the present invention is read by a plurality of processor units and the corresponding processing operation is executed, the plurality of processor units execute a memory check in the work area of the common memory. One processor unit to be written is selected, and the write prohibition request is written in the management area of the common memory from this one processor unit. The write inhibit request written in the management area of the common memory is read out by all the processor units that do not execute the memory inspection.
This writing prohibition request is set to the data writing prohibition state of the processor unit that has read the data, and the setting completion notice is written to the management area of the common memory from the processor unit that has completed the setting of the prohibition state. The setting completion notification written in the management area of the memory is read by the processor unit that executes the memory check, and the setting completion notification is caused by the processor unit that reads the data to execute the memory check of the working area of the common memory. The processor unit that has completed the memory inspection writes data to the prohibition release request in the management area of the common memory, and the prohibition release request written in the management area of this common memory is written to the processor unit in which the data writing is in the disabled state. The processor unit that has been read and has read this prohibition cancellation request data By releasing the data write prohibition state, when one of the multiple processor units executes the memory check on the work area of the common memory, other processor units write data to the work area of the common memory from the beginning to the end. Since the integration is not executed, the work area of the common memory can be inspected by one of the plurality of processor units without error.

In the memory inspection method by the data processing device of the present invention, the processor selecting means selects one processor unit for executing the memory inspection in the work area of the common memory. Therefore, the common memory is selected from the selected one processor unit. The prohibition request writing means causes the write prohibition request data to be written in the management area of the common memory, and the write prohibition request written in the management area of the common memory is read out to all processor units that do not execute the memory inspection. Since the means causes the data to be read out, the write prohibition request sets the data write prohibition means of the processor unit that has read the data to the prohibition state, and the processor unit in which the prohibition state has been set is transferred to the management area of the common memory. Since the setting completion writing means causes the setting completion writing means to write data, this common memory management Since the setting completion reading means causes the processor unit that executes the memory inspection to read the setting completion notification written in the area data, and the processor unit that has read the setting completion notification causes the inspection executing means to execute the memory inspection. The release request writing means causes the release request writing means to write data from the processor unit that has completed this memory inspection to the management area of the common memory, and the release request writing data is written to the management area of this common memory. Since the release request read means causes the processor unit in the prohibited state to read the data, the setting release means releases the data write prohibited state of the processor unit that has read this prohibition release request. When performing a memory check on the common memory work area, first Since Luo end until the other processor unit does not execute the data write in the work area of the common memory can be no error checking the working area of the common memory in one of a plurality of processor units.

Further, in the above-described data processing device, the release completion writing means causes the release completion writing means to write data to the management area of the common memory from the processor unit that has released the data write prohibition state, and The release completion notice written in the management area is made to be read by the release completion reading means to the processor unit which executes the memory inspection, and the inspection end means finishes the memory inspection of the processor unit which read the release completion data. Thus, when the memory inspection by one processor unit is completed, it is possible to reliably restore the data writing of the other processor unit that does not execute the memory inspection.

Further, the inspection control means causes the memory inspection to be executed one by one in all of the plurality of processor units, whereby the memory inspection can be sequentially executed in all the processor units.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a logical structure of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a physical structure.

FIG. 3 is a flowchart showing a main routine of the memory inspection method of the present embodiment.

FIG. 4 is a flowchart showing a subroutine of a processor unit that executes a memory check.

FIG. 5 is a flowchart showing a subroutine of a processor unit that does not execute a memory check.

[Explanation of symbols]

100 data processor 200 common memory 201 work area 202 management area 300,400 processor unit 311 processor selection means 312 Prohibition request writing means 313 Setting completion reading means 314 Inspection execution means 315 Release request writing means 316 Release completion reading means 317 Inspection ending means 318 Inspection control means 411 Prohibition request reading means 412 Prohibition setting means 413 setting completion writing means 414 Release request reading means 415 Setting cancellation means 416 Release completion writing means 500,600 Individual memory

Claims (8)

(57) [Claims] 1. A memory inspection method for inspecting a single common memory, which comprises a work area and a management area and is shared by a plurality of processor units, the processor unit being connected to the common memory.
The processor unit determines whether there is a plurality or a single number, and the processor unit has only one
If so, a normal memory check is performed and the processor unit is
If the number is judged to be a number, one of the processor units for executing the memory inspection of writing the inspection data into the work area of the common memory and then reading the data is selected, and the management of the common memory is performed from the one processor unit. The write prohibition request is written in the area, and the write prohibition request written in the management area of the common memory is read out to all the processor units that do not execute the memory inspection. The data writing of the processor unit that has read the data is set to the prohibited state, and the setting completion notice is written to the management area of the common memory from the processor unit that has completed the setting of the prohibited state. The setting completion notification written in the area is sent to the processor unit that executes the memory check. The processor unit that has read the setting completion notification to perform a memory inspection of the work area of the common memory, and the processor unit that has completed the memory inspection sends a prohibition release request to the management area of the common memory. Data is written into the management area of the common memory, and the prohibition release request written in the management area of the common memory is read out by the processor unit whose data writing is in the prohibition state. A memory inspection method that cancels the write-protected state. 2. An information storage medium storing software readable by a plurality of processor units sharing a single common memory having a work area and a management area, the information storage medium being connected to the common memory. The processor unit
Whether there is only one processor unit, if there is only one processor unit
If it is determined that a normal memory test is to be executed , and if it is determined that there are a plurality of processor units, one of the processor units that performs a memory test of writing test data in the work area of the common memory and then reading the data is read. Selecting the write inhibit request from this one processor unit to write data to the management area of the common memory, and executing a memory check on the write inhibit request written to the management area of the common memory. Not setting all of the processor units to read the data, setting the write prohibition request to the data writing of the processor unit that has read the data, and setting the prohibition state to the common state from the processor unit. Data writing of setting completion notification in the management area of the memory, A setting completion notice written in the management area of the common memory of the common memory is read by the processor unit that executes the memory check; Performing an inspection, causing the processor unit that has completed the memory inspection to write a prohibition release request to the management area of the common memory, and writing the prohibition release request to the management area of the common memory. A program is stored for causing the processor unit to execute the data reading by the processor unit in the write prohibited state, and release the data write prohibited state of the processor unit that has read the data from the prohibition release request. Information storage medium characterized by being . 3. A data processing apparatus comprising: one common memory having a work area and a management area; and a plurality of processor units sharing the common memory, Processor selection means for selecting one of the processor units for executing the memory inspection of writing inspection data in the work area of the memory and then reading the data, and one processor unit selected by the processor selection means for the common A prohibition request writing means for writing a write prohibition request to the management area of the memory, and a write prohibition request written to the management area of the common memory is written to all of the processor units that do not execute a memory check. Read prohibition request read means, and data of the processor unit that has read the write prohibition request data Prohibition setting means for setting the lock state to a prohibition state, setting completion writing means for writing a setting completion notice to the management area of the common memory from the processor unit which has completed the setting of the prohibition state, and management of the common memory Setting completion reading means for causing the processor unit that executes the memory inspection to read the setting completion notification written in the area data, and inspection executing means for causing the processor unit that has read the setting completion notification to perform the memory inspection. Release request writing means for writing the prohibition release request to the management area of the common memory from the processor unit which has completed the memory inspection, and data writing the prohibition release request written to the management area of the common memory. And a release request reading means for causing the processor unit in the prohibited state to read data, Setting canceling means for canceling the data write prohibition state of the processor unit that has read the cancel request data,
And comprising, said processor unit, first contact to the common memory
The processor unit being continued is whether more or singular
Judge that only one processor unit exists
If you decide not to do so, a normal memory inspection is executed and
If it is determined that there are multiple processor units, the processor
Server selecting means selects one of the processor units.
That the data processing device. 4. A release completion writing unit for writing a release completion notification to the management area of the common memory from the processor unit that has released the data write prohibition state, and data writing to the management area of the common memory. Also provided are release completion reading means for causing the processor unit that executes the memory inspection to read the released release completion notification, and inspection ending means for ending the memory inspection by the processor unit that has read the release completion notification. The data processing device according to claim 3, 5. The data processing apparatus according to claim 3, further comprising an inspection control unit that sequentially executes a memory inspection for each of the plurality of processor units. 6. The plurality of processor units are ranked in order.
It is preset and the processor units sequentially
The data processing device according to claim 5, which executes a memory test. 7. A plurality of processor units are provided.
An individual memory is individually occupied, and the order is described in the individual memory as data.
Item 6. The data processing device according to item 6. 8. A single common memory having a work area and a management area, a plurality of processor units sharing the common memory, and a plurality of processor units individually occupied by the plurality of processor units. A data processing device comprising an individual memory, wherein the program of the information storage medium of the invention according to claim 2 is stored in the individual memory.