JP3482897B2 - Cluster-type parallel computer system and inter-processor barrier synchronization method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cluster-type parallel computer system including nodes having a plurality of processors, and more particularly to inter-processor barrier synchronization which spans nodes and in which a plurality of processors in the node participate.

[0002]

2. Description of the Related Art An example of a conventional interprocessor barrier synchronization method is described in Japanese Patent Laid-Open No. 7-234841. Less than,
The conventional technique will be described with reference to the publication.

In a parallel computer system, a synchronization mechanism is indispensable for advancing processing together while confirming that each element processor has completed certain processing. In order to meet this demand, a method known as barrier synchronization is known, in which all processors to be synchronized reach the next stage only after it is guaranteed that they have reached a certain stage called the program barrier. There is.

In the "parallel processing computer" described in the above publication, a barrier synchronization control device connected to an inter-node connection network
14 (shown in FIG. 7), and as shown in FIG.
A synchronization control unit 32 is included therein. Barrier synchronization controller 14
Has an AND gate 60 and a group phase register 58 for inputting the barrier synchronization confirmation signal 52 from the synchronization control unit 32 of each node P. Further, the synchronization control unit 32 of each node P, as shown in FIG. 9, has a processor phase register 61 and a group phase register 58 in the barrier synchronization control device 14.
Judgment circuit to which the group phase signal 56 from
I have 62.

In the initial state, the processor phase register 60 of each node P is "0", and the barrier synchronization control device 1
The state of the group phase register 58 of 4 is set to "1". In performing the synchronization, in each node P participating in the synchronization, when the program reaches the barrier, the instruction execution mechanism 30 inverts the bit of the processor phase register 61 to "1". When bit inversion occurs, the match determination circuit 6
As a result of 2, the comparison result between the values of the group phase register 58 and the processor phase register 61 becomes "true", and the result is sent to the AND gate 60 in the barrier synchronization control device 14. When all the signals from the participating nodes P become “true”, the output of the AND gate 60 becomes “true”, the barrier establishment signal 54 becomes “true”, and the signal is distributed to each node P and the barrier synchronization is established. .

At the same time, the barrier synchronization controller 14 inverts the bit of the group phase register 58 to "0". The inverted bit is sent to the synchronization control unit 32 of each node P,
The match determination circuit 60 detects a mismatch with the value of the processor phase register 61 that is already "1" this time, sends "false" to the barrier synchronization control device 32, and enters the next barrier synchronization wait state. .

Since the AND gate 64 in FIG. 9 is not directly related to the present invention, its explanation is omitted and the output of the coincidence determination circuit 62 is used as it is as the output of the AND gate 64.

[0008]

However, in the above-mentioned conventional technique, when there are a plurality of processors participating in a barrier in a node, barrier synchronization needs to be layered within a node and between nodes. However, there is a problem that processing becomes complicated. The reason is that when each participating processor updates the processor phase register 60, bit inversion occurs multiple times and the barrier synchronization breaks down, or the barrier synchronization between nodes is determined only by the state of the processor that first inverted the bit. This is because it will be established and will either fail.

Therefore, an object of the present invention is to provide a cluster type parallel computer system and an interprocessor barrier synchronization method which can speed up interprocessor synchronization across clusters without hierarchizing.

[0010]

A cluster type parallel computer system of the present invention is a cluster type parallel computer system in which nodes having one or more processors are connected to each other by an internode network. In the barrier synchronization means, a means for storing the number of in-node processors participating in the barrier synchronization and a value of the storage means are copied as initial values, one for each barrier synchronization request from each processor participating in the barrier synchronization. a counting means to be subtracted, and means for said count value to issue a barrier synchronization establishment notification to the node as it becomes 0, and means for again performing the copy at the same time, the
One barrier synchronization unit is provided for each barrier , and each processor in the node confirms that the assigned bit of the state register assigned to each barrier on the node is inverted by this barrier synchronization establishment notification. It is characterized in that the establishment of barrier synchronization is detected by doing so.

The inter-processor barrier synchronization method of the present invention is an inter-processor barrier synchronization method in a cluster type parallel computer system in which nodes having one or more processors are connected by an inter-node network.
1 tsuzuic the number of processors to participate in the barrier synchronization on each barrier
One as an initial value, a procedure for setting the initial value in counting means provided for each barrier, and a value of the counting means is set to 1 in accordance with a synchronization request from a processor participating in the barrier synchronization. Subtraction procedure,
A procedure for detecting the establishment of barrier synchronization when the value of the counting means becomes 0, and notifying a node including one or more processors participating in the barrier synchronization of the establishment of barrier synchronization and counting the initial value. Set to means
And instructions, a processor to participate in the barrier synchronization has a read-free procedure the value of the status register in the node, and a procedure for updating the value of the status register by the barrier synchronization establishment notification, the processor the state Characterized by detecting that barrier synchronization is established by updating the register

In the present invention, the portion corresponding to the processor phase register 61 in FIG. 9 is not updated by each processor in the node, and the portion corresponding to the barrier synchronization control device 14 in FIG. The feature is that it was updated in. That is, the barrier synchronization request is directly sent from each processor to the barrier synchronization control device, and the synchronization is determined here, and the value on the node is changed. Therefore, there are multiple processors participating in the barrier synchronization in the node. Even if it is, the effect that the barrier synchronization can be correctly determined can be obtained.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, there is shown an embodiment of the cluster type parallel computer system of the present invention.

In FIG. 1, one or more barrier synchronization devices 1 exist in the system, and one or more barrier synchronization management units.
10, a communication device 31 for receiving a barrier synchronization request 40 from the inter-node network 3 and notifying the establishment of synchronization, and a barrier synchronization management unit 10 corresponding to the barrier synchronization request 40 are identified, and a message ID selection unit 15
Have and. Further, each barrier synchronization management unit 10 includes a counter 11 for barrier synchronization and a register for holding its initial value.
12, a barrier synchronization establishment determination unit 13, and a subtractor 16,
Barrier synchronization request 40 from each processor 21 on each node 2
Accordingly, the establishment of barrier synchronization is determined, and the synchronization notification 41 is performed via the communication device 31.

The node 2 is a constituent element of the cluster parallel computer system, and is a computing computer having one or more processors 21. Each node 2 has a state register 22 and a barrier synchronizer 1 for obtaining the state of barrier synchronization.
It includes a communication device 23 for communicating with.

Next, the operation of interprocessor synchronization in the cluster type parallel computer system of FIG. 1 will be described with reference to FIG.

Prior to the barrier synchronization, each processor 21 participating in the barrier synchronization is a processor participating in the barrier synchronization.
21 synchronization groups are determined (step S200), and node 2
A group configuration is given to the above OS, and a request is made to allocate one of the barrier synchronization management units 10 (step S201).

The OS that has received the request arbitrates with the OS of the other node 2 and secures the free space in the barrier synchronization management unit 10 (step S210). Next, the OS gives a barrier synchronization ID (step S211) and notifies the barrier synchronization device 1 of the number of processors in the group and the barrier synchronization ID (step S212). Finally, the OS maps the vacant 1 bit of the status register 22 to the barrier synchronization ID, and notifies each processor 21 of the barrier synchronization group of the assigned barrier synchronization ID and the bit position of the status register 22 ( Step S213).

When the barrier synchronization device 1 receives a notification from the OS while waiting for a request (step S220) (step S212),
The vacant barrier synchronization management unit 10 is mapped to the notified barrier synchronization ID (step S221), and an initial value is passed to the mapped barrier synchronization management unit 10 to request initialization (step S222).

When the barrier synchronization management unit 10 mapped in step S221 receives the initialization request while waiting for the request (step S230), it sets the value passed to the register 12 (step S231). The barrier synchronization management unit 10 uses the register 12
When the initial value is set to, the value is copied to the counter 11 (step S232) and the barrier synchronization completion notification waits (step S230). At this time, the barrier synchronization management unit 10 must be uniquely determined among the clusters.
Which of 22 bits and the assigned barrier synchronization management unit 10
Whether and are mapped may be different for each node 2.

Each processor 21 performs calculation processing (step S20
When step 2) progresses and reaches the synchronization point (step S203), the state register 22 assigned at the start of barrier synchronization
The value is read from the bit position of (step S204).
Next, the processor 21 transmits the message of the barrier synchronization request 40 to the barrier synchronization device 1 through the communication device 23 (step S205).

In the barrier synchronization device 1, when the barrier synchronization request 40 message transmitted from each processor 21 in step S205 arrives while waiting for the request (step S220), the ID selection unit 15 responds to the request by the barrier synchronization management unit. Select 10 (step S223), and pass the message of barrier synchronization request 40 (step S222).

In the barrier synchronization management unit 10, when the message of the barrier synchronization request 40 is passed while waiting for the request (step S230), the subtractor 16 subtracts 1 from the value of the counter 11 (step S233). Then, when the result value becomes 0, it means that the barrier synchronization request message has arrived from all the processors 21 participating in the barrier synchronization, so that the barrier synchronization is established. If it is not 0, the state of waiting for a message is resumed (step S230) (step S234).

When the barrier synchronization is established, the barrier synchronization management unit 10 issues a barrier synchronization completion notice 41 to each node 2 (step S235). At the same time that the barrier synchronization completion notification 41 is issued, the barrier synchronization management unit 10 copies the value of the register 12 to the counter 11 again (step S232) and waits for a barrier synchronization request (step S230). The barrier synchronization synchronization completion notification 41 is received by the communication device 23 on each node 2 and inverts the bit of the status register 22 mapped to the barrier synchronization ID.

The processor 21 that has issued the message 40 of the barrier synchronization request 40 (S205) reads the assigned bit position of the status register 22 as appropriate, but in step S235.
The status register bit inversion by
When a value different from the value read in S204 is read, the establishment of barrier synchronization is detected (steps S206 and S207).

As described above, in the above embodiment, since the status register 22 for barrier synchronization is updated only by the barrier synchronization completion notification 41 from the barrier synchronization apparatus 1, each participating processor 21 in the node directly communicates with it. Barrier synchronization request to
By issuing 40 and directly referring to the status register 22, each processor 21 can independently detect the completion of barrier synchronization. Therefore, it is not necessary to make barrier synchronization hierarchical, and each processor 21 can perform barrier synchronization in the same procedure.

Next, a second embodiment of the cluster computer system of the present invention will be described. This embodiment has the same basic configuration as that of the first embodiment, but does not use hardware such as the barrier synchronizer 1 and realizes equivalent functions only by software as shown in FIG. .

The barrier synchronization management node 5 is a barrier synchronization ID.
Barrier synchronization counter 51 and register 52 identified by
And a communication establishment 23 for communicating with another node 2 via the inter-node network 3 having one or more barrier synchronization management processes 50 each comprising a synchronization establishment determining unit 53. The barrier synchronization management node 5 may exist in any number in the system.

Each node 2 is a computer for computation consisting of one or more processors 21, a communication device 23 for communicating with another node 2 via the inter-node network 3, and a communication device 23 generated for each barrier synchronization ID. With a barrier state variable of 25.
The barrier communication device 23 has a function of performing DMA to a memory on another node.

Next, the operation of the embodiment of FIG. 3 will be described with reference to the flowchart of FIG. Prior to the barrier synchronization, each processor 21 participating in the barrier synchronization determines a group of processors 21 participating in the barrier synchronization (step T200), and sets one barrier state variable 25 to the node 2 in which the participating processor 21 exists. Generate and initialize with 0 (step T20
1). Then, it notifies the barrier synchronization management node 5 together with the group configuration and requests that the barrier synchronization management process 50 be allocated (step T202).

In the barrier synchronization management node 5, the ID identification unit 55 waiting for synchronization (step T220) receives this request, issues a new barrier synchronization ID, creates a barrier synchronization management process 50, and uses it for barrier synchronization. The ID is notified to each processor 21 (step T221).

When the barrier synchronization management process 50 is generated, it sets the value given to the internal register 52, copies it to the internal counter 51 as well, and further sets the state variable.
57 is initialized to 0, which is the same as the barrier state variable 25 of each node 2 (step T230), and waits for a request (step T231).

Each processor 21 performs calculation processing (step T2
When (03) advances and reaches the synchronization point (step T204), the value of the barrier state variable 25 is read out when starting the barrier synchronization (step T205). Next, the processor 21 is a communication device.
The barrier synchronization request message 40 is transmitted to the barrier synchronization management node 5 through 23 (step T206).

In the barrier synchronization management node 5, the ID identification section 55
When the message of the barrier synchronization request 40 transmitted from each processor 21 in step T206 arrives while waiting for the request (step T220), the barrier synchronization management process corresponding to the request
Select 50 (step T222) and pass the barrier synchronization request 40 message to it (step T223).

In the barrier synchronization management process 50, when the message of the barrier synchronization request 40 is passed while waiting for the request (step T231), the value of the counter 51 is decremented by -1 (step T23).
3). If the result value becomes 0, it means that the messages have arrived at the barrier synchronization management process 50 from all the processors 21 participating in the barrier synchronization, so that the barrier synchronization is established. If it is not 0, the message waiting state (step T231) is entered again (step T234).

When the barrier synchronization is established, the barrier synchronization management process 50 increments the value of the state variable 57 by 1, and notifies the barrier state variable 25 on each node 2 of the value of the barrier synchronization completion synchronization notification 41. As a result, writing is performed using the DMA function of the communication device 23 (step T235). Also, the barrier synchronization management process 50 issues a barrier synchronization completion notification 41 (step T2
At the same time, the value of the register 52 is copied again to the counter 51 (step T232), and the state of waiting for a barrier synchronization request (step T230) is entered.

In step T206, a barrier synchronization request message
The processor 21 that issued 40 has properly read the value of the barrier state variable 25, but when a value different from the value read in step T204 is read as a result of writing the synchronization state variable 25 in step T235. Then, the establishment of barrier synchronization is detected (steps T207 and T208).

As described above, in the above-described embodiment, the barrier synchronization management process is performed except the initialization of the update of the barrier state variable 25.
Since only the barrier synchronization completion synchronization notification 41 from 50 is issued, each participating processor 21 in the node 2 directly issues a barrier synchronization request 40 to each and directly references the barrier state variable 25, The processor 21 can independently detect the completion of barrier synchronization. Therefore, it is not necessary to make barrier synchronization hierarchical, and each processor 21 can perform barrier synchronization in the same procedure.

Next, as a third embodiment of the present invention, an example in which the cluster system has an atomic operation function for the memory of another node is shown in FIG. This embodiment has the same configuration as the second embodiment, but since the system has an atomic operation function for the memory of another node, the synchronization management process 50 does not need to have the state variable 57. There is.

This is because it is not necessary to store the state before the change in order to change the value of the barrier state variable 25 on each node 2 participating in the synchronization. Because
This is because the atomic operation function can be used to change the value of the barrier state variable 25 on each node 2 by +1 without knowing the original value.

The process flow of the third embodiment is shown in FIG.
Prior to the barrier synchronization, each processor 21 participating in the barrier synchronization determines a group of the processors 21 participating in the barrier synchronization (step U200) and sets one barrier state variable 25 to the node 2 in which the participating processor 21 exists. It is generated (step U201), notified to the barrier synchronization management node 5 together with the group configuration, and requested to allocate the barrier synchronization management process 50 (step U202).

The barrier synchronization management node 5 receives a request from the ID identification unit 55 waiting for synchronization (step U220), issues a new barrier synchronization ID, creates the barrier synchronization management process 50, and outputs the barrier synchronization ID. Notify each processor 21 (step U221).

When the barrier synchronization management process 50 is generated, it sets the internal register 52 to the given initial value, copies it to the internal counter 51 as well, and further sets the state variable 57 of each node 2. It is initialized to 0, which is the same as the barrier state variable 25 (step U230), and waits for a request (step U231).

Each processor 21 performs calculation processing (step U20
3) proceeds to reach the synchronization point (step U204), the barrier synchronization variable is read from the value of the barrier state variable 25 at the start of the barrier synchronization (step U205), and a barrier synchronization request node 40 message is sent to the barrier synchronization management node 5 through the communication device 23. Send (step U206).

In the barrier synchronization management node 5, the ID management unit 55
When the message of the barrier synchronization request 40 transmitted from each processor 21 in step U205 arrives while waiting for the request (step U220), the barrier synchronization management process corresponding to the request
Select 50 (Step U222), Barrier synchronization request message
Pass 40 (step U223).

In the barrier synchronization management process 50, when the message of the barrier synchronization request 40 is passed while waiting for the request (step U230), the value of the counter 51 is decremented by -1 (step U23).
3). If the result value becomes 0, it means that the messages have arrived at the barrier synchronization management process 50 from all the processors 21 participating in the barrier synchronization, so that the barrier synchronization is established. If it is not 0, the state of waiting for a message is resumed (step U230) (step U234).

When the barrier synchronization is established, the barrier synchronization management process 50 uses the atomic operation function for the other nodes of the system to set the barrier state variable 25 on each node 2.
+1 is added to the barrier synchronization completion notification 41. The barrier synchronization management process 50 issues the barrier synchronization completion notification 41 (step U235) and simultaneously counts the value of the register 52.
It is copied again to 51 (step U232), and the state becomes the waiting state for barrier synchronization request (step U230).

The processor 21 that issued the barrier synchronization request message 40 reads the value of the barrier state variable 25 as appropriate, but the value read in step U204 depends on the result of writing the synchronization state variable 25 by the atomic function described above. When a value different from is read, the establishment of barrier synchronization is detected (steps U207 and U208).

As described above, in the above embodiment, the barrier synchronization management process is performed except for the initialization of the update of the barrier state variable 25.
Since it is performed only by the barrier synchronization completion notification 41 from 50, each participating processor 21 in the node directly issues a barrier synchronization request 40 to each and directly refers to the barrier state variable 25, so that each processor 21 Can independently detect the completion of barrier synchronization.

At this time, the synchronization state variable 25 of each node 2 does not necessarily have to be initialized to the same value.
Since the state (value) at that point is incremented by 1 by the barrier synchronization management process 50 by the atomic operation, the value immediately before the start of barrier synchronization is stored each time (step U205), and the value and the value of the barrier state variable 25 are stored. It suffices to compare (step U207). Therefore, it is not necessary to make barrier synchronization hierarchical, and each processor 21 can perform barrier synchronization in the same procedure.

The inter-processor barrier synchronization method described above may be programmed and recorded in a recording medium such as a semiconductor memory or a magnetic disk, and read by a computer and executed.

[0053]

As described above, in the present invention, the value indicating the state of barrier synchronization is updated only from the part that manages the synchronization state, so that barrier synchronization across clusters is not hierarchized. It has the effect that it can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a cluster parallel computer system of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment of FIG.

FIG. 3 is a block diagram showing a second embodiment of the cluster parallel computer system of the present invention.

FIG. 4 is a flowchart showing the operation of the second embodiment of FIG.

FIG. 5 is a block diagram showing a third embodiment of the cluster parallel computer system of the present invention.

6 is a flowchart showing the operation of the third embodiment of FIG.

FIG. 7 is a block diagram of a barrier synchronization control device in a conventional parallel processing computer.

FIG. 8 is a block diagram of a node in a conventional parallel processing computer.

FIG. 9 is a block diagram of a synchronization control unit in a conventional parallel processing computer.

[Explanation of symbols]

1 Barrier synchronizer 2 nodes Three-node network 5 Barrier synchronization management node 10 Barrier synchronization management unit 11 counter 12 registers 13 Synchronization establishment determination unit 15 ID selection section 16 subtractor 21 CPU (processor) 22 Status register 23 Communication equipment 25 Barrier state variables 26 Atomic calculator 29 Disk unit 31 Communication equipment 40 Barrier synchronization request 41 Barrier synchronization completion notification 42 Initial value setting 50 Barrier synchronization management process 51 counter 52 registers 53 Synchronization establishment determination unit 55 ID identifier 57 state variables 58 CPU 59 Disk unit

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References Japanese Patent Laid-Open No. 6-149752 (JP, A)                 JP-A-8-235143 (JP, A)                 JP-A-7-152694 (JP, A)                 Japanese Patent Laid-Open No. 10-49507 (JP, A)                 JP-A-9-6734 (JP, A)                 Hideki Saito and others, event-capable               Shu coherence control method and its burr               Application to synchronization, IPSJ research report               Announcement, Japan, August 19, 1992, Vol.               92 No. 64 (92-ARC-95), p.               9-16

Claims (4)

(57) [Claims] 1. A cluster-type parallel computer system in which nodes having one or more processors are coupled to each other in an inter-node network, wherein a barrier synchronizing means connected to the inter-node network participates in barrier synchronization. A means for storing the number, a counting means for copying the value of the storing means as an initial value and subtracting one for each barrier synchronization request from each processor participating in the barrier synchronization, and the count value being 0. Has a means for issuing a barrier synchronization establishment notification to the node at the same time, and a means for performing the copy again at the same time, one barrier synchronization means is provided for each barrier , and each processor in the node With this barrier synchronization establishment notification, the assigned bit of the state register assigned for each barrier on the node A cluster-type parallel computer system characterized by detecting establishment of barrier synchronization by confirming reversal. 2. A node having one or more processors
Cluster parallel meter connected by inter-network
Barrier synchronization management connected to the inter-node network in a computer system
A barrier synchronization process running on a node , one barrier synchronization process is provided for each barrier.
Is, the barrier synchronization process, the first of the generated if the state variable
Participate in barrier synchronization by performing processing that sets the period value to "0"
Processing for storing the number of processors in a node, and
The number of processors is copied as an initial value and is used for barrier synchronization.
Decremented by 1 for each barrier synchronization request from each participating processor
Count processing to be performed and when the count value becomes 0
Increment the state variable by 1 in the barrier synchronization management process.
And write that value to the state variable in the node,
Sometimes, the copying is performed again , and each processor in the node has a state for each barrier in the node.
By confirming the update of the variable, the establishment of barrier synchronization is detected.
Cluster type parallel computer system characterized by issuing
Mu. 3. A barrier synchronization method between processors in a cluster type parallel computer system in which nodes having one or more processors are connected by an inter-node network, wherein the number of processors participating in barrier synchronization is one for each barrier.
One as an initial value, a step of setting the initial value in counting means provided for each barrier, and a value of the counting means is set to 1 in accordance with a synchronization request from a processor participating in the barrier synchronization. And a step of detecting the establishment of barrier synchronization when the value of the counting means becomes 0, and notifying a node including one or more processors participating in the barrier synchronization that the barrier synchronization is established. and procedures for setting the initial value to the counting means, procedures processor participating in the barrier synchronization, in which the read non-procedure the value of the state register in the node, updates the value of the status register by the barrier synchronization establishment notification A processor for detecting that barrier synchronization has been established by updating the status register. Inter-barrier synchronization method. 4. A barrier synchronization method between processors in a cluster parallel computer system in which nodes having one or more processors are connected by an inter-node network, wherein the number of processors participating in barrier synchronization is one for each barrier.
One as an initial value, a step of setting the initial value in counting means provided for each barrier, and a value of the counting means is set to 1 in accordance with a synchronization request from a processor participating in the barrier synchronization. And a step of detecting the establishment of barrier synchronization when the value of the counting means becomes 0, and notifying the establishment of the barrier synchronization to a node including one or more processors participating in the barrier synchronization. and procedures for setting the initial value to the counting means, the processor to join before Symbol barrier synchronization, and read non-procedure the value of the state register in the node, updates the value of the status register by the barrier synchronization establishment notification And a computer-readable recording medium recording a program for causing a computer to execute the method having the steps.