JP3480105B2 - Display panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel in an active matrix type liquid crystal display device or the like.

[0002]

2. Description of the Related Art For example, some active matrix type liquid crystal display devices have an auxiliary capacitance portion in addition to a pixel capacitance portion. 7 and 8 show a part of a display panel in such a conventional active matrix type liquid crystal display device. This display panel is a glass substrate 1
Is equipped with. Scanning lines (gate lines) 2A and 2B also serving as auxiliary capacitance lines and signal lines (drain lines) 3 are provided in a matrix on the upper surface side of the glass substrate 1, and a thin film transistor 4A as a switching element is provided near each intersection thereof. 4B and pixel electrodes 5A, 5B,
5C is provided.

That is, scanning lines 2A and 2B including a gate electrode 6 (a portion which also serves as an auxiliary capacitance line will be described later) are formed at predetermined positions on the upper surface of the glass substrate 1, and the gate is formed on the entire upper surface. The insulating film 7 is formed. A semiconductor thin film 8 made of amorphous silicon is formed at a predetermined position on the upper surface of the gate insulating film 7, and a channel protective film 9 is formed at the center of the upper surface of the semiconductor thin film 8. Contact layers 10 and 11 made of n ⁺ silicon are formed on both sides of the upper surfaces of the semiconductor thin film 8 and the channel protection film 9, and a drain electrode 12 and a source electrode 13 are formed on the upper surfaces of the contact layers 10 and 11. The signal line 3 is formed simultaneously with the formation of the electrodes 12 and 13. ITO is provided at a predetermined position on the upper surface of the gate insulating film 7.
Pixel electrodes 5A, 5B, and 5C are formed by being connected to the source electrode 13.

Next, a portion of the scanning lines 2A and 2B which also serves as an auxiliary capacitance line will be described. The scanning line 2B connected to the pixel electrode 5B shown in the central portion of FIG. 7 via the thin film transistor 4B is provided on the lower side of the pixel electrode 5B, but the scanning line 2A in the preceding stage, that is, the upper side of the pixel electrode 5B. The scanning line 2A provided on the side also serves as an auxiliary capacitance line for the pixel electrode 5B. The scanning line 2A in the previous stage is drawn out along the common straight line portion 2a provided at a position corresponding to the upper side portion of the pixel electrode 5B, and from the common straight line portion 2a along the left side portion and the right side portion of the pixel electrode 5B. It consists of drawer parts 2b and 2c. And
The respective predetermined portions of the common linear portion 2a and the lead portions 2b, 2c are overlapped with the upper side portion, the left side portion and the right side portion of the pixel electrode 5B, and the overlapped portion forms an auxiliary capacitance portion. On the other hand, although not shown, the pixel capacitance portion is formed by the pixel electrode 5B, a common electrode arranged to face the pixel electrode 5B, and liquid crystal arranged between them.

Next, FIG. 9 shows an equivalent circuit of an active matrix type liquid crystal display device having the above-mentioned display panel. Reference numeral 21 is a pixel capacitance portion, 22 is an auxiliary capacitance portion, and 23 is a gate electrode 6 of the thin film transistor 4B.
And a parasitic capacitance portion between the source electrode 13 and 24, a parasitic capacitance portion between the pixel electrode 5B and the scanning line 2B for the pixel electrode 5B. Then, the capacitance of the pixel capacitance section 21 is changed to C _LC.
When the capacitance of the auxiliary capacitance portion 22 is C _S , the total capacitance of the parasitic capacitance portions 23 and 24 is C _GS, and the potential difference between the high level and the low level of the gate pulse is V _GHL , the gate pulse is turned off. Then, a jump voltage ΔV obtained by the following equation (1) is generated. ΔV = (C _GS · V _GHL ) / (C _LC + C _S + C _GS ) …… (1)

By the way, since the capacitance C _LC of the pixel capacitance section 21 is different between the ON state and the OFF state, the jump voltage ΔV also takes different values in the ON state and the OFF state. When the voltage difference ΔΔV of the jump voltage ΔV in both states is obtained, the following equation (2) is obtained. However, since the capacitance C _LC of the pixel capacitance unit 21 is all different depending on the data (gradation) even in the ON state, the maximum capacitance is C
_{LC / FULL,} and the variable capacity due to data is C _{LC / DATA} . ΔΔV = (C _{LC / FULL-} C _{LC / DATA} ) ・ C _GS・ V _GHL / {(C _{LC / FULL} + C _S + C _GS ) ・ (C _{LC / DATA} + C _S + C _GS )} …… (2)

Since this voltage difference ΔΔV causes afterimages and image sticking, it is desirable to make its absolute value as small as possible. As one method for this, by forming the thin film transistor 4B in a self-alignment structure,
Gate electrode 6 and source electrode 13 of thin film transistor 4B
There is a method of reducing the total capacitance C _GS by reducing the capacitance of the parasitic capacitance section 23 between the and. However, in this case, the pixel electrode 5B and the scanning line 2 for the pixel electrode 5B
It is not possible to reduce the capacitance of the parasitic capacitance section 24 between B and B.

[0008]

As described above, in the conventional active matrix type liquid crystal display device, in particular, the capacitance of the parasitic capacitance portion 24 between the pixel electrode 5B and the scanning line 2B for the pixel electrode 5B is reduced. As a result, there is a limit to the reduction of the absolute value of the voltage difference ΔΔV between the jump voltages ΔV in the on-state and the off-state, and there is a problem that it is not possible to obtain a better image quality. An object of the present invention is to provide a display panel capable of reducing the capacitance of a parasitic capacitance portion between a pixel electrode and the pixel electrode scanning line.

[0009]

According to a first aspect of the present invention, pixel electrodes are connected to scanning lines and signal lines provided in a matrix form via switching elements, and adjacent pixel electrode scanning lines and in the display panel to form an auxiliary capacitor by a portion where the pixel electrode are overlapped, the in the adjacent pixel electrode scan lines wherein the pixel electrode, one side edge of the adjacent pixel electrode side and the one side
Than the central portion of the other side edge opposite to the edge is obtained by distributing <br/> location to the other side edge.

[0010]

In accordance with the invention according to claim 1, in the adjacent pixel electrode scan line the pixel electrode, adjacent pixel electrodes
Since the one side edge on the one side and the other side edge opposite to the one side edge are arranged on the other side edge side with respect to the central portion, the distance between the one side edge of the pixel electrode and the pixel electrode scanning line is The capacitance is increased to some extent, and the capacitive coupling between the pixel electrode and the pixel electrode scanning line is reduced accordingly. Therefore, the capacitance of the parasitic capacitance portion between the pixel electrode and the pixel electrode scanning line can be reduced .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a main part of a display panel to which a first embodiment of the present invention is applied. In this figure, the same reference numerals are given to the same names as those in FIG. 7, and the description thereof will be omitted as appropriate. In the first embodiment, the scanning line 2A at the previous stage, which also serves as the auxiliary capacitance line for the pixel electrode 5B shown in the central portion of FIG. 1, has a common straight line portion 2d provided substantially at the central portion in the vertical direction of the pixel electrode 5B. And this common straight line part 2
It is composed of a lead-out portion 2e which is led out from d along the left side portion of the pixel electrode 5B. The respective predetermined portions of the common straight line portion 2d and the lead portion 2e are overlapped with the substantially central portion in the vertical direction and the left side portion of the pixel electrode 5B, and the overlapped portion forms an auxiliary capacitance portion. In addition, the leading end of the lead-out portion 2e is the pixel electrode 5A in the previous stage.
Is the gate electrode 6 of the thin film transistor 4A in the previous stage connected to.

As a result of the above, the common straight line portion 2d of the scanning line 2B for the pixel electrode 5B is disposed substantially vertically in the center of the pixel electrode 5C in the subsequent stage. When this arrangement is viewed from another direction, the pixel electrode at the rear stage adjacent to the rear stage of the pixel electrode 5B between the lower side (one side edge) of the pixel electrode 5B and the scanning line 2B for the pixel electrode 5B. One side edge (upper side) of 5C is arranged. As a result, as compared with the conventional case shown in FIG.
The horizontal interval t between B and the common straight line portion 2d of the scanning line 2B for the pixel electrode 5B becomes large to some extent, and accordingly, the capacitive coupling between the pixel electrode 5B and the scanning line 2B for the pixel electrode 5B is performed. Therefore, the capacitance of the parasitic capacitance portion between the pixel electrode 5B and the scanning line 2B for the pixel electrode 5B can be reduced, and further, a better image quality can be obtained.

By the way, since the common straight line portion 2d of the scanning line 2B for the pixel electrode 5B is arranged substantially vertically in the center of the pixel electrode 5C in the subsequent stage, it is applied to a transmissive active matrix type liquid crystal display device. In this case, the scan line 2B is made of, for example, ITO which is the same material as the pixel electrode.
When formed by, the aperture ratio can be prevented from lowering. When applied to a reflection type active matrix type liquid crystal display device, even if the scanning line 2B is made of an opaque material such as aluminum or chromium, the aperture ratio can be prevented from lowering.

Next, FIG. 2 shows a main part of a display panel to which the second embodiment of the present invention is applied. In this figure, the same reference numerals are given to the same names as those in FIG. 1, and the description thereof will be omitted as appropriate. In the second embodiment, a part of the common straight line portion 2d of the scanning line 2A is a substantially U-shaped protruding portion that protrudes downward, that is, extends leftward extending downward along the left side portion of the pixel electrode 5B. The protrusion 2f and the right extension 2g extending downward along the right side portion of the pixel electrode 5B.
And both extending portions 2f and 2g along the lower side of the pixel electrode 5B.
It is a substantially U-shaped projecting portion including a lower portion 2h provided therebetween. Then, almost all of the left extending portion 2f is overlapped with the pixel electrode 5B, and the right extending portion 2g and the lower portion 2h are formed.
The respective predetermined portions are overlapped with the right side portion and the lower side portion of the pixel electrode 5B, and the overlapped portion also forms the auxiliary capacitance portion. In this case, in particular, the lower side of the lower portion 2h is arranged outside the lower side (the other side edge) of the pixel electrode 5B, but does not reach the upper side of the pixel electrode 5C in the subsequent stage.

Next, FIG. 3 shows a simplified cross section taken along line XX of FIG. In this figure, the dotted lines indicate the lines of electric force. The lines of electric force are generated between the pixel electrode 5B and the pixel electrode 5C in the rear stage, between the pixel electrode 5B and the lower portion (auxiliary capacitance electrode) 2h, and the pixel electrode 5B in the rear stage.
And the lower portion 2h are connected to each other, and both end points thereof are perpendicular to the pixel electrodes 5B and 5C and the lower portion 2h. And, the more the lines of electric force are, the larger the capacity therebetween is. In this case, since one predetermined side edge of the lower portion 2h is located between the pixel electrodes 5B and 5C, the capacitive coupling between the pixel electrodes 5B and 5C is weakened, so that a better image quality can be obtained. On the contrary,
As shown in FIG. 4, a lower portion 2h is placed between the pixel electrodes 5B and 5C.
Is not present, the capacitive coupling between the pixel electrodes 5B and 5C becomes strong, and as a result, the potential of the pixel electrode 5B in the OFF state of the thin film transistor 4B is the pixel electrode 5 in the subsequent stage.
It fluctuates under the influence of the potential of C, and it becomes impossible to obtain better image quality.

In the second embodiment shown in FIG. 2, the common straight line portion 2d of the scanning line 2A is arranged substantially vertically in the center of the pixel electrode 5B, and the drain electrode 12 and the source electrode 13 of the thin film transistor 4B are gated. Electrode 6
Although they are arranged on the left side and the right side respectively, as in the third embodiment shown in FIG.
It is also possible to dispose d on the lower side of the pixel electrode 5B substantially in the vertical center and to dispose the drain electrode 12 and the source electrode 13 of the thin film transistor 4B on the lower side and the upper side of the gate electrode 6, respectively.

In the first to third embodiments, the pixel electrodes 5A to 5C are arranged in stripes, but it is particularly effective in the case of colorization as in the fourth embodiment shown in FIG. There may be a delta arrangement. In this case, since the scanning line 2A and the signal line 3 overlap with each other only at the intersection indicated by the parallel hatched line P, it can be minimized. As a result, the load capacity seen from the driver for driving this display panel is reduced.

Further, in the first embodiment shown in FIG. 1, for example, the scanning line 2B connected to the pixel electrode 5B in the central portion through the thin film transistor 4B is arranged substantially vertically in the central portion of the pixel electrode 5C in the subsequent stage. However, the vertical relationship of FIG. 1 is reversed, and the thin film transistor 4 is formed on the pixel electrode 5B in the central portion.
The scanning line 2B connected via B may be arranged substantially at the center in the vertical direction of the pixel electrode 5A in the preceding stage. Needless to say, this is also the case with the second to fourth embodiments.

[0019]

As described above, according to the first aspect of the present invention, the adjacent pixel electrode scanning line is provided on one side edge of the pixel electrode adjacent to the adjacent pixel electrode side.
Since it is arranged closer to the other side edge than the central portion with the other side edge facing, the distance between the one side edge of the pixel electrode and the pixel electrode scanning line is increased to some extent, and accordingly the pixel electrode and the pixel electrode Capacitive coupling with the pixel electrode scanning line is reduced, so that the capacitance of the parasitic capacitance portion between the pixel electrode and the pixel electrode scanning line can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a display panel to which a first embodiment of the present invention is applied.

FIG. 2 is a plan view of a main part of a display panel to which a second embodiment of the present invention is applied.

FIG. 3 is a diagram showing a simplified cross section taken along line XX of FIG.

FIG. 4 is a sectional view similar to FIG. 3 shown for comparison.

FIG. 5 is a plan view of an essential part of a display panel to which a third embodiment of the invention is applied.

FIG. 6 is a plan view of a main part of a display panel to which a fourth embodiment of the invention is applied.

FIG. 7 is a plan view of part of a conventional display panel.

8 is a cross-sectional view taken along the line YY of FIG.

FIG. 9 is a diagram showing an equivalent circuit of an active matrix type liquid crystal display device.

[Explanation of symbols]

2A, 2B scanning line 3 signal lines 4A, 4B Thin film transistor (switching element) 5A, 5B, 5C Pixel electrode

Claims (5)

(57) [Claims] 1. A pixel electrode is connected to a scan line and a signal line provided in a matrix form via a switching element, and an auxiliary capacitance is formed by a portion where an adjacent pixel electrode scan line and the pixel electrode are overlapped. In the display panel, the adjacent pixel electrode scan lines are
In the corresponding pixel electrode, one side edge of the adjacent pixel electrode side
The other side of the central portion of the other side edge opposite to said one side edge and
A display panel characterized by being arranged on the edge side . 2. The adjacent pixel electrode scan lines are
The display panel of claim 1, wherein a part and wherein the this <br/> located outside the other side edge of the corresponding pixel electrode. Wherein a portion of the adjacent pixel electrode scan lines, claims, characterized in that are superimposed with the at least one side portion of the side portion perpendicular to the pixel electrode scanning line of the pixel electrode The display panel according to 1 or 2. Wherein a portion of the adjacent pixel electrode scan line, to claim 1 or 2, characterized in that they are overlapped with both side portions perpendicular to the said pixel electrodes of the pixel electrode for the scanning lines Display panel described. Wherein said adjacent pixel electrodes for the scanning lines, before
Serial display panel according to claim 1 or 2, characterized in that a shape that protrudes in a U-shape toward the pixel electrode side positioned on the other side edge of the pixel electrode.