JP3476113B2 - Contact hole forming method and semiconductor integrated circuit device forming method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole forming method and a semiconductor integrated circuit device forming method .

[0002]

2. Description of the Related Art A conventional procedure is shown in FIGS. Note that FIG. 9 shows a cross-sectional structure of the contact hole portion immediately after the contact hole opening and a view seen from the surface side.
Although the first interlayer insulating film 1 is shown as the lowermost layer in FIG. 9, there is a lower wiring below the first interlayer insulating film 1, and the contact 2 reaching the wiring is buried. It is assumed that

The upper end surface of the contact 2 is electrically connected to the lower surface of the lower layer wiring 3 extending along the surface of the primary interlayer insulating film 1. FIG. 9 shows a state in which a part of the secondary interlayer insulating film 4 laminated so as to cover the surface of the lower layer wiring 3 is removed and a contact hole 5 is opened. A natural oxide film is immediately grown on the surface of the lower layer wiring 3 exposed by the opening of the contact hole 5. However, since the natural oxide film interferes with the electrical connection between the lower layer wiring 3 and the upper layer wiring, a step of removing the natural oxide film before forming the contact is provided.

This is the surface treatment shown in FIG. At this time, dilute hydrofluoric acid (HF) or the like is used to remove the natural oxide film, but since the etching speed of the lower layer wiring 3 is faster than that of the natural oxide film, only the lower layer wiring 3 located below the opening of the contact hole 5 is etched. Instead, as shown in FIG. 10, the erosion progresses to the lower layer wiring 3 located below the second interlayer insulating film 4 on all the sidewall portions of the contact hole 5, and the secondary interlayer insulating film 4 and the lower layer wiring 4 are eroded. There was a problem in that it was unavoidable that a cavity was formed between the two.

For this reason, when the upper layer wiring 7 is laminated in this state, as shown in FIG. 11, a cavity which cannot be filled with the upper layer wiring 7 over the entire circumference of the lower side wall of the contact hole 5 is avoided. There was a problem that I could not get it.
In the worst case, as shown in FIG. 12, disconnection may occur between the upper layer wiring 7 and the lower layer wiring 3 in this portion.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above points, and a contact hole forming method and a semiconductor integrated circuit capable of surely connecting an upper wiring and a lower wiring in a contact hole portion. It is intended to propose a device.

[0007]

In order to solve such a problem, in the present invention, the bottom surface of the contact hole is formed.
Forming a first interlayer insulating film on the first interlayer insulating film
Lower layer wiring, and place the lower layer wiring inside the contact hole.
Pattern the lower layer wiring so that part or all of the wire ends are exposed.
2nd turning and forming side surface of contact hole
Next layer insulation film is formed and exposed lower layer wiring is surface treated
However, part or all of the end exposed by this surface treatment
And the lower wiring that partially corroded under the second interlayer insulating film
And upper layer wiring on the first interlayer insulating film and the second interlayer insulating film
Are stacked. At this time, an area portion where at least one of the side walls forming the contact hole is not provided with the lower layer wiring to be electrically connected to the upper layer wiring is present under at least one side wall. Since there is no possibility that a cavity will be formed in this portion due to the surface treatment, it is possible to avoid the possibility of disconnection of the upper layer wiring in at least the area portion. As a result, the upper layer wiring and the lower layer wiring can be surely connected to each other without defective conduction.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment FIG. 1 in which parts corresponding to those in FIGS.
~ Fig. 4 shows an example of the processing procedure of the contact hole forming method according to the present invention. In this embodiment, the contact hole 11 is formed at a position where the end of the lower layer wiring 3 is exposed at the substantially central portion of the opening of the contact hole 11 at the time of opening. FIG. 1 shows the situation. In the first embodiment, only one side of the end portion of the lower layer wiring 3 is exposed in the contact hole 11.

After the contact hole 11 is formed, the surface treatment shown in FIG. 2 is performed next. On this occasion,
As for the lower layer wiring 3 in the portion exposed to the opening of the contact hole 11, erosion 12 occurs on the surface of the lower layer wiring 3 and its adjacent portion, as in the conventional case. However, since the lower layer wiring 3 is not provided under the side wall of one or more side wall portions of the contact hole 11, the side wall is formed vertically and a cavity as in the conventional case does not occur. Incidentally, in the case of FIG. 2, it is possible to prevent cavities from being formed on all or part of the three sides of the four sides forming the contact hole 11.

After such surface treatment, the process proceeds to the laminating process for the upper layer wiring 13 shown in FIG. At this time, there is a possibility that a disconnection as shown in FIG. 4 may occur in the side wall portion of the portion where the lower layer wiring 3 is located in the lower layer, but the upper layer wiring 13 contacts the side wall and the bottom surface of the portion where the lower layer wiring 3 is not present. Since the holes 13 are continuously stacked from the side wall to the bottom surface, the upper layer wiring 1 is formed on at least one side.
Conduction between the lower layer wiring 3 and the lower layer wiring 3 is surely guaranteed.

According to the above method, the contact hole 1
When the opening 1 is formed, the contact hole 11 is formed by positioning so that the end of the lower layer wiring is exposed at the bottom surface of the opening, so that at least one side wall of the four side walls forming the contact hole 11 is formed. The boundary between the bottom surface and the bottom can be surely conducted, and the upper layer wiring 1
It is possible to realize a contact hole forming method capable of electrically and surely connecting the third layer 3 and the lower layer wiring 3.

Further, according to the above method, since there is no possibility that a cavity is formed in the side wall portion of the contact hole 11, the process at the time of surface treatment or at the time of opening the contact hole becomes reliable and the process margin can be further expanded. Further, according to the above method, the contact hole 11
Since there is no possibility that a cavity will be formed in the side wall portion of the above, it is possible to widen the selection range of the etching liquid or etching gas at the time of surface treatment or opening of the contact hole.

(2) Reference Example Next, in FIGS. 5 to 8 in which parts corresponding to those in FIGS. 1 to 4 are denoted by the same reference numerals, an example of a processing procedure of the contact hole forming method in the reference example is shown. Note that this embodiment is an example in which the contact hole 11 is formed such that the entire lower layer wiring 3 exists at the substantially central portion of the opening of the contact hole 11 isolated from the side wall at the time of opening. FIG. 5 shows the situation. In the case of the second embodiment, the lower layer wiring 3
All of the end faces of are exposed in the contact hole 11.

FIG. 6 shows a state in which this is surface-treated. In this case, the surface of the lower layer wiring 3 is eroded and deformed into a hemispherical shape as shown in FIG. 6, for example. However, only the lower wiring 3 is affected by such erosion, and a cavity is not formed at the boundary between the primary interlayer insulating film 1 and the secondary interlayer insulating film 4 due to the effect of erosion. Absent. Therefore, when the upper layer wiring 13 is laminated after this surface treatment, as shown in FIG.
Further, as shown in FIG. 8, the upper wiring 13 is continuously formed from the side wall of the contact hole 11 along the bottom surface thereof, and it is possible to eliminate the possibility of defective conduction on all four side walls forming the contact hole 11. This makes it possible to electrically and reliably connect the upper layer wiring 13 and the lower layer wiring 3.

According to the above structure, the contact hole 1
1 is opened, a contact hole 11 is formed on the bottom surface of the opening of a size large enough to expose the entire end of the lower layer wiring, and the contact hole 11 is positioned so that the entire contact hole 11 can be exposed. By forming the contact hole, a conduction state can be secured at the boundary between the side wall and the bottom surface of the contact hole 11, and a contact hole forming method can be realized in which the upper layer wiring 13 and the lower layer wiring 3 can be electrically and reliably connected. In addition, the same effects as in the case of the first embodiment can be obtained.

[0017]

Effects of the Invention According to the present invention as described above, contactor
Forming a primary interlayer insulating film that forms the bottom surface of the through hole,
A lower layer wiring is formed on the first interlayer insulating film, and contact is made.
Part or all of the end of the lower layer wiring is exposed inside the hole.
Pattern the lower layer wiring to
The second interlayer insulating film that forms the side surface of the
The lower layer wiring is surface treated and exposed by this surface treatment.
Part or all of the edge and the part under the second interlayer insulating film penetrates.
On the eroded lower layer wiring, the first interlayer insulating film, and the second layer
By laminating the upper layer wiring on the inter-layer insulating film, the upper layer wiring can be laminated without disconnection at the lower part of at least one side wall of the side walls forming the contact hole. As a result, it is possible to realize a contact hole forming method capable of surely connecting the upper wiring and the lower wiring. Further, this makes it possible to realize a highly reliable semiconductor integrated circuit device.

[Brief description of drawings]

1A and 1B are a sectional view and a plan view for explaining a method of forming a contact hole according to the present invention.

2A and 2B are a cross-sectional view and a plan view showing how the contact hole portion shown in FIG. 1 is surface-treated.

3A and 3B are a cross-sectional view and a plan view showing a state after an upper layer wiring is laminated on the contact hole portion shown in FIG.

4 is a cross-sectional view showing an enlarged detail of FIG.

5A and 5B are a cross-sectional view and a plan view for explaining a contact hole forming method according to the present invention.

6A and 6B are a cross-sectional view and a plan view showing a state where the contact hole portion shown in FIG. 5 is surface-treated.

7A and 7B are a cross-sectional view and a plan view showing a state after an upper layer wiring is laminated on the contact hole portion shown in FIG.

FIG. 8 is a cross-sectional view showing an enlarged detail of FIG.

9A and 9B are a cross-sectional view and a plan view for explaining a conventional contact hole forming method.

10A and 10B are a cross-sectional view and a plan view showing how the contact hole portion shown in FIG. 9 is surface-treated.

11A and 11B are a sectional view and a plan view showing a state after the upper layer wiring is laminated on the contact hole portion shown in FIG.

12 is an enlarged sectional view showing details of FIG. 11. FIG.

[Explanation of symbols]

1 ... Primary interlayer insulating film, 2 ... Contact, 3 ... Lower layer wiring, 4 ... Secondary interlayer insulating film, 5, 11 ... Contact hole, 6, 12 ... Erosion, 7, 13 ... … Upper layer wiring.

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Claims (2)

(57) [Claims] 1. A primary forming a bottom surface of a contact hole
An interlayer insulating film is formed , a lower layer wiring is formed on the primary interlayer insulating film, and one end portion of the lower layer wiring is formed inside the contact hole.
Pattern the lower layer wiring so that part or all is exposed.
Grayed, Second interlayer insulating constituting a side surface of said contact hole
A film is formed, and the exposed lower layer wiring is subjected to a surface treatment, and part or all of the exposed end portion is formed by the surface treatment.
And the lower layer in which a portion under the second interlayer insulating film is eroded
On the wiring, the first interlayer insulating film, and the second interlayer insulation film
A method of forming a contact hole, which comprises laminating an upper layer wiring on an edge film . 2. A primary forming a bottom surface of a contact hole
An interlayer insulating film is formed , a lower layer wiring is formed on the primary interlayer insulating film, and one end portion of the lower layer wiring is formed inside the contact hole.
Pattern the lower layer wiring so that part or all is exposed.
Grayed, Second interlayer insulating constituting a side surface of said contact hole
A film is formed, and the exposed lower layer wiring is subjected to a surface treatment, and part or all of the exposed end portion is formed by the surface treatment.
And the lower layer in which a portion under the second interlayer insulating film is eroded
On the wiring, the first interlayer insulating film, and the second interlayer insulation film
A method for forming a semiconductor integrated circuit device, comprising: laminating an upper wiring on an edge film .