JP3474320B2 - Wiring inspection method for semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ASIC (Applic
ation Specific IC), and more particularly, to improvement of a wiring inspection method for a macro-embedded cell array having both the features of a standard cell and a gate array.

The ASIC is provided with basic circuits such as gates and cells in advance, so that the first stage of circuit design can be omitted.
It shortens the development time. In the field of ASIC, standard cells for reducing the chip size and gate arrays for shortening the development period have been developed due to their advantages. However, in recent years, the increase in the circuit scale has made the chip size larger and the development period longer, so macro-embedded cell arrays having both features have been developed, and the demand for them is increasing.

[0003]

2. Description of the Related Art LSI such as a macro-embedded cell array
Describes the development process. First, the specifications of the LSI are defined. Next, a circuit designing the operation and a pattern to be provided on the silicon wafer are designed, and then a trial process is started.

In the trial manufacturing process, the bulk process is a process of forming transistors and resistors on the silicon substrate according to the completed pattern layout data. The wiring process is a process of forming a metal pattern as a design drawing on a silicon substrate and connecting transistors and resistors formed by a bulk process. assembly·
The test process is a process of packaging the finished silicon substrate and shipping it after the pass / fail judgment.

Here, the macro-embedded cell array is
Since a plurality of wiring patterns can be applied to one bulk pattern, layout data (layout bulk data) such as transistors and resistors created in the bulk process, and wiring created in the wiring process If the pattern information (layout wiring data) does not match, the operation of the completed IC cannot be guaranteed. Therefore, it is important to perform a wiring inspection to verify whether the data of the wiring layer completely matches the data of the bulk layer (consistency of the bulk layers in both).

FIG. 6 shows a flow chart of a conventional wiring inspection method. In the conventional wiring inspection, the layout data (step S81) generated in the bulk layout step (step S80) and the wiring layout step (step S85)
The layout data (step S86) generated in
The masks are supplied to the same or different mask manufacturers (steps S82 and S87). Mask data is created by each mask manufacturer based on the supplied data (steps S83 and S88).

The verification of the consistency is performed by comparing the mask data (steps S84 and S89) delivered from the mask manufacturer (step S90). When the consistency is not obtained (step S90: NO), the wiring layout is redone (step S85). When the consistency is obtained (step S90: YES), the drawing for manufacturing the IC is performed (steps S91 and S92).

As described above, in the conventional verification of the consistency of the bulk layer, the mask data for the wiring drawing which is the output of the wiring process and the mask data input in the bulk process are compared. That is, referring to the data at the stage immediately before actually forming wiring on the wafer, all physical information such as transistors and resistors in the bulk layer is compared with the wiring information to verify the consistency. Was there.

[0009]

However, since it takes a considerable amount of time to create mask data, if a problem such as data inconsistency occurs, the wiring layout time will be duplicated again. , The development time will be very long,
There was an inconvenience. In particular, recently, since the physical information amount of the bulk layer is increasing with the increase in the size of the macro cell to be mounted and the number of gates, the number of man-hours such as the use time and cost of the computer required when a wiring failure occurs Is dramatically increasing.

In view of the above problems, the present invention has an object to reduce the development time of a semiconductor integrated circuit in which a layout of circuit elements and a wiring layout are individually created as represented by a macro-embedded cell array. .

[0011]

According to a first aspect of the present invention, there is provided a wiring inspection method for a semiconductor integrated circuit, which is based on circuit layout data that defines a layout of circuit elements and wiring layout data that defines wiring of the circuit elements. Therefore, the wiring layout process for inputting the circuit layout data that defines the layout of the circuit elements in the semiconductor integrated circuit and creating the wiring layout data that defines the wiring for the circuit elements based on the input circuit layout data The completed wiring layout data is compared with the circuit layout data input at the stage when the wiring layout data has been created, and if the circuit layout data and the wiring layout data do not match, a new wiring layout process is performed. Create wiring layout data based on circuit layout data , If the circuit layout data and wiring layout data is consistent, configured with a consistency verification process proceeds to the fabrication of semiconductor integrated circuit.

According to a second aspect of the present invention, there is provided a wiring inspection method for a semiconductor integrated circuit, which is based on circuit layout data that defines a layout of circuit elements and wiring layout data that defines wiring of the circuit elements. The circuit layout process for creating the circuit layout data that determines the layout of the circuit elements in the semiconductor integrated circuit based on the pattern layout data that defines the pattern, and the wiring layout data that defines the wiring for the circuit element based on the pattern layout data. The wiring layout process to be created is compared with the circuit layout data created in the circuit layout process and the wiring layout data created in the wiring layout process. If the circuit layout data and the wiring layout data do not match, Layout process Wiring layout data based on newer pattern layout data is created, and when the circuit layout data and the wiring layout data are matched, a consistency verification step of shifting to manufacturing of a semiconductor integrated circuit is provided. It

According to a third aspect of the present invention, in the wiring inspection method for a semiconductor integrated circuit according to the first or second aspect, the consistency verification step includes a predetermined wiring connection information out of all circuit layout data. Only data is extracted as verification data and compared.

According to a fourth aspect of the present invention, in the wiring inspection method for a semiconductor integrated circuit according to the first or third aspect, the consistency verification step includes a predetermined wiring connection data out of all wiring layout data. Only data is extracted as verification data and compared.

[0015]

According to the invention described in claim 1, since the wiring layout data for defining the wiring for the circuit element is created based on the input circuit layout data, the layout of the circuit element and the wiring layout are basically provided. Is consistent with.

Further, even if the circuit layout data and the wiring layout data do not match, the consistency verification step verifies the existence of this consistency immediately before the shift to the manufacturing of the semiconductor integrated circuit. Therefore, it is possible to recreate the wiring layout data based on the new circuit layout data in the wiring layout process.

According to the second aspect of the invention, the circuit layout process creates circuit layout data, and in parallel with this, the wiring layout process creates wiring layout data. In the consistency verification process, the circuit layout data and the wiring layout data are compared with each other, and if the two data do not match, the wiring layout process recreates the wiring layout data based on the new pattern layout data. If the two data match, the process moves to the manufacturing of a semiconductor integrated circuit.

According to the third or fourth aspect of the present invention, the data to be compared in the consistency verification process is limited to the information (for example, the position information) extracted from all the layout data. Is done in a short time.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the apparatus of the present invention will be described with reference to the drawings. ( I) First Embodiment This first embodiment is an application of the invention of claim 1,
Design the wiring layout based on bulk data.

FIG. 1 is a flowchart showing the overall flow of LSI manufacturing. The steps A and B are LS
This is a process of defining the physical specifications of I and the input / output conditions. In step C, the circuit actually mounted on the silicon substrate is designed. In step D, a pattern layout for creating the circuit created in step C on the silicon substrate is created. In this part, a lot of human manual work is involved,
Human error is most likely to occur. Step C'is a step of performing additional wiring or modification that occurs after the bulk layout (step D).

Step D is a bulk layout process, in which bulk data for layout is created in units of circuit elements such as transistors and resistors that form an actual macro cell. Step E is a mask data creation process, which creates mask data for bulk data.

Step F is a wiring layout process,
Layout wiring data for forming a metal pattern as designed on a silicon substrate is created. Step E'is a wiring mask data generation process, in which mask data for wiring data is generated.

Step G relates to the present invention, and Step E
And verifying the consistency of the bulk data and wiring data generated in step E ′. In steps H and H ′, a mask (photomask) corresponding to the presence or absence of a pattern is created for each layer of the silicon substrate based on the bulk data and the wiring data for which the consistency is tested. A mask is often manufactured by a specialized mask manufacturer.

The silicon wafer is exposed to light to form an actual pattern based on the photomask formed by the above steps. As mentioned above, layout design involves a lot of manual work, so at the initial design stage,
The pattern changes especially frequently. A wrong mask pattern wastes a huge amount of time and labor required for the wafer process. Therefore, mask creation (step H)
It is necessary to improve the completeness of the layout data before.

Therefore, in this embodiment, the consistency is verified at the stage of layout data for which a mask manufacturer or the like is requested to create a mask. Specifically, in the wiring process (step F in FIG. 1), the wiring layout is created while verifying the consistency based on the layout bulk data created in the bulk process (step E in FIG. 1). Is.

Next, the wiring inspection of the first embodiment to be performed in steps E to G of FIG. 1 will be described with reference to the flowchart of FIG. Bulk process (step S1
(Step E in FIG. 1), the layout of circuit elements such as transistors and resistors is determined, and bulk data, which is the layout information, is released (step S).
2). This bulk data may be supplied to the wiring process department within the same manufacturer or may be supplied from another manufacturer.

In the wiring process (step F in FIG. 1),
The layout bulk data is called from the released bulk data, and the wiring layout for connecting the circuit elements is created (step S5). At this time, the information such as the pattern shape and the logic information for wiring layout are referred to (step S4).

The wiring layout is output as layout wiring data (step S6). It is verified whether the layout bulk data matches the layout wiring data actually created (step S).
7).

If the layout wiring data and the currently released bulk data for layout are matched (OK), both data are released to the same or different mask manufacturers, and mask production is performed separately. (Step S8).

If both data do not match (step S7: NG), the wiring layout is created again using the latest bulk data (step S5). In this way, integrity verification is performed immediately before release when bulk data is changed by the time the wiring layout work is completed when wiring data is created based on a certain version of bulk data. This is the case.

As described above, according to the first embodiment, first, the wiring layout is created based on the bulk data that defines the layout of the circuit elements, and the consistency is verified just before the release. For this reason, it is possible to reduce the risk that the data inconsistency is surely generated after the data inconsistency is discovered after the mask data is created, and the data inconsistency is surely generated as compared with the conventional procedure of starting over from the wiring layout. (II) Second Embodiment The second embodiment is an application of the inventions of claims 2 to 4. The point that the bulk process and the wiring process are performed in parallel is the same as the conventional method, but the consistency is verified before the mask is made. Also, the consistency is verified only by the extracted data.

In this embodiment, in the flow chart of the LSI manufacturing shown in FIG. 1, after the pattern design (step D), the bulk process (step E) and the wiring process (step F) are processed in parallel, and the final process is performed. A consistency test (step F) is performed.

The wiring inspection method of the second embodiment will be described with reference to the flowchart of FIG. Steps S10 to S1
The flow of the bulk layout design of step 3 is step S14-
It is processed in parallel with the flow of the wiring layout design of S17.

In the bulk process, first, of the pattern layout created in the pattern design process (step D in FIG. 1), only layout data relating to circuit elements is created (step S10), and this is used as bulk data for layout. (Step S11).

In step S12, only the data necessary for verifying the consistency with the wiring layout is extracted from the layout bulk data. For example, the layout data includes a master type, a master version number, a macrocell type, a macrocell version number, macrocell position information, a macrocell rotation / reversal code, and the like. In this, for example, the position information of the macro cell is extracted as the data for verifying the consistency (step S13).

On the other hand, in the wiring process, of the pattern layouts created in the pattern design process (step D in FIG. 1), only the layout relating to the wiring pattern is created (step S14) and used as the layout wiring data (step S14). Step S15).

In step S16, based on the same idea as in step S12, only the positional information required for the consistency verification is extracted from the layout wiring data. In step S18, the verification data extracted from the bulk process (step S13) and the verification data extracted from the wiring process (step S17) are compared with each other to verify matching.

Here, if the two verification data cannot be matched (step S17: NG), it is determined that the specification has been slightly changed during the creation of the layout data, and based on the new pattern design data. Then, the wiring layout is designed (step S14).

When the consistency of both verification data can be confirmed (step S17: OK), the layout data is released to the mask manufacturer (step S19). As described above, according to the second embodiment, the consistency is verified by using only necessary information out of the bulk data and the wiring data, which is necessary for the verification in addition to the effect of the first embodiment. You can save time. Further, even when the bulk data and the wiring data are created in parallel by different manufacturers, it is possible to prevent the mask from being redone. (III) Third Embodiment In the third embodiment, the processing of the first embodiment and the processing of the second embodiment are performed together.

That is, as shown in FIG. 4, basically, the bulk process (step S20) as shown in the second embodiment is performed.
To S23) and the wiring process (steps S24 to S28) are performed in parallel. At this time, in the wiring layout of the wiring process (step S25), the wiring layout is not based on the pattern layout from the pattern design process, but based on the layout bulk data created in the bulk process (step S25). .

The verification of the consistency between the layout bulk data in the bulk process and the layout wiring data in the wiring process is performed by extracting the verification data (steps S22 and S27) as in the second embodiment. The verification data thus extracted (steps S23 and S28) is compared (step S29).

If the verification data cannot be matched (step S29: NG), the wiring layout (step S2).
5) will have to be redone. As described above, according to the third embodiment, since wiring is performed based on bulk data as in the first embodiment, it is possible to avoid a fundamental input error of data to be used. Moreover, since the consistency between the latest bulk data and the wiring data is verified just before the mask is created, the risk of release data inconsistency can be reduced. (IV) Fourth Embodiment The fourth embodiment shows an example of a case where data creation is divided among different manufacturers.

As shown in FIG. 5, Maker A creates bulk data from a reference pattern layout supplied by a user or the like. That is, the maker A performs bulk layout based on the reference pattern layout (step S40) and creates layout bulk data (step S41). The bulk data for layout is supplied to the maker B.

In step S42, the verification data is extracted. The extracted verification data (step S4
3) is supplied to maker B. Further, release data to be delivered to the mask manufacturer C is created using the layout bulk data (step S44). The layout data by the created release command is released (step S46) and supplied to the mask manufacturer C.

The bulk data released to the mask manufacturer may be all of the bulk data, but may be the minimum data necessary for mask production, for example, only the verification data used for verifying the consistency.

On the other hand, the maker B designs the wiring layout based on the layout bulk data supplied from the maker A (step S47). At this time, if necessary, module layout data (step S56),
The wiring layout logic information (step S57), the layout data before EC (step S58), etc. are referred to.

In verifying the consistency, the verification data is extracted from the created layout wiring data (step S48) (step S49), and the extracted verification data (step S50) is supplied from the manufacturer A in bulk. The data is compared with the verification data (step S).
51).

If the verification data cannot be matched (step S51: NG), the latest layout bulk data (step S41) is requested to the manufacturer A again, and the wiring layout is restarted (step S47).

When both verification data are matched (step S51: OK), the release data is created using the layout wiring data (step S48) (step S52). That is, release data is created using the release command for the mask manufacturer (step S53) and released to the mask manufacturer C (step S54).

The mask manufacturer C manufactures a photomask for the bulk layer based on the release data relating to the bulk data supplied from the manufacturer A. In addition, a photomask having a wiring pattern is manufactured based on the release data regarding the wiring supplied from the maker B (step S55). Further, the mask manufacturer C provides the mask data to the semiconductor manufacturer, and the semiconductor integrated circuit is manufactured.

As described above, according to the fourth embodiment, the final consistency verification is performed even if each manufacturer is in charge of different processes, and the cost or man-hour is increased by re-creating the mask. Can be prevented. Further, even if the layout data cannot be matched, it is only necessary to repeat the layout creating process by one manufacturer. (V) Other Modifications Various modifications are possible without being limited to the above embodiment of the present invention.

In each of the above-mentioned embodiments, the verification of the consistency is carried out at the end of the wiring layout process, but the verification of the consistency may be carried out at another place. For example, if the mask manufacturer compares the bulk data and the wiring data, which have been separately supplied before the mask data is manufactured, if there is no match,
You may contact the manufacturer who does the wiring layout.

[0053]

According to the first aspect of the present invention, since the wiring layout data is created based on the circuit layout data, the two layout data have good consistency. Furthermore, since the matching of both layout data is verified immediately before the shift to the manufacturing of semiconductor integrated circuits, it is possible to prevent an enormous amount of time from being re-created in the conventional mask making, and it is possible to greatly reduce the time and economic loss.

Conventionally, when a user requests a semiconductor manufacturer (mask manufacturer) to manufacture a semiconductor integrated circuit, the consistency can be verified only after the mask data is supplied. However, according to the present invention, the consistency can be confirmed at the customer's level and in the design center. As a result, if the present invention is applied to the macro-embedded cell array, the features of the semiconductor integrated circuit, such as short development period and reduction of defects, can be brought out to the maximum.

According to the second aspect of the present invention, even when the circuit layout data and the wiring layout data are created in parallel, the consistency of both layout data immediately before the shift to the manufacturing of the semiconductor integrated circuit is performed. Since it is possible to verify the above, it is possible to prevent the development time from increasing due to the re-making of the mask.

According to the invention of claim 3 or claim 4, in addition to the effect of claim 1 or claim 2, the consistency is verified on the basis of the extracted verification data. The time required for verification can be shortened, and the development time can be shortened.

[Brief description of drawings]

FIG. 1 is a flow chart of LSI manufacturing.

FIG. 2 is a flowchart illustrating a wiring inspection method according to the first embodiment.

FIG. 3 is a flowchart illustrating a wiring inspection method according to a second embodiment.

FIG. 4 is a flowchart illustrating a wiring inspection method according to a third embodiment.

FIG. 5 is a flowchart illustrating a wiring inspection method according to a fourth embodiment.

FIG. 6 is a flowchart illustrating a conventional wiring inspection method.

[Explanation of symbols]

Steps A to H ... Each process in the LSI development process Steps S1 to S55 ... Concrete processing

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Claims (4)

(57) [Claims] 1. A wiring inspection method for a semiconductor integrated circuit based on circuit layout data that defines the layout of circuit elements and wiring layout data that defines the wiring of the circuit elements. A wiring layout step of inputting circuit layout data that defines an arrangement and creating wiring layout data that defines wiring for the circuit element based on the input circuit layout data, and the wiring layout data that has been created and the wiring layout data. The circuit layout data input at the stage when the wiring layout data has been created is compared, and if the circuit layout data and the wiring layout data do not match, new wiring layout data is created by the wiring layout process. Create wiring layout data based on And,
A wiring inspection method for a semiconductor integrated circuit, comprising: a consistency verification step of shifting to manufacturing of the semiconductor integrated circuit when the circuit layout data and the wiring layout data match. . 2. A wiring inspection method for a semiconductor integrated circuit based on circuit layout data defining a layout of circuit elements and wiring layout data defining wiring of the circuit element, the pattern defining a pattern of the semiconductor integrated circuit. A circuit layout step of creating circuit layout data that defines the layout of the circuit elements in the semiconductor integrated circuit based on the layout data; and creating wiring layout data that defines wiring of the circuit elements based on the pattern layout data And the wiring layout data created in the circuit layout step and the wiring layout data created in the wiring layout step are compared, and the circuit layout data and the wiring layout data match each other. Absent In this case, in the wiring layout process, wiring layout data based on new pattern layout data is created, and if the circuit layout data and the wiring layout data match, the process shifts to the manufacturing of the semiconductor integrated circuit. A wiring inspection method for a semiconductor integrated circuit, comprising: 3. The wiring inspection method for a semiconductor integrated circuit according to claim 1, wherein the matching verifying step is for verifying only predetermined data regarding connection information out of all the circuit layout data. A wiring inspection method for a semiconductor integrated circuit, which comprises extracting as data and comparing the data. 4. The wiring inspection method for a semiconductor integrated circuit according to claim 1, wherein the matching verification step verifies only predetermined data relating to connection information out of all the wiring layout data. A wiring inspection method for a semiconductor integrated circuit, which comprises extracting as data and comparing the data.