JP3473802B2 - Mirror circuit in optical recording / reproducing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mirror circuit in a recorded information reproducing device. The present invention also relates to a mirror circuit including a function of detecting whether or not a reading point for a recording medium such as an optical disk or a magneto-optical disk is on a recording track.

[0002]

2. Description of the Related Art A digital audio disc called a compact disc (CD), a video disc on which an image signal is recorded together with an audio signal, and a so-called C.
In a system that reads and reproduces recorded information on an optical information recording disk such as a D-ROM (hereinafter collectively referred to as an optical disk), an information reading point is generally once for a set number of tracks. It has a track jump function that jumps over to. This track jump operation is executed in a search mode, a scan reproduction mode, etc., and a comparatively small track jump is performed in a pickup forming an information reading point, and a comparison is performed in a slider moving the entire pickup in the disk radial direction. Including significant track jumps.

After the end of the track jump operation, since the tracking servo circuit exceeds the linear control range, it is necessary to devise the settling of the tracking actuator (that is, the tracking servo pull-in). For example, a half-wave brake circuit configured to apply a brake to the tracking actuator by turning on / off the loop switch of the tracking servo loop at an appropriate timing during the jump operation is used. In order to obtain the on / off control timing of the tracking servo in this brake circuit, the information reading point is located on the track of the disk (hereinafter referred to as the on-track state), or the information reading point is out of the track. An on / off track detection signal (hereinafter, referred to as a mirror signal) indicating whether the state (hereinafter, referred to as an off track state) is present is required. That is, depending on the state of the mirror signal at the control timing, it is detected whether the information reading point moves in the direction from the inner circumference to the outer circumference or from the outer circumference to the inner circumference. The signal having the waveform (for example, one of the positive half-wave and the negative half-wave of the tracking error signal) is supplied as a drive signal for the tracking actuator.

During the track jump operation,
In order to recognize how many information reading points actually jump over tracks, the number of on-track states or off-track states indicated by the mirror signal is counted. An example of such a mirror circuit (also called a mirror surface detection circuit) is shown in FIG.

In FIG. 1, a pickup system and its output amplification system (both not shown) are used to read a disk obtained while the information reading point crosses the track in a track jump operation such as a high speed search in which the moving speed is relatively fast. A signal (see FIG. 2A, also referred to as an RF (high frequency) signal) is supplied to the peak hold circuit 11, and its maximum value, that is, a peak value is sequentially held, and an upper envelope signal (see FIG. 2B) is generated. Is generated. The read signal is also supplied to the bottom hold circuit 12, and its minimum value, that is, the bottom value is sequentially held, and the lower envelope signal (see FIG. 2C) is generated. These envelope signals are respectively supplied to the subtractor 13, the level of the lower envelope signal is reduced from the level of the upper envelope signal, and the envelope difference signal (see the solid line in FIG. 2 (d)) of a level corresponding to the result of this subtraction is obtained. Is generated. The envelope difference signal is supplied to the peak hold circuit 14 and peak-held with a relatively large time constant. The hold output of the peak hold circuit 14 is supplied to the coefficient multiplier 15,
The signal is converted or divided into a signal having a level of 2/3 of the held output level, and the divided signal is used as a comparison reference signal (see FIG. 2).
(D) Refer to the broken line) and is supplied to one input terminal of the comparison circuit 16. The output envelope difference signal of the subtractor 13 is also used as a signal to be compared with the comparison reference signal in the comparison circuit 1.
It is also supplied to the other input terminal of 6. The comparison circuit 16 is
The level comparison between the supplied comparison reference signal and the envelope difference signal is performed, and the mirror signal becomes high only when the envelope difference signal is lower than the comparison reference signal (see FIG. 2).
(See (e)) is generated.

FIG. 3 shows the case where the crosstalk of the read signal is 33%, and FIG. 4 shows the case where the crosstalk is 50%. The mirror signal e, the envelope difference signal d ₁ , the comparison reference signal d ₂ and It is a wave form diagram of tracking error signal f, f '. The crosstalk refers to the ratio of the difference between the read signal levels in the on-track state and the off-track state with respect to the maximum amplitude of the read signal.

First, referring to FIG. 3, the envelope difference signal d
The peak level and the bottom level of ₁ are relatively well balanced, and the level of the comparison reference signal d ₂ having a level of about ⅔ of the peak level is approximately the inflection point of the waveform of the envelope difference signal d _1. It becomes a substantially average value (median value) of the peak value and the bottom value. Therefore, it is understood that the mirror signal e obtained based on these signals d ₁ and d ₂ draws a waveform having a duty ratio of about 1: 1.

On the other hand, according to FIG. 4, the bottom level approaches the peak level of the envelope difference signal d ₁ , and the level of the comparison reference signal d ₂ having a level about 2/3 of the peak level is the envelope difference signal d 1. The value is closer to the bottom in the waveform of ₁ . Therefore, it can be seen that the mirror signal e obtained based on these signals d ₁ and d ₂ draws a waveform in which the high level period is considerably shorter than the low level period.

In FIG. 3 and FIG. 4, the tracking error signal f is theoretically a mirror signal e at the rising and falling inflection points of its waveform, that is, the timing at which the error level of the error signal becomes zero (so-called zero cross timing). It is exactly in the middle of the high and low level periods. In the above-described brake circuit, the moving direction of the information reading point is determined depending on whether or not the mirror signal is at the high level at this timing, and the timing is the high or low level period of the mirror signal like the tracking error signal f. If it corresponds to the center of, the determination can be made accurately. The braking drive signal g to the tracking actuator obtained based on this is shown in FIG.

However, the tracking error signal f
When the zero-cross timing is deviated as shown in ‘′, or so-called phase delay occurs, the high-level period of the mirror signal waveform becomes shorter as the crosstalk level increases as shown in FIG. Since the zero-cross timing of the signal is out of the low level period, an error occurs in the determination of the moving direction of the information reading point.

[0011] In Figure 4, by the level of the comparison reference signal d ₂ is also approaching the bottom level of the envelope difference signal d _1, at the noise envelope difference signal d ₁ is riding crosstalk 50% Even if there is, a high level may not appear in the mirror signal. Therefore, in this case as well, an error occurs in the determination of the moving direction of the information reading point, and since no pulse is generated in the mirror signal, it becomes impossible to count the number of moving tracks of the information reading point during the track jump operation. In addition, since it is not possible to determine the moving direction of the information reading point, it is not possible to generate an appropriate braking half-wave drive signal to the tracking actuator, and so-called track slip at the information reading point frequently occurs.

On the other hand, the specific configuration of the bottom hold circuit 12 is shown in FIG. In FIG. 5, the read signal is supplied to the cathode of the diode 31. The anode of the diode 31 is connected to one end of a resistor 32 having a resistance value R _1, and the other end of the resistor 32 is guided to the output end of the bottom hold circuit 12. Further, the other end of the resistor 32 is supplied with a voltage Vcc by a constant voltage source through a resistor 33 having a resistance value R ₂ , and a capacitor 3 having a capacitance C.
It is grounded via 4.

FIG. 6 is used to explain the detailed operation of the mirror circuit including the bottom hold circuit 12. Marks such as pits corresponding to, for example, RLL (Run Length Limited) code converted signals are recorded on the disc. Assuming that the bit period (unit period or basic period) of the original digital signal before the RLL code conversion is T, information is inverted at intervals of 3T to 11T in the mark train.
That is, the RLL code conversion is performed so that the minimum inversion interval of the mark row is 3T and the maximum inversion interval is 11T. A read signal whose level changes or whose waveform is inverted is obtained.

In FIG. 6, in order to simplify the explanation,
The read signal (a) is depicted as a square wave whose waveform is inverted at equal intervals of 11T. Therefore, the read signal (a) is 22T.
It is considered to have a type of high frequency carrier signal component of the period and the low level of the carrier signal to have a low frequency envelope component. Peak hold circuit 11 not described in detail
The output signal (b) holds the level when the read signal (a) shows a high level (upper peak level), and gradually decreases from the held level with a predetermined time constant while the read signal (a) shows other low levels. ) Is generated. The output signal (b) has a level that follows the upper peak level of the read signal, though it has a level reduction leakage due to the time constant, and therefore becomes the upper envelope signal of the read signal.

The bottom hold circuit 12 holds the read signal (a) at a low level (lower peak level) when the read signal (a) shows the low level, and keeps the level at a predetermined time constant while the read signal (a) shows the other high level. An output signal (c) that gradually rises is generated. More specifically, when the read signal (a) becomes low level, a current flows through the resistor 32 and the diode 31 to the input side, so that the capacitor 34 is discharged,
The potential at the output terminal of the bottom hold circuit 12 decreases with the time constant of C · R ₁ and reaches the low level indicated by the input read signal. The time constant of C · R ₁ is set to be sufficiently small, and the output terminal potential macroscopically immediately follows the low level of the read signal. Further, when the read signal (a) becomes high level, a current flows through the resistor 33 to the capacitor 34, the capacitor 34 is charged, and the bottom hold circuit 12
The potential at the output end of C rises with the time constant of C · R ₂ . The time constant of C · R ₂ is set to be relatively large, and the output terminal potential gradually rises. Therefore, even if the read signal becomes high level, the bottom hold circuit 12 can set the output signal level which is not much different from the low level of the held read signal, whereby the read signal becomes low level (lower peak level). The following bottom hold, ie the lower envelope detection of the read signal, is achieved.

The subtractor 13 takes the difference between the upper envelope signal (b) and the lower envelope signal (c) to generate the envelope difference signal d ₁ shown in FIG. 6 (d). The envelope difference signal d ₁ is converted into the signal d ₂ having a level of ⅔ of the peak level through the peak hold circuit 14 and the coefficient multiplier 15 as described above. Then, the levels of both signals are compared in the comparison circuit 16, and a mirror signal (e) having a high level when the envelope difference signal d ₁ exceeds the comparison reference signal d ₂ and a low level when the envelope difference signal d ₁ falls below is obtained. .

In the example of FIG. 6, the high level period and the low level period of the mirror signal (e) are substantially equal in length, and both periods are relatively stable, which is preferable. The reason why such a mirror signal is obtained is that the time constant CR ₂ of the bottom hold circuit 12 is properly set for the read signal. For example, as shown in FIG. 7, when the amplitude change of the read signal is small and the crosstalk is large, the obtained mirror signal (e) does not form a stable high level period. The phenomenon that the low level instantaneously becomes low when the originally high level continues frequently occurs. This is because the time constant CR ₂ is too small for the amplitude change of the lower envelope of the read signal. In this case, if the time constant CR ₂ is set sufficiently large, such an unstable mirror signal should not occur.

However, there is a problem when the time constant CR ₂ is set large. That is, as shown in FIG. 8, when the amplitude change of the read signal is large and the crosstalk is small, the stable low level period of the obtained mirror signal (e) becomes short. More specifically, when the lower envelope of the read signal tends to rise, the charging rate of the capacitor 34 of the bottom hold circuit 12 is small due to the large time constant CR ₂ even when the read signal becomes high level, so the lower envelope signal level Rises only slightly. Therefore, when the read signal is switched to the low level next time, the charging voltage of the capacitor 34 is still lower than the low level of the read signal, and the current does not flow to the input side through the resistor 32 and the diode 31. 34 cannot be discharged so that the lower envelope signal does not follow the low level of the read signal. The capacitor 34 is
Only when the charge voltage is higher than the read signal level, the discharge is performed and the charge voltage is reduced and converges to the charge voltage corresponding to the read signal level. Therefore, until the charge voltage of the capacitor 34 becomes higher than the read signal level, The charging by Vcc through the resistor 33 will be continued. As a result, the envelope difference signal also has a larger portion than the comparison reference signal d ₂ as shown in FIG. 8D, and the low level period of the mirror signal (e) is shortened.

Thus, if the time constant CR ₂ is too large for the read signal, not only the duty of the mirror signal collapses but also if the frequency of the lower envelope of the read signal is too high, the bottom hold circuit 12 causes the read signal to be read. I will not be able to follow.

[0020]

Thus, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an appropriate mirror even if the level of read signals or crosstalk varies. It is to provide a mirror circuit that can generate a signal.

[0021]

Rumi error circuit by the present invention SUMMARY OF THE INVENTION, when the read signal indicates a minimum value is corresponding to the minimum value
Hold level, otherwise hold level?
The lower envelope that gradually increases in level with a time constant
Bottom hold means for generating a read signal and a read signal
Means for generating an upper envelope signal;
Depending on the difference between the bellows signal and the upper envelope signal
To generate an envelope difference signal with different levels
Rope detection means, comparison reference signal and envelope difference
The level is compared with the signal and the level according to the comparison result is set.
A mirror circuit having comparing means for generating a mirror signal for
And has a time constant adjusting means for adjusting the time constant.
However, the time constant adjusting means is configured to detect the lower envelope signal.
No., the amplitude of the envelope difference signal or the read signal
It is characterized in that the time constant is changed according to the level .

[0022] That is, according to the mirror circuit of this, read
When the signal shows a minimum value, the level corresponding to that minimum value
Hold, otherwise have an adjusted time constant
The lower level that gradually increases from the level held by
An envelope signal is generated. Another mirror circuit according to the present invention, when the read signal exhibits a maximum value, is matched to the maximum value.
The level that corresponds to the level
The upper engine whose level gradually decreases with a time constant
Peak hold means for generating a bellows signal and read signal
Means for generating a lower envelope signal,
The difference between the envelope signal and the lower envelope signal
An error that produces an envelope difference signal having a level
The envelope detection means, the comparison reference signal and the envelope
Level comparison with the differential signal and the level according to the comparison result
And a comparison means for generating a mirror signal with
Circuit, a time constant adjusting means for adjusting the time constant
And the time constant adjusting means includes the upper envelope.
Signal, the envelope difference signal or the read signal
The time constant is changed according to the width level .

That is, according to the other mirror circuit,
When the read signal shows a maximum value, the
Holds the bell, otherwise it gives the adjusted time constant
The level gradually decreases from the held level
A side envelope signal is generated. Still another according to the invention
When the read signal shows a minimum value , the mirror circuit of
Holds the level corresponding to the small value, and holds it otherwise.
The level gradually rises from the level with a time constant
Bottom hold means for generating lower envelope signal
And means for generating the upper envelope signal of the read signal
And the lower envelope signal and the upper envelope
Envelope difference signal having a level according to the difference with the signal
An envelope detection means for generating
The level difference is compared with the envelope difference signal and
Comparing means for generating a mirror signal having a level according to
A mirror circuit having:
A constant signal adjusting means, wherein the time constant adjusting means is a command signal
In response to the, the initialization process that sets a predetermined value as the time constant
And the amplitude level of the read signal after the initialization step.
Adjustment step of setting a value according to the above as the time constant
Of the envelope difference signal after the first adjusting step.
Second setting a value corresponding to the amplitude level as the time constant
It is characterized in that the adjustment process is executed.

Yet another mirror circuit according to the present invention is a read
When the signal shows a local maximum, the level corresponding to that local maximum
Holds the time constant from the held level otherwise
Upper envelope signal whose level gradually decreases with
And the lower end of the read signal.
Means for generating a bellows signal and said upper envelope
Level according to the difference between the signal and the lower envelope signal
Envelope detector for generating an envelope difference signal with
Output means, a comparison reference signal and the envelope difference signal
Mira comparing levels and having a level according to the comparison result
Is a mirror circuit having a comparison means for generating a signal.
And having a time constant adjusting means for adjusting the time constant,
The time constant adjusting means sets the time constant in response to a command signal.
After the initialization process, which sets a predetermined value by
And a value corresponding to the amplitude level of the read signal as the time constant
And the first adjusting step, and after the first adjusting step
A value corresponding to the amplitude level of the envelope difference signal is
To execute the second adjustment step, which is set as a time constant
It has a feature.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION The reference signal generating means in the first mirror circuit described above outputs a level signal indicating a value obtained by multiplying a sum value of a peak value and a bottom value of the envelope difference signal by a predetermined coefficient. It is possible to adopt a mode in which the comparison reference signal is used. More specifically, a peak hold circuit that peak-holds the envelope difference signal, a bottom hold circuit that bottom-holds the envelope difference signal, and an adder circuit that adds the output of the peak hold circuit and the output of the bottom hold circuit. The reference signal generating means can be configured by a multiplier that multiplies the output of the adder circuit by a predetermined coefficient. As the predetermined coefficient,
It is preferably 1/2, but other values may be adopted.

When the lower envelope of the read signal has a component according to the on / off track state of the read point, the second mirror circuit is applied. The time constant adjusting means in the second mirror circuit adjusts the time constant according to the maximum change speed of the lower envelope of the read signal, and as one mode thereof, the time constant is adjusted according to the amplitude level of the lower envelope signal. Change the constant.

When the upper envelope of the read signal has a component according to the on / off track state of the read point, the third mirror circuit is applied. The time constant adjusting means in the third mirror circuit adjusts the time constant according to the maximum change speed of the upper envelope of the read signal, and as one mode thereof, adjusts the time constant according to the amplitude level of the upper envelope signal. Just change it.

Both the second and third mirror circuits can adopt a mode in which the time constant is changed according to the amplitude level of the envelope difference signal as the time constant adjusting means. Further, the time constant adjusting circuit may change the time constant according to the amplitude level of the read signal. Further, in the second and third mirror circuits, it is preferable to provide a reference signal generating means that uses the level signal corresponding to the intermediate value between the peak value and the bottom value of the envelope difference signal as the comparison reference signal. Further, as a mode of the time constant adjusting means, an initialization step of setting a predetermined value as the time constant in response to a command signal, and a value corresponding to the amplitude level of the read signal after the initialization step are set to the time constant. And a second adjustment step of setting a value corresponding to the amplitude level of the envelope difference signal as the time constant after the first adjustment step.

[0029]

The present invention will be described in detail below with reference to the drawings. FIG. 9 shows the configuration of a disk recorded information reproducing apparatus to which a mirror circuit of an embodiment according to the present invention is applied.
In FIG. 9, a video disc which is an information recording disc, a CD, a CD-ROM, and a DVD (digital video disc, SD (Super De-
nsity) also called disk 5)
1 is rotationally driven by a spindle motor 52, and its recorded information signal is read by a reading beam from an optical pickup 53. The read information signal is subjected to waveform shaping and amplification in the preamplifier stage 54 and is used as a read signal by a digital signal processor (DS).
P) 55. The DSP 55 decodes the supplied read signal and outputs it as an information signal.

The focus error signal from the preamplifier stage 54 is supplied to the focus equalizer and control circuit 56, and the tracking error signal is supplied to the tracking equalizer circuit 57. The focus equalizer and control circuit 56 equalizes the focus error signal and, based on the defect signal and the equalized focus error signal from the mirror and defect signal generation circuit 58, the read beam of the pickup 53 with respect to the recording surface of the disc 51. In order to perform focus control, a drive signal having a level that causes the reading beam to converge on the recording surface is generated for a drive system including a focus actuator. The tracking equalizer circuit 57 equalizes the tracking error signal, supplies the high frequency component of the equalized tracking error signal to the tracking control circuit 59, and supplies the low frequency component to the slider equalizer and control circuit 60. The tracking control circuit 59 controls the position of the reading beam of the pickup 53 in the disc radial direction with respect to the recording track of the disc 51, based on the high-frequency tracking error component and the defect signal and the mirror signal from the mirror and defect signal generating circuit 58. In order to perform the above, a drive signal of a level is generated for the drive system including the tracking actuator so that the read beam is at the optimum disc radial position. The slider equalizer and control circuit 60 controls a slider motor that positions the disk 51 of the entire pickup in the radial direction, and includes a slider motor to equalize the low-frequency tracking error component and perform slider control based on this. A drive signal is generated for the drive system.

The mirror / defective signal generation circuit 58 includes a mirror circuit, which will be described later, which is a feature of this embodiment, and based on the read signal from the preamplifier stage 54, the read signal is sent to the disk 5 by the disk 5.
When there is a disturbance component such as so-called dropout due to scratches, stains, dirt, etc. in 1), it is detected and a defect signal is output, or on-track of the information reading point in the track jump operation such as search or scan reproduction mode. The mirror signal indicating the state and the off-track state is output. The DSP 55 also detects a sync signal in the read RF signal and generates a spindle error signal based on the reference sync signal from a reference signal generating circuit (not shown) and the reproduced sync signal obtained by the detection, and the spindle equalizer. And to the control circuit 61. The spindle equalizer and control circuit 61 performs equalizing on the supplied spindle error signal, and reads the drive system including the spindle motor to control the rotation of the spindle motor 52 with respect to the disk based on the equalized spindle error signal. A drive signal having a level such that the signal is synchronized with the reference synchronization signal is generated.

The configuration of the mirror circuit included in the mirror and defect signal generation circuit 58 is shown in FIG. 10, the same parts as those in FIG. 1 are designated by the same reference numerals, and the details thereof will be omitted. The characteristics of this mirror circuit are as follows. The envelope difference signal of the read signal, that is, the output signal of the subtracter 13 is the peak hold circuit 1.
4 and the comparison circuit 16, and is also supplied to the bottom hold circuit 21. The bottom hold circuit 21
The minimum value of the envelope difference signal, that is, the bottom level is held with a relatively large time constant. The hold output of the bottom hold circuit 21 is supplied to the adder 22, and is added to the peak hold output of the envelope difference signal from the peak hold circuit 14. The addition output of the adder 22 is supplied to the coefficient multiplier 23, converted into or divided into a signal having a level of 1/2 of the addition output level, and the divided signal is input to one of the comparison circuits 16 as a comparison reference signal. Supplied to the terminal.

According to this structure, the average level of the peak hold level and the bottom hold level of the envelope difference signal is obtained from the multiplier 23, and this average level is set as the comparison reference signal of the comparison circuit 16. That is, while the comparison reference signal level in the mirror circuit shown in FIG. 1 is set only by the peak hold level of the envelope difference signal, the comparison reference signal level in the present mirror circuit is not limited to the peak hold level of the envelope difference signal. It is also set by the bottom hold level.

To describe the merits of the mirror circuit of this embodiment, the waveform diagram of FIG. 11 is used. FIG. 11 shows the mirror signal e ′, the envelope difference signal d ₁ , the comparison reference signal d ₂ ′, and the tracking error signal in the mirror circuit of this embodiment when the crosstalk of the same read RF signal as in FIG. 4 is 50%. It is a wave form diagram of f and f '. According to FIG. 11, the envelope difference signal d ₁
Although the bottom level V _B is considerably close to the peak level V _P of the reference level d _{P, the} level of the comparison reference signal d ₂ ′ having the average level (V _P + V _B ) / 2 of the peak level and the bottom level is the envelope difference signal. It is almost equal to the value of the inflection point of the waveform of d ₁ . Accordingly mirror signal e'obtained based on these signals d ₁ and d ₂ 'is approximately 1 duty ratio: It can be seen that 1 Draw become like waveform.

On the other hand, even if the same case as in FIG. 3 is applied to the mirror circuit of the present embodiment, the comparison reference signal level indicates the center between the peak value and the bottom value of the envelope difference signal, so the duty ratio is 1: An error signal of 1 is obtained. Further, even in the case of crosstalk having other values, an error signal with a duty ratio of 1: 1 is obtained in the same manner. Therefore, the mirror circuit of the present embodiment always has a duty ratio of 1: 1, even if the crosstalk changes.
The error signal of 1 will be maintained.

Thus, when the ideal tracking error signal f having no time lag is generated, the rising and falling inflection points of the waveform, that is, the timing at which the error level of the error signal becomes zero (so-called zero cross timing). Is positioned exactly at the center of the high-level period and the low-level period of the mirror signal, so that the moving direction of the information reading point can be accurately determined in the above-mentioned brake circuit, and the zero crossing like the tracking error signal f ′ can be performed. Even if the timing shifts and the phase delay occurs, the duty ratio of 1: 1 is maintained, so that the zero-cross timing of the tracking error signal, which should detect the high level of the mirror signal, does not deviate during the low level period of the mirror signal. It is possible to accurately determine the moving direction of the reading point.

Further, the level of the comparison reference signal d ₂ 'approaches the bottom level of the envelope difference signal d _1, even if noise is riding on the envelope difference signal d _1, unless to a great extent deteriorated extreme crosstalk The high level does not disappear in the mirror signal. Therefore, even in this case, the movement direction of the information reading point can be accurately and stably determined, and a pulse is reliably generated in the mirror signal, so that the number of moving tracks of the information reading point during the track jump operation is counted. It doesn't stop. Thus, a proper half-wave drive signal for braking to the tracking actuator can be generated by the accurate and stable determination of the moving direction of the information reading point, and so-called track slippage at the information reading point can be eliminated.

In the above embodiment, the comparison reference signal level is the average value of the peak level and the bottom level of the envelope difference signal. However, the comparison reference signal level is not limited to this, and it may be between the two levels depending on the nature of the read signal waveform. Other values may be used. However, the comparison reference signal level must be generated so as to depend not only on the peak level of the envelope difference signal but also on the bottom level. That is, the comparison reference signal according to the present invention essentially has a level corresponding to or proportional to the sum of the peak value and the bottom value of the envelope difference signal, and is largely different in configuration from the conventional mirror circuit as shown in FIG. It can be said that the bottom value of the envelope difference signal also plays a role in determining the comparison reference signal level.

In the above embodiment, two hold circuits, an adder and a multiplier are used to obtain the average value of the peak level and the bottom level of the envelope difference signal, but the present invention is not limited to this. It goes without saying that various methods for obtaining such average values are conceivable within the range that can be easily conceived by those skilled in the art. Next, a mirror circuit of another embodiment according to the present invention will be described.

FIG. 12 shows the structure of such a mirror circuit, and the same parts as those in FIG. 10 are designated by the same reference numerals. The mirror circuit in FIG. 12 digitally processes the read signal. Therefore, the read signal from the preamplifier stage 54 is digitized by the A / D converter 70, and the blocks 11, 12, 13, 14, 16, 21, 22, 22 are read.
A digital circuit configuration is applied to each circuit of 3. Further, in the bottom hold circuit 12, the time constant corresponding to CR ₂ described above is controlled by the control signal from the time constant adjusting circuit 71. The time constant adjustment circuit 71 responds to the adjustment command signal and responds to the peak hold circuit 14 and the bottom hold circuit 2.
A control signal is generated in the bottom hold circuit 12 so as to have an optimum time constant for the read signal based on the output signal of 1.

The specific processing of the bottom hold circuit 21 is as follows.
The procedure is as shown in FIG. In FIG. 13, the bottom hold process is called and executed as a subroutine at a predetermined sampling cycle in a main routine (not shown). When this subroutine is called, first, the input signal (read signal) level Vin of the bottom hold circuit 12 is compared with the output signal level Vout (step S01). When it is determined by this comparison that the input signal level Vin is smaller than the output signal level Vout, the output signal level Vout is set to the input signal level Vout.
This is matched with in (step S02), and this routine ends.

FIG. 14 shows how the input signal level Vin is directly used as the output signal level Vout. That is, in step S01, when the input signal sample point p1 and the output signal sample point q1 are compared in level, Vin <Vout, and thus the bottom hold circuit 12 changes the value of the output signal level Vout to the previous value. The value of the sampling point q1 is changed to the value of the input signal level Vin of the sampling point p1. Next, when the subroutine of FIG. 13 is called again, the level of the sampling point p2 of the input signal and the sampling point q2 of the output signal are compared in step S01. At this time, the value of the sampling point q2 is the sampling point p1.
On the other hand, since the value of the sampling point p2 is smaller than the value of the previous sampling point p1 and Vin <Vout, the bottom hold circuit 12 changes the value of the output signal level Vout to that of the sampling point q2 up to that point. The value is changed to the value of the input signal level Vin at the sampling point p2. By repeating such an operation, the output signal follows the bottom level of the input signal.

Returning to FIG. 13 again, when it is determined in step S01 that the input signal level Vin is equal to or higher than the output signal level Vout, whether the input signal level Vin is higher than the output signal level Vout by V0. It is determined whether or not (step S03). V0 is 1 for judging whether the input signal transits to the peak.
It is a predetermined value per sampling cycle. Step S0
3, the input signal level Vin is equal to the output signal level Vou
If it is determined that V0 is not larger than t, step S
Move to 02. That is, when Vin is equal to or higher than Vout but equal to or lower than Vout + V0, the output signal level Vout is made to match the input signal level Vin as in the above case, and this routine is finished.

This state is shown in FIG. That is, in step S01, the sampling point p1 of the input signal
And the output signal sample point q1 is compared in level,
Since Vin <Vout, the bottom hold circuit 12
The value of the output signal level Vout is the sampling point q
The value of 1 is changed to the value of the input signal level Vin at the sampling point p1. Next, when the subroutine of FIG. 13 is called again, in step S01 the sampling point p2 of the input signal
And the sampling point q2 of the output signal are compared in level. At this time, the value of the sampling point q2 is the value of the sampling point p1, while the value of the sampling point p2 is larger than the value of the previous sampling point p1 and Vin> Vout, so that the step S03 is performed.
Move to. However, the value of sample point p2 is p1 (q2)
V0 is not larger than the value of. Therefore step S03
To step S02, the bottom hold circuit 12
Changes the value of the output signal level Vout from the value at the sampling point q2 until then to the value of the input signal level Vin at the sampling point p2. In this way, steps S01, S03, S
By sequentially repeating 02, the output signal follows the bottom level of the input signal even when the bottom of the input signal gradually increases.

Returning to FIG. 13 again, in step S03, the input signal level Vin is higher than the output signal level Vout by V.
If it is determined to be larger by 0, the predetermined value X is added to the previous value Vout to obtain a new value Vout (step S04),
This routine ends. Where X is CR as described above
Corresponding to the time constant of ₂ , the output signal level increases with the slope determined by this X while the input signal reaches the peak. This state is shown in both FIG. 14 and FIG. That is, when the sample point pn of the input signal and the sample point qn of the output signal are compared in level in step S03, Vin> Vout + V0, so the bottom hold circuit 12 sets the value of the output signal level Vout to that level. The sampling point qn of the above is increased by a predetermined value X. Next, when the subroutine of FIG. 13 is called again, the sampling point pn + of the input signal is obtained in step S03.
The level of 1 is compared with the sample point qn + 1 of the output signal. Again, since Vin> Vout + V0, the bottom hold circuit 12 sets the value of the output signal level Vout to a value larger than the value of the sampling point qn + 1 by the predetermined value X. By repeating such an operation, it is possible to obtain an output signal that increases by a predetermined value X in each sampling period without following the input signal while it reaches its peak.

If the predetermined value X corresponding to the time constant is set in, for example, a predetermined register of a plurality of bits in the bottom hold circuit 12, it is possible to easily change the value by rewriting the contents of this register. Can be tightened. This is one of the advantages of the bottom hold circuit 12 being a digital circuit. For example, when the bottom hold circuit 12 is configured by an analog circuit, its circuit components are basically fixed, and therefore, in order to achieve a fine change of the time constant, the bottom hold circuit has a number of time constants to be provided. Since a circuit must be provided, the circuit scale becomes large, which is disadvantageous in terms of circuit space and manufacturing cost. On the other hand, if the circuit space and the manufacturing cost are not restricted, this is not the case.

Next, the operation of the time constant adjusting circuit 71 will be described. FIG. 16 shows a procedure of processing executed mainly by the time constant adjusting circuit 71. The time constant adjustment circuit 71
In response to the adjustment command signal from the control circuit (not shown), FIG.
The process of is executed. The adjustment command signal is a timing signal for optimizing the time constant of the sample hold circuit 12, and this timing is appropriate when the following conditions are satisfied.

1) When the focus servo of the read light on the recording surface of the disk 51 is on 2) When the tracking servo of the read light on the recording track of the disk 51 is off, these conditions 1) and 2) are satisfied. 2 and 6-
It is possible to obtain a read signal (track crossing signal) having a waveform as shown in FIG.

More specifically, the above conditions are satisfied during so-called setup of the disc player as shown in FIG. 9, during high-speed transfer of the pickup 53, during single or multi-track jump of the information reading point, and the like. Setup is performed every time the disc to be read changes. Normally, at the time of setup, pickup 5
The reading light is focused on the recording surface of the disc 51 at one or a plurality of predetermined positions where 3 takes a home position, and after the focusing operation is completed, the disc 51 is recorded.
The tracking servo of the reading light is activated for the recording track. Therefore, if the adjustment command signal is generated and the process of FIG. 16 is executed after the focusing is completed, and the tracking servo is started when this is completed, the above condition is satisfied. Also, pickup 5
The high-speed transfer of 3 is applied to a so-called long search mode and the like, and the tracking servo is turned off while the focus servo is kept on, so that the above condition is satisfied. Further, the track jump is applied to a so-called scan reproduction mode, double speed reproduction mode, or the like, and the focus servo is turned on and the tracking servo is turned off during the track jump, so that the above condition is satisfied.

Thus, when the adjustment command signal is generated when the above conditions are satisfied, the time constant adjusting circuit 71 receives this and first initializes the time constant (step S1). In this initialization, in preparation for the first and second adjustments, which will be described later, the time constant obtained last time by performing the time constant adjustment processing of FIG. 16 is used again as it is or set as a default value. A control signal is generated in the bottom hold circuit 12 to use the time constant. A control signal for determining the predetermined value X is supplied to the bottom hold circuit having the digital circuit configuration as described above.

An example of the default time constant will be described. For the sake of simplicity, it is assumed that the standard read signal level is 1 volt (see FIG. 2A) and the crosstalk is 20% (redbook standard is 50% or less). From these values, it is assumed that the amplitude of the lower envelope of the read signal is 0.8 volts when the read point crosses the track with the tracking servo off (FIG. 2).
(See (c)). If the lower envelope is frequency f, then
ω = 2πf and the lower envelope is

[0052]

## EQU00001 ## It changes with 0.8 sin .omega.t (1). In this case, the maximum change speed of the lower envelope is

[0053]

[Expression 2] 0.8ω = 1.6πf [V / sec] (2) When the maximum frequency of the lower envelope is fmax, the maximum change speed of the lower envelope that the bottom hold circuit 12 should follow is

[0054]

(3) 1.6πfmax (3) Therefore, if fmax is determined as a standard value, the maximum rate of change can be obtained. fmax = 10 [KH
z], the maximum rate of change is approximately 50 [K
V / sec] is derived. In step S1, this value is adopted as the time constant τ set in the bottom hold circuit 12, and a control signal indicating the value of X [V / 1 sample] corresponding thereto is generated. The bottom hold circuit 12 rewrites the contents of the register for holding X according to this control signal. As a result, a time constant is set in the bottom hold circuit 12, which is assumed to be a target for reading a standard disk and is assumed to obtain an approximately correct mirror signal when the disk is read by a standard operation. Become. In addition, the reason why the time constant τ is set to the maximum change speed of the lower envelope is shown in FIG. 8 so that the time constant is not too small for the amplitude change of the lower envelope as shown in FIG. This is to prevent the time constant from being too large with respect to the amplitude change of the lower envelope. In other words, considering only FIG. 7, the larger the time constant, the better. However, if it is too large, something like that in FIG. 8 will occur. The value corresponding to the maximum change speed of the side envelope is set as the time constant. Generally, the time constant τ is equal to or slightly smaller than the maximum change rate.

After step S1, a standby state is maintained for a predetermined time (step S2), and after the standby time has passed, the process proceeds to the first adjustment routine (step S3). In the description so far, the focus servo of the reading light is turned on before the process of FIG. 16 is executed, but since the time constant can be set in step S1 regardless of the focus servo, the reading servo is performed between step S2. The light focus servo may be turned on. Also, step S2
The standby time is set so that the bottom hold circuit 12 operates stably. If the bottom hold circuit 12 does not require time for stable operation and it is not necessary to turn on the focus servo in step S2, You may make it transfer from S1 to step S3 immediately.

In the first adjustment processing of step S3, the read signal having the waveform as shown in FIG. 2A has already been obtained as the focus servo is operated, and the second stage peak hold circuit 14 outputs the read signal. The peak level of the envelope difference signal, that is, the amplitude level of the read signal when on-track (see (a) and (d) of FIG. 2 and V _P ) is the time constant adjusting circuit 7.
1 is being supplied. Time constant adjustment circuit 71, the V _P
Based on the maximum rate of change

[0057]

Equation 4] again grasped as 1.6V _P πfmax ... (4), generates a control signal to the bottom hold circuit 12 so that constant τ and a predetermined value X when corresponding to this value is set. When the first adjustment is performed in this way and is completed, the standby state is again set for the predetermined time (step S
4) After the waiting time has passed, the process proceeds to the second adjustment routine (step S5). The waiting time in step S4
The bottom hold circuit 12 is designed to operate stably, and if the bottom hold circuit 12 does not require time for stable operation, the operation immediately starts from step S3.
You may make it transfer to 4.

In the first adjustment processing of step S3, the amplitude level of the read signal from the second-stage peak hold circuit 14 and the bottom level of the envelope difference signal from the second-stage bottom hold circuit 15, that is, when the read signal is off-track. Amplitude level (see (a) and (d) of FIG. 2, V _B )
And are supplied to the time constant adjusting circuit 71. The time constant adjusting circuit 71 determines the maximum change speed based on these V _P and V _B.

[0059]

Equation 5] again grasped as _{2 (V P -V B) πfmax} ... (5), generates a control signal to the bottom hold circuit 12 so that constant τ and a predetermined value X when corresponding to this value is set. After the second adjustment is performed in this way,
It is determined whether or not the second adjustment process has been performed N times in this time constant adjustment routine (step S6). If it has not been performed N times, the process proceeds to step S4, and if it has been performed N times, this time constant adjustment routine ends. After the completion of the time constant adjustment routine, for example, the tracking servo is turned on to shift to the reproduction mode.

The reason why the second adjustment process is executed a plurality of times is that the more the second adjustment process is performed, the more the time constant suitable for the read signal is obtained. That is, the above formula is based on V _P and V _B from the peak hold circuit 14 and the bottom hold circuit 15, and from this formula, it is true that the V _P and V _B are truly optimum unless they are truly correct. Time constant is not obtained. Since the truly correct V _P and V _B can be obtained only when the truly optimum time constant is set in the bottom hold circuit 12, in order to do so, the second adjustment process is performed several times. It is necessary to converge to a truly optimal time constant. Therefore, N used in the time constant adjustment routine is
The larger the value, the better. However, if the adjustment time is too long, the operation of other players will be hindered, and the shorter the adjustment time, the better. In view of these points, N is set to a number that provides a time constant sufficiently suitable for the read signal.

Thus, as can be seen from the above description, the comparison reference signal has a level according to the intermediate value between the peak value and the bottom value of the envelope difference signal of the read signal, and the read signal shows the minimum value. When it holds the level corresponding to the minimum value, otherwise, it should be configured to generate a lower envelope signal whose level gradually rises from the held level with an adjusted time constant. This makes it possible to accurately count the tracks that the information reading point crosses in a track jump operation where the moving speed is relatively fast, such as high-speed search (a mirror signal that can identify the on-track and off-track states is obtained. However, even if the level of the read signal changes, a proper mirror signal can be generated and the crosstalk of the read signal changes. The duty ratio of the mirror signal even if it can be kept constant to an appropriate value. Especially, CD-ROM discs and DV whose recording density and access speed are increasing.
It is suitable for an information reproducing apparatus that performs high-speed search for D and the like.

In the above description, the embodiment in which the lower envelope of the read signal has a component according to the on / off track state of the read point has been described. On the contrary, the upper envelope of the read signal has the read point on. The mirror circuit (the third mirror circuit) can be configured in the same manner as in the above embodiment even when the component has a component according to the off-track state. In the embodiment shown in FIG. 12, the mirror circuit is composed of a digital circuit. However, in principle, even if the mirror circuit is composed of an analog circuit, a unique effect can be obtained.

[0063]

As described in detail above, according to the mirror circuit of the present invention, an appropriate mirror signal can be generated even if the level or crosstalk of the read signal changes.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional mirror circuit.

2 is an output signal waveform diagram of each part of the mirror circuit of FIG.

3 is a waveform diagram of an envelope difference signal, a comparison reference signal, a mirror signal, a tracking error signal, and a brake tracking actuator drive signal when the crosstalk of the read signal is 33% in the mirror circuit of FIG.

4 is a waveform diagram of an envelope difference signal, a comparison reference signal, a mirror signal, a tracking error signal, and a brake tracking actuator drive signal when crosstalk of a read signal is 50% in the mirror circuit of FIG.

5 is a circuit diagram showing a specific configuration of a bottom hold circuit in the mirror circuit of FIG.

6 is a standard operation waveform diagram of each part of the mirror circuit when the bottom hold circuit of FIG. 5 is applied.

7 is an operation waveform diagram of each part in large crosstalk of the mirror circuit when the bottom hold circuit of FIG. 5 is applied.

FIG. 8 is an operation waveform diagram of each part at a large bottom hold time constant of the mirror circuit when the bottom hold circuit of FIG. 5 is applied.

FIG. 9 is a diagram showing a configuration of a disc recording information reproducing device to which a mirror circuit according to the present invention is applied.

FIG. 10 is a block diagram showing the configuration of a mirror circuit according to an embodiment of the present invention.

11 is a waveform diagram of an envelope difference signal, a comparison reference signal, a mirror signal, a tracking error signal, and a brake tracking actuator drive signal when the crosstalk of the read signal is 50% in the mirror circuit of FIG.

FIG. 12 is a block diagram showing the configuration of a mirror circuit of another embodiment according to the present invention.

13 is a flowchart showing a signal processing procedure of a bottom hold circuit in the mirror circuit of FIG.

14 is a waveform chart showing how the bottom hold circuit in the mirror circuit of FIG. 11 performs signal processing when the bottom level of the read signal tends to decrease.

FIG. 15 is a waveform diagram showing how the bottom hold circuit in the mirror circuit of FIG. 11 performs signal processing when the bottom level of the read signal tends to rise.

16 is a flowchart showing a processing procedure of time constant adjustment of the mirror circuit of FIG.

[Explanation of symbols]

11 Peak hold circuit 12 Bottom hold circuit 13 Subtractor 14 Peak hold circuit 16 Comparison circuit 21 Bottom hold circuit 22 adder 23 coefficient multiplier 31 diode 32,33 Electric resistor 34 capacitor 51 Information recording disc 52 Spindle motor 53 pickups 54 preamplifier stage 55 Digital Signal Processor 56 Focus equalizer and control circuit 57 Tracking equalizer circuit 58 Mirror and defect signal generation circuit 59 Tracking control circuit 60 Slider equalizer and control circuit 61 Spindle equalizer and control circuit 70 A / D converter 71 Time constant adjustment circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichiro Haraguchi 25-1, Nishimachi, Yamada, Kawagoe, Saitama Prefecture 1 Pioneer Co., Ltd., Kawagoe factory (72) Inventor Kamo Kawana 25, Nishida, Yamada, Kawagoe, Saitama 1 Pioneer Co., Ltd. Kawagoe Plant (72) Inventor Takehiro Takada 25 Nishi Nishimachi, Yamada, Kawagoe City, Saitama Prefecture 1 Pioneer Co., Ltd. Kawagoe Plant (56) Reference JP-A-63-206975 (JP, A) Kaihei 8-124176 (JP, A) JP-A-7-129972 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 7/085 G11B 7/00

Claims (12)

(57) [Claims] 1. When the read signal shows a minimum value, the minimum value
Holds the level corresponding to the value, otherwise holds
The level gradually rises with a time constant
Bottom hold means for generating a side envelope signal,
Means for generating an upper envelope signal of the read signal;
The lower envelope signal and the upper envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
And a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means changes the time constant according to an amplitude level of the lower envelope signal. Mirror circuit. 2. When the read signal shows the maximum value, the maximum value
Holds the level corresponding to the value, otherwise holds
The level gradually decreases from the level with a time constant.
Peak hold means for generating a side envelope signal,
A means for generating a lower envelope signal of the read signal;
The upper envelope signal and the lower envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
And a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means changes the time constant according to an amplitude level of the upper envelope signal. /> to Rumi error circuit. 3. When the read signal shows a minimum value, the minimum value
Holds the level corresponding to the value, otherwise holds
The level gradually rises with a time constant
Bottom hold means for generating a side envelope signal,
Means for generating an upper envelope signal of the read signal;
The lower envelope signal and the upper envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
And a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means changes the time constant according to an amplitude level of the envelope difference signal.
Rumi error circuit. 4. When the read signal shows a maximum value, the maximum value
Holds the level corresponding to the value, otherwise holds
The level gradually decreases from the level with a time constant.
Peak hold means for generating a side envelope signal,
A means for generating a lower envelope signal of the read signal;
The upper envelope signal and the lower envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
A mirror circuit having a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means is an amplitude of the envelope difference signal.
Characterized in that the time constant is changed according to the level
Mirror circuit. 5. When the read signal shows a minimum value, the minimum value
Holds the level corresponding to the value, otherwise holds
The level gradually rises with a time constant
Bottom hold means for generating a side envelope signal,
Means for generating an upper envelope signal of the read signal;
The lower envelope signal and the upper envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
A mirror circuit that has a constant adjusting means when adjusting the time constant, the time constant adjusting means, features and to Rumi altering the time constant according to the amplitude level of the read signal Ra circuit. 6. The maximum when the read signal shows a maximum value
Holds the level corresponding to the value, otherwise holds
The level gradually decreases from the level with a time constant.
Peak hold means for generating a side envelope signal,
A means for generating a lower envelope signal of the read signal;
The upper envelope signal and the lower envelope signal
Generate an envelope difference signal with a level that depends on the difference between
The envelope detection means, the comparison reference signal and the
Level comparison was made with the bellows difference signal, and the results were compared.
Comparing means for generating a mirror signal having a level
And a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means responds to the amplitude level of the read signal.
Mirror times characterized by changing the time constant
Road. 7. Any of the preceding claims, characterized in 6 that has a reference signal generating means and the comparison reference signal level signal corresponding to an intermediate value between the peak value and the bottom value of the envelope difference signal The mirror circuit according to item 1 . 8. The reference signal generating means uses a level signal indicating a value obtained by multiplying a sum value of a peak value and a bottom value of the envelope difference signal by a predetermined coefficient as the comparison reference signal. The mirror circuit according to claim 7 . 9. The reference signal generating means includes a peak hold circuit for peak-holding the envelope difference signal, a bottom hold circuit for bottom-holding the envelope difference signal, an output of the peak hold circuit, and a bottom hold circuit. An adder circuit for adding the output and
9. The mirror circuit according to claim 8 , further comprising a multiplier that multiplies an output of the adder circuit by a predetermined coefficient. 10. The mirror circuit according to claim 8 , wherein the predetermined coefficient is 1/2. 11. When the read signal shows a local minimum value, that local
Holds the level corresponding to the small value, and holds it otherwise.
The level gradually rises from the level with a time constant
Bottom hold means for generating lower envelope signal
And means for generating the upper envelope signal of the read signal
And the lower envelope signal and the upper envelope
Envelope difference signal having a level according to the difference with the signal
An envelope detection means for generating
The level difference is compared with the envelope difference signal and
Comparing means for generating a mirror signal having a level according to
A mirror circuit have a have a constant adjusting means when adjusting the time constant, the time constant adjusting means comprises an initialization step of setting the predetermined value as the time constant in response to a command signal, A first adjusting step of setting a value according to the amplitude level of the read signal as the time constant after the initialization step, and a value of the amplitude level of the envelope difference signal after the first adjusting step . It features and to Rumi error circuit to perform a second adjustment step of setting a value as the time constant. 12. When the read signal shows a maximum value, the maximum value
Holds the level corresponding to the maximum value, and holds it otherwise.
Level gradually decreases with a time constant from the level
Peak hold means for generating upper envelope signal
And means for generating the lower envelope signal of the read signal
And the upper envelope signal and the lower envelope
Envelope difference signal having a level according to the difference with the signal
An envelope detection means for generating
The level difference is compared with the envelope difference signal and
Comparing means for generating a mirror signal having a level according to
And a time constant adjusting means for adjusting the time constant, wherein the time constant adjusting means responds to a command signal by the time constant.
Initialization step for setting a predetermined value as
After that, the value according to the amplitude level of the read signal is set to the time
Of the first adjusting step, which is set as a number, and the first adjusting step.
After that, the value according to the amplitude level of the envelope difference signal is changed to
Performing a second adjusting step of setting the time constant
And a mirror circuit.