JP3469176B2 - Saturation value detector - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a characteristic measuring device for measuring characteristics of various electronic components and electronic devices, and more particularly,
The present invention relates to a saturation value detection device that detects a saturation value of an output signal of a measurement target. In other words, the present invention relates to a technique effective in quickly and automatically measuring linearity while replacing linear functional elements such as an amplifier and an analog switch.

[0002]

2. Description of the Related Art Output characteristics are one of the characteristics of various electronic components and electronic devices. This output characteristic indicates the relationship between the signal level of the measurement signal (input signal) applied to the input end of the measurement target such as an electronic component or electronic device and the signal level of the output signal output from the output terminal of the measurement target. . Generally, the input signal level and the output signal level show a linear relationship, but when the input signal level exceeds a certain allowable level, the input signal level becomes non-linear and the output signal level is saturated. Furthermore, increasing the input signal level decreases the output signal level.

Therefore, it is important to measure the saturation value, which is the maximum output value in an object to be measured such as electronic parts and electronic equipment, and the input value for this saturation value.

The saturation value detecting device for detecting the saturation value of the measuring object is constructed as shown in FIG. The measurement signal a having the signal level I output from the measurement signal generator 1
Is applied to the measurement target 2 such as an electronic component or an electronic device.
The output signal b having the signal level P output from the measurement target 2 is input to the measuring device 3. A measurement control device 5 composed of, for example, a personal computer is connected to the measuring instrument 3 via a GP-IB or VXI bus 4 which is a standard interface bus of the measurement system. Measuring instrument 3
Measures the signal level P of the output signal b of the measuring object 2, converts the signal level P into data (language) that can be understood by the measurement control device 5 composed of a personal computer, and then, via the bus 4. It is sent to the measurement control device 5. The measurement signal generator 1 is also connected to the measurement control device 5 via a bus 4 of GP-IB or VXI.

When the measurement control device 5 receives the signal level P of the output signal b of the measurement object 2 from the measuring device 3, based on the signal level P of this output signal b, the measurement signal a of the measurement signal a to be applied to the measurement object 2 is measured. The signal level I is determined, and the data of this new signal level I is transferred to the measurement signal generator 1 via the bus 6.
Transmit to. The measurement signal generator 1 applies the measurement signal a having the signal level I corresponding to the data of the signal level I received from the measurement control device 5 to the measurement object 2.

The measurement control device 5 which is a personal computer of the saturation value detecting device having the above-described configuration executes the process of detecting the saturation value of the output signal b of the measuring object 2 based on the flow chart shown in FIG.

First, an initial value I ₀ of the signal level I of the measurement signal a output from the measurement signal generator 1 (index n =
The signal level at 0:00) and the increment ΔI are set (S1).
Then, the index n is initialized (n = 0) (S
2). The measurement signal a to be output, that is, the signal level I _n of the input signal to the measurement target 2 is set to the measurement signal generator 1 (S3).

The signal level P _n of the output signal b of the measuring object 2 measured by the measuring device 3 is read (S4). Then, the previous signal level _Pn-1 read in the previous time (n = n-1) stored in the previous value memory is read (S5) and compared with the current signal level _Pn (S6). If the current signal level P _n is higher, the current signal level P _n is set in the previous value memory (P _n-1 = P _n ) (S7). Then, the index n is updated (S8), and the signal level I _n of the measurement signal a is updated (I _n = I _n + ΔI) in S9. Then, the process returns to S3, and the updated signal level I _n (output value) is set in the measurement signal generator 1.

In S6, when the signal level P _n of the output signal b measured this time becomes equal to or lower than the signal level P _{n-1 of} the output signal b measured last time, the signal level P of the output signal b exceeds the saturation value. Therefore, the saturation value P _S is approximately calculated by the following formula (S10).

PS = (P _n + P _n-1 ) / 2 FIG. 5 shows the output characteristic showing the relationship between the signal level I of the measurement signal (input signal) a and the output signal b in the measurement object 2, and FIG. The calculation procedure of the saturation value P _S shown in the flowchart is shown.

[0011]

However, the saturation value detecting device shown in FIG. 4 still has the following problems to be solved.

That is, since the measuring device 3 and the measurement control device 5 are connected by the GP-IB or VXI bus 4, the measuring device 3 measures the signal level of the output signal b of the measured object 2. It is necessary to convert P into data (language) that the measurement control device 5 can understand and send it to the measurement control device 5 via the bus 4.

For example, when the transfer rate of the GP-IB interface is verified, the transfer time of the GP-IB command is 5 ms per command. Moreover, 1 ms is required for each command of the measurement control device 5. Furthermore, it takes 5 ms to transmit a command from the measurement control device 5 to the measurement signal generator 1, and the measurement signal generator 1 interprets the command from the measurement control device 5 and outputs the measurement signal. Time is required to set the signal level I of a to the value corresponding to this command.

In this way, the measurement signal for the measurement object 2 is obtained.
Setting the signal level I of a, the output signal b of the measurement target 2
No. Level P analysis is all done by software.
Then, for example, in order to improve the measurement accuracy, the value of ΔP is
If it is set small, the saturation value P _SThe number of measurements required to obtain
However, there is a problem in that the measurement time is increased and the measurement time is increased.

The present invention has been made in view of the above circumstances, and includes a comparator for comparing a previous value and a current value in synchronization with a clock, and a count-up circuit for increasing the signal level of a measurement signal. It is an object of the present invention to provide a saturation value detection device that can significantly reduce the measurement processing time of the saturation value for the measurement target by providing the above. Moreover, it aims at contributing to the automatic measurement of the linearity of a functional element by this.

[0016]

In order to solve the above-mentioned problems, a saturation value detecting device of the present invention is a measuring signal generator for outputting a measuring signal to be applied to a measuring object, and a control applied from the outside. A gain adjustment circuit that controls the level of the measurement signal according to the signal value and applies it to the measurement target, a level detector that detects the level of the output signal of the measurement target, and a clock generation circuit that outputs a clock signal with a fixed period And an A / D converter for A / D converting the level detected by the level detector into a digital output signal value in synchronization with the clock signal,
In synchronization with the clock signal, the output signal value of the current clock cycle A / D converted by the A / D converter is compared with the output signal value of the previous clock cycle, and the previous output signal value is A comparator that outputs a count-up stop signal when the output signal value is exceeded, and a control signal of a value corresponding to the count value that counts up by receiving a clock signal and increases, and applies to the gain adjustment circuit. A count-up circuit for stopping the increase of the count value when a count-up stop signal is inputted from the comparator, and the A / D immediately after the count-up stop signal is outputted from the comparator.
The output signal value A / D converted by the converter is extracted as the saturated output value of the measurement target.

In the saturation value detecting device configured as described above, a gain adjusting circuit is inserted between the measurement signal generator and the measurement object. The signal level of the measurement signal input to the measurement target is controlled by this gain adjustment circuit.

The signal level of the measurement signal output from the gain adjusting circuit automatically increases in accordance with the count value of the count-up circuit whose count value is incremented in synchronization with the clock of the clock signal.

The signal level of the output signal to be measured is detected by the level detector and A / D converted by the A / D converter in synchronization with the clock of the clock signal. Then, the comparator compares the output signal value (output signal level) of this clock cycle with the output signal value (output signal level) of the previous clock cycle, and the output signal value of this clock cycle is When it falls below the output signal value of the cycle, a count-up stop signal is output to the count-up circuit.

Therefore, the A / D-converted output signal level at the time when the count-up stop signal is output becomes the saturation value. Further, the signal level of the measurement signal to the measurement object corresponding to the saturation value can be obtained from the count value of the count-up circuit at this point.

As described above, since the setting of the signal level of the measurement signal for the measurement target and the analysis of the output signal of the measurement target are all performed by hardware, the measurement processing efficiency for the measurement target can be improved.

Another aspect of the present invention is that, in addition to the saturation value detecting device of the above-mentioned aspect, an offset value is added to the output signal value of the current clock cycle which is compared with the output signal value of the previous clock cycle by the comparator. An offset value addition circuit is added.

Since the offset value is added to the output signal value of the present clock cycle in the saturation value detecting device having the above-described configuration, the offset value is set to a value larger than the noise level, which causes noise. do it,
The output signal value of the previous clock cycle becomes larger than the output signal value of the current clock cycle, and the output signal value of the current clock cycle is prevented from being mistakenly recognized as the saturation value.

In addition to the above-mentioned saturation value detecting device, another invention further comprises a frequency divider for frequency-dividing the clock signal applied to the comparator, and a gain adjusting circuit for dividing the frequency of the frequency divider. Frequency division ratio program control means for reducing the value in accordance with an increase in the value of the control signal applied to the.

In the saturation value detecting device configured as described above, coarse intervals are used when the signal level of the measurement signal input to the measurement target is small, and fine intervals are used when the signal level of the measurement signal input to the measurement target is increased. Since the current value and the previous value of the output signal are compared with each other, the saturation value can be detected with high accuracy in a short time.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a saturation value detection device according to an embodiment. The measurement signal a output from the measurement signal generator 11 is input to the gain adjustment circuit 12. The gain adjustment circuit 12 controls the signal level of the measurement signal a input from the measurement signal generator 11 according to the signal value of the analog control signal g applied to the control terminal G, and a new signal level I Is applied to the measurement target 13 as a measurement signal a ₁ having

As the object 13 to be measured, an element constituted by a semiconductor such as an amplifier or an analog switch so as to exhibit a unique function is mentioned.

The output signal b output from the measuring object 13 is input to the measuring device 14. The analog signal level P of the output signal b input into the measuring device 14 is detected by the level detector 15. The signal level P of the output signal b detected by the level detector 15 is displayed on the display unit 17 after being subjected to predetermined data processing by the data processing unit 16.

The analog signal level P of the output signal b detected by the level detector 15 of the measuring device 14 is input to the A / D converter 18. The A / D converter 18 synchronizes with the clock of the clock signal c having the constant cycle (clock cycle) T shown in FIG. Is A / D converted and applied to one end of the adder circuit 19 and the latch circuit 21 as a digital output value PD.

The clock generation circuit 29 is startup-controlled by the control unit 28 including, for example, a personal computer (PC). Further, the clock signal c having the constant period T output from the clock generation circuit 29 is applied to the clock terminal CP of the count-up circuit 25 and the control unit 28.

Further, the clock signal c having a constant cycle T output from the clock generation circuit 29 is divided by the frequency divider 26.
The clock frequency is divided into 1 / N, that is, the clock cycle is expanded N times, and a new clock cycle TN is generated.
As a clock signal c ₁ having
3, applied to the comparator 24. The frequency division ratio 1 / N of the frequency divider 26 is set by the control unit 28.

A digital offset value OF is constantly applied from the offset memory 20 to the other end of the adder circuit 19. The offset value OF is set to a value slightly higher than the signal level of the noise component included in the output signal b output from the measurement target 13. The adder circuit 19 adds the offset value OF to the output value PD applied in synchronization with the clock of the divided clock signal c ₁ to obtain a new output value PDA (PDA = PD + OF), which is the present value buffer 22. Write to.

The latch circuit 21 synchronizes with the clock of the divided clock signal c ₁ and outputs the applied output value P.
D is fetched and the fetched output value PD is written to the next previous value buffer 23 in synchronization with the clock of the next clock signal c ₁ . That is, the output value PD stored in the previous value buffer 23 is the output value PD stored in the current value buffer 22.
The output value is delayed from A by one clock cycle TN.

The comparator 24 outputs the divided clock signal c
_In synchronization with the clock of ₁ , the output value PDA output from the current value buffer 22 is compared with the output value PD stored in the previous value buffer 23, and the output value PD stored in the previous value buffer 23 is determined to be the current value. When the output value PDA output from the value buffer 22 is equal to or larger than the output value PDA, the count-up stop signal d is sent to the count-up circuit 25 and the control unit 28.

In the count-up circuit 25, an initial value CN ₀ corresponding to the initial value I ₀ of the signal level I of the measurement signal a ₁ applied to the measurement object 13 is supplied from the control unit 28 to the count value CN before the measurement is started. Is set to. Then, as shown in FIG. 3, the count-up circuit 25 counts up the count value CN in synchronization with the clock of the clock signal c output from the clock generation circuit 29. When the count-up stop signal d is input from the comparator 24, the count-up operation of the count value CN is stopped.

The count value CN output from the count-up circuit 25 is converted into an analog control signal g by the next D / A converter 27, and then applied to the control terminal G of the gain adjusting circuit 12. As a result, the gain adjustment circuit 1
The signal level I of the measurement signal a ₁ applied from 2 to the measurement target 13 changes corresponding to the count value CN of the count-up circuit 25.

In the control unit 28 composed of a computer,
A clock counter 30 and a frequency division ratio table 31 are provided. The clock counter 30 counts the number of clocks CK of the clock signal c output from the clock generation circuit 29 after being activated.

As shown in FIG. 3, the frequency division ratio table 31 stores the frequency division ratio N which is gradually reduced in accordance with the increase in the number of clocks CK counted by the clock counter 30. There is. That is, at the measurement start time t ₀ , the frequency division ratio N is large, the frequency division ratio decreases as time t passes, and the frequency division ratio N becomes 1 shortly before the count-up stop signal d is output. . Note that, of the functions described above, the components other than the data processing unit 16 and the control unit 28 may be configured by hardware.

Then, the control unit 28 executes the processing for measuring the saturation value of the measuring object 13 according to the flow chart shown in FIG. When the measurement of the saturation value for the measurement object 13 is started, the initial value CN ₀ of the count value CN is written in the count-up circuit 25 (Q1). Furthermore, the clock counter 3
Reset the clock number CK of 0 (CK = 0) (Q
2). Next, the clock generation circuit 29 is activated (Q
3). As a result, the count value CN of the count-up circuit 25 starts increasing, and the signal level I of the measurement signal a ₁ applied to the measurement target 13 starts increasing.

Cycle T from the clock generation circuit 29 before frequency division
When one clock of the clock signal c of
4) The clock number CK of the clock counter 30 is updated (CK = CK + 1) (Q5). The frequency division ratio N corresponding to the corresponding clock number CK is read from the frequency division ratio table 31 (Q
6) The read frequency division ratio N is set in the frequency divider 26 (Q7). When the count-up stop signal d is not output from the comparator 24 (Q8), the signal level P of the output signal b of the measurement target 13 has not yet reached the saturation value P _S , so the process returns to Q4 and the clock signal c Wait for the next clock of input.

When the count-up stop signal d is output from the comparator 24 in Q8, the output value PD stored in the previous value buffer 23 becomes equal to or larger than the output value PDA output from the current value buffer 22. , It is determined that the signal level P of the output signal b of the measurement target 13 has reached the saturation value P _S.
Then, at this time point, the digital output value PD output from the A / D converter 18 is read as the saturation value P _S of the output signal b (Q9). The read saturation value P _S is displayed and output (Q10).

Also, the count-up times at this point
Read the count value CN output from path 25,
Measured from the gain adjustment circuit 12 based on the count value CN of
Measurement signal a applied to the target 13₁Signal level I_STo
Saturation value P obtained previously _SAnd display output.

FIG. 3 shows a time chart showing the operation of detecting the saturation value P _S of the output signal b of the measuring object 13 in the saturation value detecting apparatus of the embodiment.

When the measurement operation is started at time t ₀ , the count value CN output from the count-up circuit 25 increases in synchronization with the clock of the cycle T of the clock signal c, and the measurement value applied to the measurement object 13 is measured. The signal level I of the signal a ₁ also increases.

On the other hand, in synchronization with the clock of the clock signal c ₁ having the period TN divided by the frequency divider 26 to 1 / N, the comparator 24 synchronizes with the current output value PDA and the previous output value P.
D is compared. The interval of the comparison operation becomes narrower with the passage of time.

Then, at time t ₁ , the current output value PD
When A becomes equal to or less than the previous output value PD, the count-up stop signal d is output from the comparator 24 and the saturation value P _S is read.

[0047] In such configured saturation value detecting device, in the period from time t ₀ of the measurement start to time t ₁ of the measurement end, the output value P of the present output value PDA and the previous
Since the comparison with D is automatically performed by hardware in synchronization with the clock of the clock signal c ₁ , the saturation value is higher than that of the conventional apparatus which the measurement control device 5 shown in FIG. The measurement processing efficiency of P _S can be significantly improved.

Further, the offset value OF is added to the current output value PDA to make a new current output value PDA, and this current output value PDA is compared with the previous output value PD. This offset value OF is set to be larger than the noise level. Therefore, due to noise, the current output value P
Accidental recognition of DA as the saturation value P _S is prevented.
Therefore, the measurement accuracy of the saturation value P _S is improved.

Further, since the frequency division ratio N of the frequency divider 26 is lowered with the lapse of time, when the signal level I of the measurement signal a ₁ input to the measuring object 13 is small, it is set at coarse intervals.
When the signal level I of the measurement signal a ₁ increases, the comparator 24 compares the output value PDA of this time with the output value PD of the previous time at a fine interval, so that the saturation value P _S can be obtained in a short time and with high accuracy. Can be detected.

The present invention is not limited to the apparatus of the above embodiment. ALC in the gain adjustment circuit 12
By incorporating the (automatic level control) circuit and setting the clock period T of the clock signal c to a time slightly longer than the response time of the output signal level control in the ALC (automatic level control) circuit, the saturation value P _S and It can improve the measurement accuracy of the measuring signal a ₁ signal level I _S in the saturation value P _S.

[0051]

As described above, in the saturation value detecting device of the present invention, the comparator for comparing the previous value and the present value in synchronization with the clock and the count-up for increasing the signal level of the measurement signal. A circuit is provided, and the output value at the time when the previous value exceeds the current value is set as the saturation value.

Therefore, since the increase of the signal level of the measurement signal and the comparison between the previous value and the current value can be performed by hardware, the measurement processing time of the saturation value for the measurement object can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a saturation value detection device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a saturation value detection processing operation of a control unit incorporated in the saturation value detection device of the embodiment.

FIG. 3 is a time chart showing a saturation value detection operation in the saturation value detection device of the embodiment.

FIG. 4 is a block diagram showing a schematic configuration of a conventional saturation value detection device.

FIG. 5 is a diagram showing a method of detecting a saturation value in the conventional saturation value detection device.

FIG. 6 is a flowchart showing a saturation value detection processing operation in a measurement control device incorporated in the conventional saturation value detection device.

[Explanation of symbols]

11 ... Measurement signal generator 12 ... Gain adjustment circuit 13 ... Measurement target 14 ... Measuring instrument 15 ... Level detector 18 ... A / D converter 19 ... Adder circuit 20 ... Offset memory 21 ... Latch circuit 22 ... Current value buffer 23 ... Previous value buffer 24 ... Comparator 25 ... Count-up circuit 26 ... Divider 28 ... Control unit 29 ... Clock generation circuit 31 ... Dividing ratio table

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-73646 (JP, A) JP-A-60-102573 (JP, A) JP-A-55-51366 (JP, A) JP-A-11- 298274 (JP, A) JP-A-3-77077 (JP, A) JP-A-59-80114 (JP, A) Actually open flat 7-18280 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/00 G01R 31/26 G01R 31/316

Claims (3)

(57) [Claims] 1. A measurement signal generator (11) that outputs a measurement signal to be applied to a measurement target (13), and controls the level of the measurement signal according to the value of a control signal externally applied. A gain adjusting circuit (12) applied to the measurement target; a level detector (15) for detecting the level of the output signal of the measurement target; a clock generation circuit (29) for outputting a clock signal of a constant cycle; A for A / D converting the level detected by the level detector into a digital output signal value in synchronization with the clock signal
An A / D converter (18) and an A / D converter for synchronizing with the clock signal.
The / D converted output signal value of this clock cycle is compared with the output signal value of the previous clock cycle, and a count-up stop signal is output when the previous output signal value exceeds this output signal value. And a control signal having a value corresponding to a count value that counts up and increases in response to the clock signal when receiving the clock signal, and applies a count-up stop signal from the comparator. A count-up circuit (25) for stopping the increase of the count value when input, and an A / D converted output from the A / D converter immediately after the count-up stop signal is output from the comparator A saturation value detecting device, wherein a signal value is extracted as a saturation output value of the measurement target. 2. An offset value adding circuit for adding an offset value to an output signal value of a current clock cycle which is compared with an output signal value of a previous clock cycle by the comparator (19,
20. The saturation value detecting device according to claim 1, comprising 20). 3. A frequency divider (26) for frequency-dividing a clock signal applied to the comparator, and a frequency division ratio of the frequency divider according to an increase in the value of a control signal applied to the gain adjusting circuit. The saturation value detecting device according to claim 1 or 2, further comprising a frequency division ratio program control means (28) for decreasing the frequency.