JP3468119B2 - Constant voltage power supply circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-voltage output type constant voltage power supply circuit capable of individually supplying a constant voltage to a plurality of loads.

[0002]

2. Description of the Related Art Conventionally, as a constant voltage power supply circuit for supplying a constant voltage to an external load, for example, as shown in FIG. 9, on a power supply path for supplying power from an unillustrated DC power supply (power supply voltage VDD) to an external load. In addition, a PNP transistor (so-called power transistor) T capable of controlling an output voltage to an external load
An output circuit DRV provided with R is provided, and this output circuit DRV
The output voltage VO from is divided by resistors R1 and R2,
The PNP transistor T in the output circuit DRV is provided by the output from the operational amplifier 1 which compares the divided voltage with the reference voltage Vref so that the divided voltage becomes a predetermined reference voltage Vref.
It is known that R is controlled.

That is, in this circuit, the resistors R1 and R2 are
When the divided voltage divided by is lower than the reference voltage Vref, the output voltage from the operational amplifier 1 decreases and the base current of the PNP transistor TR increases, and conversely, the divided voltage becomes equal to or higher than the reference voltage Vref. Then, the output voltage from the operational amplifier 1 increases and the base current of the PNP transistor TR decreases. As a result, the output voltage VO from the output circuit DRV to the external load is controlled to a constant voltage determined by the reference voltage Vref and the voltage division ratio of the resistors R1 and R2.
Can supply constant voltage to external load. In FIG. 9, V
SS is a ground line (GN) with the same potential as the negative side of the DC power supply.
Represents D).

Conventionally, for example, when it is necessary to individually supply a constant voltage to two or more loads, the constant voltage power supply circuit shown in FIG. 9 is constructed for each load.
A constant voltage is individually supplied to the corresponding load from each constant voltage power supply circuit.

[0005]

When a constant voltage power supply circuit of this kind is incorporated in a semiconductor integrated circuit (IC) alone or together with other functional circuits to reduce the size,
Since the load current IO flows through the output circuit DRV and its power consumption increases, the output circuit DRV cannot be incorporated in the IC.

That is, the power consumption WO of the output circuit DRV
Is the load current IO and the potential difference (V
DD-VO), the following equation (1) is obtained.
WO = IO * (VDD-VO) (1) Output circuit DRV
However, it was difficult to incorporate this into the IC.

Therefore, conventionally, the constant voltage power supply circuit is
When incorporated in C, the output circuit DRV is configured separately from the IC, and only the operational amplifier 1 serving as the control circuit of the output circuit DRV and the resistors R1 and R2 for voltage division are incorporated in the IC. . Therefore, as described above, when a constant voltage power supply circuit is configured for each load in order to individually supply a constant voltage to a plurality of loads, these circuits are integrated into an IC.
Even if you try to reduce the size of the power supply circuit by incorporating it inside,
The output circuit DRV must be separately configured for each load, and there is a limit to downsizing the entire power supply circuit.

The present invention has been made in view of these problems, and in a multi-voltage output type constant voltage power supply circuit that outputs two or more constant voltages, the power consumption in the output circuit for constant voltage output is reduced. Then, it is an object of the present invention to enable the output circuit to be incorporated in the semiconductor integrated circuit together with the voltage control circuit.

[0009]

In a constant voltage power supply circuit according to claim 1, which has been made to achieve the above object, a first voltage is provided on a first path for supplying power from a DC power supply to a first load. There is provided first output means having a first voltage control element capable of controlling the output voltage to the load. Then, the first control means detects the output voltage from the first output means to the first load, and controls the first voltage control element so that the detected output voltage becomes the first constant voltage.

Further, a second path for supplying power to the second load is connected to the first path from the first output means to the first load, and an output to the second load is provided on the second path. Second output means having a second voltage control element capable of controlling the voltage is provided. Then, the second control means detects the output voltage from the second output means to the second load, and controls the second voltage control element so that the detected output voltage becomes the second constant voltage.

Therefore, according to the constant voltage power supply circuit of the present invention, the first constant voltage can be supplied to the first load and the second constant voltage can be supplied to the second load. Then, since power is supplied to the second path for supplying power to the second load via the first output means on the first path, the power consumed by the second output means is the second path. It is less than that when is connected directly to the DC power supply.

That is, the first output means transfers the first load to the first load.
When the constant voltage is supplied and the second constant voltage is supplied from the second output means to the second load, a dedicated path from the DC power source to each load is formed as in the conventional case, and each path is individually provided. When the output means is provided, the potential difference (and hence the power consumption) generated in each output means increases, but in the present invention, the power is supplied to the second output means via the first output means. , The potential difference generated in the second output means can be reduced, and the power consumption thereof can be reduced.

Therefore, when the constant voltage power supply circuit of the present invention is incorporated in a semiconductor integrated circuit, not only the first and second control means but also the second output means can be incorporated in the semiconductor integrated circuit. Therefore, the entire power supply circuit can be downsized as compared with the conventional circuit. When three or more types of constant voltage are required as the output voltage to the external load, a plurality of power supply circuits each including the second path, the second output means, and the second control means may be provided. Also in this case, since the second output means forming each of these power supply circuits can be incorporated in the semiconductor integrated circuit, the power supply circuit as a whole can be configured by the semiconductor integrated circuit and the first output means, and the power supply circuit The overall size can be reduced.

By the way, when the second path is directly connected to the first path from the first output means to the first load, the same voltage as or the same as the output voltage from the second output means to the first load is used. The above voltage cannot be output. This is because the voltage supplied to the second output means is the output voltage to the first load, and the second voltage control element is controlled so that the output voltage from the second output means to the first load becomes maximum. Even so, the output voltage from the second output means becomes lower than the output voltage to the first load due to the voltage drop caused by the load current to the second load flowing through the second voltage control element. is there.

Therefore, in the present invention, in order to make the output voltage from the second output means to the second load equal to or higher than the output voltage to the first load ,
On the first path from the first output means to the first load, the second control means makes the second voltage so as to maximize the output voltage to the second load.
There is provided a potential difference generating means for generating a potential difference which is equal to or more than a potential difference (that is, a voltage drop) generated in the second output means when the voltage control element is controlled, and the second path is provided with the potential difference generating means
The first control means is connected to the first path to the output means, and the first control means is configured to detect the output voltage from the potential difference generation means to the first load . Therefore, according to the present invention, the voltage supplied from the first output means to the second output means through the second path is the voltage obtained by adding the potential difference generated by the potential difference generation means to the output voltage to the first load. Therefore, the voltage output from the second output means to the second load can be the output voltage to the first load or higher.

As the second voltage control element constituting the second output means, a bipolar type transistor or a field effect transistor (FET) can be used. Especially, as described above. When the output voltage to the second load is controlled to be equal to or higher than the output voltage to the first load, a MOS type FET with small loss is used as the second voltage control element, and the potential difference is large. It is desirable to minimize the potential difference generated by the generating means so that the voltage drop generated in the second output means is as small as possible.

Then, for example, when the output voltage to the second load is controlled to the same voltage as the output voltage to the first load by the second control means, the second voltage is set as described in claim 2. The control element is constituted by a MOS type FET, and the potential difference generating means is constituted by a diode which generates a potential difference by a forward voltage at the time of energization, or, as in claim 4 , the second voltage control element is constituted. It may be constituted by a MOS type FET, and the potential difference generating means may be constituted by a MOS type FET provided on the first path and a first drive circuit for controlling the MOS type FET to be in an ON state.

That is, when the potential difference generating means is constituted by a diode as described in claim 2 , the diode forward voltage VF (about) is provided on the first path from the first output means to the first load. 0.7V) potential difference can be generated without using a special drive circuit, and the potential difference is the minimum required to supply the same output voltage as the first load to the second load. Since it is larger than the voltage drop of the second output means, the desired voltage can be stably supplied from the second output means to the second load.

However, in this case, since the potential difference generated by the potential difference generating means is larger than the minimum voltage drop of the second output means necessary for supplying power from the second output means to the second load, When the output voltage from the power supply (power supply voltage) is reduced, the voltage output from the first output means to the first load via the potential difference generation means is the second output means from the second output means.
It may be lower than the voltage output to the load.

Therefore, as described in claim 2 , the second
When the second voltage control element of the output means is composed of a MOS type FET and the potential difference generation means is composed of a diode, the output voltage to the first load is the second load as described in claim 3. Voltage determining means for determining whether the output voltage to the first load is lower than the output voltage to the second load, and the voltage determining means determines that the output voltage to the first load is lower than the output voltage to the second load.
Potential difference reducing means for controlling the MOS FET provided in parallel with the potential difference generating means to reduce the potential difference so that the output voltage to the first load matches the output voltage to the second load. Is desirable.

That is, when the output voltage to the first load becomes lower than the output voltage to the second load due to the decrease in the power supply voltage, the MOS-type FET provided in parallel with the potential difference generating means.
Is controlled to reduce the potential difference generated by the forward voltage of the diode to the potential difference generated by the second output means, thereby increasing the output voltage to the first load and outputting to the first load and the second load. Match the voltage.

On the other hand, as described in claim 4 , a potential difference generating means is provided on the first path and a MOS type FET and this M type FET are provided.
When the OS type FET is constituted by the first drive circuit for controlling the ON state, the second minimum necessary for supplying the electric potential difference generated by the electric potential difference generating means to the second load from the second output means. Since the voltage drop of the output means can be made to substantially match, a first drive circuit for controlling the MOS FET to be always on is required, but the output to the first load is reduced as the power supply voltage decreases. The voltage never becomes lower than the output voltage to the second load, and each output voltage can always be the same voltage. Further, in this case, the minimum voltage required to supply power to the second load is supplied from the first output means to the second output means, and the potential difference generated in the second output means becomes the smallest, so the potential difference generation means. As compared with the case where the diode is used for the above, the power consumption in the second output means can be further reduced.

Next, the second voltage control element is a MOS type FET.
In the case where the second voltage control element is an n-channel MOS type FET, the n-channel type or the p-channel type can be used as the MOS type FET. , as described in claim 5, a boosting circuit for boosting the supplied power supply voltage to the second control unit, the high voltage boosted by the booster circuit, corresponding to the output from the first control means voltage And a second drive circuit for controlling the n-channel MOS type FET with this voltage.

That is, when an n-channel MOS type FET is used as the second voltage control element, its drain is the first
The source is connected to the output means side, and the source is connected to the second load side. In order to control the second voltage control element, the gate voltage needs to be higher than the source voltage (that is, the output voltage to the second load). Therefore, there is no problem as long as the second control means can output the voltage required to control the second voltage control element. However, for example, the power supply voltage supplied to the second control means is the second load due to the difference in the power supply system or the like. If it is lower than the output voltage to the second voltage control element, the second control means cannot control the second voltage control element. Therefore, in the constant voltage power supply circuit according to claim 5 , when the n-channel MOS type FET is used as the second voltage control element, the power supply voltage supplied to the second control means is boosted by the booster circuit. The second drive circuit generates a voltage corresponding to the output from the first control means by the boosted high voltage and controls the n-channel MOS type FET by using this voltage. Therefore, according to the constant voltage power supply circuit of the fifth aspect , even when the power supply voltage supplied to the second control means is low, the second voltage control element composed of the n-channel MOS type FET is controlled, The second constant voltage can be supplied to the second load.

Next, in any of the constant voltage power supply circuits according to claims 1 to 5 , the power consumption in the second output means is reduced as compared with the case where the conventional constant voltage power supply circuit is used as it is. Because it is possible, when actually making it, request
As described in Item 6 , it is desirable to form all the constituent means except the first output means in the same chip that constitutes the semiconductor integrated circuit.

That is, in this way, a multi-voltage output type constant voltage power supply circuit and an IC incorporating the above-mentioned means are provided.
The circuit can be configured with two circuit components including the circuit element that constitutes the first output means, and the size of the power supply circuit can be reduced. Further, in this case, if all the constituent means except the first output means are incorporated in the semiconductor integrated circuit together with other functional circuits such as a signal processing circuit and a control circuit, an electronic device having a desired function can be obtained. , It becomes possible to make it smaller.

Next, the present invention (claims 1 to 6 )
Then, in the first path between the first output means and the first load, the second path is provided.
The output voltage to the second load is controlled by connecting the path and controlling the second output means provided on the second path. In this case, for example, the second load itself or the second load is controlled. When an abnormality such as a short circuit occurs in the power supply path from the second output means to the second load for some reason, the output voltage from the second output means to the second load decreases, so the second control means outputs the second output. The second output means is controlled so as to increase the current flowing from the means to the second load. Then, in this case, an overcurrent larger than usual flows from the second output means to the second load side, and the current to be supplied to the first load cannot be secured on the first output means side. Therefore, when an abnormality such as a short circuit occurs on the second load side, it becomes impossible to supply a normal voltage to the first load as well as the abnormal second load.

[0028] In order to solve such a problem, as described in claim 7, said claims 1 to 6
In any one of the constant voltage power supply circuits, the voltage drop detecting means for detecting a voltage drop on the second path due to the increase of the output current from the second output means to the second load, and the voltage drop detecting means. It is desirable to provide current limiting means for limiting the output current from the second output means to the second load when the detected voltage drop exceeds a predetermined amount.

That is, in the constant voltage power supply circuit according to the seventh aspect , an abnormality such as a short circuit occurs on the second load side, and the second control means increases the output current from the second output means to the second load. Then, since the voltage drop on the second path becomes large, this voltage drop is detected by the voltage drop detecting means, and when the detected voltage drop becomes a predetermined amount or more, the current limiting means makes the second The output means limits the output current flowing to the second load side.

Therefore, according to the constant voltage power supply circuit of the seventh aspect , even if an abnormality such as a short circuit occurs on the second load side,
An increase in the output current flowing from the second output means to the second load side is suppressed to prevent the abnormality of the second load from affecting the output voltage to the first load, and to operate the first load normally. It will be possible.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is an electric circuit diagram showing the basic configuration of the constant voltage power supply circuit of the embodiment. As shown in FIG. 1, the constant voltage power supply circuit according to the present embodiment individually applies a constant voltage (VO1, V0, V1) to two external loads (first load, second load) not shown.
In order to supply VO2), there are provided two constant voltage output systems, a first constant voltage output system and a second constant voltage output system.
Of these, the first constant voltage output system is configured exactly like the conventional constant voltage power supply circuit shown in FIG.

That is, the first constant voltage output system is a first output means provided on a power supply path (first path) for supplying power from a DC power supply (power supply voltage VDD) (not shown) to the first load. Output circuit DRV1 as
Voltage dividing resistors R1 and R2 for dividing the output voltage VO1 from the first load to the first load, and a divided voltage (= VO1 · R1 / (R1 + R2)) divided by the resistors R1 and R2 and a reference not shown. The operational amplifier 1 is configured to compare with the reference voltage Vref generated by the voltage generation circuit.

In the first constant voltage output system, the PNP transistor TR in the output circuit DRV1 is controlled by the output from the operational amplifier 1 so that the divided voltage becomes the reference voltage Vref.
Of the output voltage VO1 to the first load by controlling the base current of the constant voltage (= Vref. (R1 + R2) / R) determined by the reference voltage Vref and the resistance ratio of the resistors R1 and R2.
Control to 1). The resistors R1 and R2 and the operational amplifier 1 correspond to the first control means of the present invention.

On the other hand, the second constant voltage output system, like the first constant voltage output system, is an output circuit D as a second output means having a voltage control element (not shown) such as a PNP transistor.
RV2, resistors R3 and R4 that divide the output voltage VO2 to the second load, a divided voltage (= VO2 · R3 / (R3 + R4)) divided by the resistors R3 and R4, and the reference voltage Vref. In the present embodiment, one end of the power feeding path (second path) to the second load in which the output circuit DRV2 is provided has one end from the output circuit DRV1 to the first operational amplifier 2.
The output circuit DRV is connected to the first path to the load.
2 receives power from a DC power supply via the output circuit DRV1.

In the second constant voltage output system, as in the first constant voltage output system, the output circuit DRV2 is controlled by the output from the operational amplifier 2 so that the divided voltage becomes the reference voltage Vref.
By controlling the voltage control element in the output voltage Vo2 to the second load, a constant voltage (= Vref. (R3 + R4) /) determined by the reference voltage Vref and the resistance ratio of the resistors R3 and R4.
Control to R3). The resistors R3 and R4 and the operational amplifier 2 correspond to the second control means of the present invention.

In this embodiment, the output circuit DV2 is provided on the first path from the output circuit DRV1 to the first load when the output circuit DRV2 is controlled so that the output voltage becomes maximum.
A potential difference greater than the potential difference generated at both ends of RV2 is generated,
A potential difference generating circuit 10 as a potential difference generating means is provided. The second path for supplying power to the second load is provided with the potential difference generating circuit 10 and the output circuit DRV1.
And one end (one end of R2) of the voltage dividing resistors R1 and R2 for detecting the output voltage VO1 to the first load is connected to the first load from the potential difference generation circuit 10 to the first load. It is connected to the.

In the constant voltage power supply circuit of the present embodiment having such a configuration, the output voltage VO1 supplied from the DC power supply to the first load via the output circuit DRV1 and the potential difference generation circuit 10 is the operation of the operational amplifier 1. Output voltage VO2 controlled by the DC power supply to the second load via the output circuit DRV1 and the output circuit DRV2.
However, since it is controlled to a predetermined constant voltage by the operation of the operational amplifier 2, a desired constant voltage can be individually supplied to the external loads (first load and second load) of the two systems.

In this embodiment, the power supply path (second path) to the second load in which the output circuit DRV2 is provided is formed from the output side of the output circuit DRV1. Therefore, the conventional circuit shown in FIG. 9 is used. Compared with the case where two constant voltage output systems are configured to be used as they are, the power consumed by the output circuit DRV2 can be significantly reduced.

That is, in the conventional circuit shown in FIG. 9, the power consumption W0 in the output circuit DRV is as shown in the above equation (1). When the output system is configured, the power consumption of the output circuit DRV of each system is "IO x (VDD-VO
) ”

On the other hand, in the constant voltage power supply circuit of this embodiment, the load currents flowing through the first load and the second load are respectively changed.
Let IO1 and IO2 be the potential difference generated by the potential difference generating circuit 10, and let V10 be the potential difference generated by the potential difference generating circuit 10. The power consumption W1 and W2 in the output circuits DRV1 and DRV2 are supplied from the DC power source and the load currents IO1 and IO2 and the potential difference V10. According to the power supply voltage VDD and the output voltage VO1 and VO2 to each load,
It can be expressed as (2) and (3).

W1 = (IO1 + IO2) × (VDD−VO1−V10) (2) W2 = IO2 × (VO1 + V10−VO2) (3) Therefore, in the constant voltage power supply circuit of this embodiment, the load currents IO1 and IO2 And the output voltages VO1 and VO2 are the same as the load current IO and the output voltage VO in the conventional device shown in FIG. 9, respectively, the power consumptions W1 and W2 are, respectively,
The following equations (4) and (5) are obtained, and W1 = 2 × IO × (VDD−VO−V10) (4) W2 = IO × V10 (5) From this equation, the conventional circuit is used as it is. It can be seen that the power consumption W2 in the output circuit DRV2 can be significantly reduced as compared with the case where two voltage output systems are configured.

Therefore, according to this embodiment, the output circuit DR
V2 can be incorporated in the IC chip, and a multi-voltage output type constant voltage power supply circuit can be realized at a lower cost than conventional circuits .

Since the output circuit DRV2 is for controlling the output voltage VO2 to the second load, a voltage control element composed of a PNP transistor or the like is provided like the output circuit DRV1. The voltage control element may be a bipolar transistor such as a PNP transistor, or an FET. Also,
Each of the output circuits DRV1 and DRV2 may be provided with a smoothing circuit including a capacitor or the like in order to stabilize the output voltage.

Furthermore, the constant voltage power supply circuit shown in FIG.
The constant voltage can be supplied individually to the external load of the system, but if more constant voltage outputs are required, the second constant voltage output system can be increased according to the number of voltage outputs. Good. Even if the second constant voltage output system is increased in this way, the power consumption of the output circuit in each increased constant voltage output system is the same as that of the output circuit DRV2 described above.
Since it can be sufficiently suppressed as compared with the conventional circuit, all but the output circuit DRV1 forming the first constant voltage output system can be incorporated in the IC chip, and the power supply circuit can be downsized.

The basic configuration of the constant voltage power supply circuit of the embodiment has been described above. Next, a specific circuit configuration for actually manufacturing the constant voltage power supply circuit shown in FIG. 1 will be described. It should be noted that each constant voltage power supply circuit described below receives power supply (for example, power supply voltage VDD = 12V) from an on-vehicle battery in an automobile, for example, to a load of two systems such as a control device and a signal processing device. Then, the output voltages VO1 and VO2 of the same voltage (for example, 5 V) are supplied.

First, FIG. 2 shows the constant voltage power supply circuit of the first embodiment in which the output circuit DRV2 is constructed by connecting the PNP transistor T1 and the NPN transistor T2 in Darlington connection in the constant voltage power supply circuit shown in FIG. Represents As shown in FIG. 2, in the constant voltage power supply circuit of the first embodiment, the PNP transistor T is provided in the output circuit DRV2.
The emitter of 1 and the collector of the NPN transistor T2 are connected to the output circuit DRV1 side, and the emitter of the NPN transistor T2 is connected to the second load side. Then, the collector of the PNP transistor T1 is connected to the base of the NPN transistor T2, and the base of the PNP transistor T1 is connected to the output of the operational amplifier 2.

Therefore, when the divided voltage obtained by dividing the output voltage VO2 by the resistors R3 and R4 is equal to or higher than the reference voltage Vref and the output voltage of the operational amplifier 2 becomes high, the transistor T1,
The base current of T2 decreases and the output voltage V
When O2 decreases and conversely the divided voltage is lower than the reference voltage Vref and the output voltage of the operational amplifier 2 decreases, the base currents of the transistors T1 and T2 increase and the output voltage VO2 to the second load increases. To do. As a result, the output voltage V02 to the second load is controlled to a desired constant voltage (for example, 5V).

Further, since this constant voltage power supply circuit controls the output voltage VO1 to the first load and the output voltage VO2 to the second load to the same voltage (for example, 5V), the potential difference generating circuit 10 The potential difference generated as a result must be equal to or larger than the potential difference generated at both ends of the output circuit DRV2. Therefore, in the present embodiment, the potential difference generating circuit 10 is composed of two diodes D1 and D2 connected in the forward direction on the power feeding path (first path) to the first load.

As a result, the potential difference (2 × VF: about 1.4V) generated in the potential difference generating circuit 10 is the output circuit DRV2.
Is greater than the potential difference (base-emitter voltage VBE of T2 + emitter-collector voltage VCE of T1) generated when the output voltage is controlled to be maximum, and the output voltages VO1 and VO2 can be controlled to the same voltage. As described above, the constant voltage power supply circuit according to the first embodiment has the output circuit DRV2.
Is composed of two transistors T1 and T2, the potential difference generation circuit 10 is composed of diodes D1 and D2, and as described above, the power consumption in the output circuit DRV2 can be sufficiently suppressed. Therefore, the output circuit DRV1 is excluded. All circuits can be built into the IC chip.

Next, FIG. 3 shows an output circuit DRV2 of the constant voltage power supply circuit shown in FIG.
2 shows a constant voltage power supply circuit of a second embodiment constituted by a type FET (Q1). As shown in FIG. 3, in the constant voltage power supply circuit of the second embodiment, the MOS type FE is provided in the output circuit DRV2.
The drain of T (Q1) is connected to the output circuit DRV1 side, the source is connected to the second load side, and the gate is connected to the output of the operational amplifier 2. Then, in order to increase the output voltage from the output circuit DRV2, the MOS type FET (Q
In order to increase the gate voltage of 1) and decrease the output voltage on the contrary, it is necessary to decrease the gate voltage. Therefore, the operational amplifier 2 which controls this has an output voltage VO2 by resistors R3 and R4.
The input terminals of the divided voltage and the reference voltage Vref are shown in FIG. 2 so that the output voltage decreases as the divided voltage divided by increases and the output voltage increases as the divided voltage decreases. The operational amplifier 2 is set in the opposite manner.

Further, the output circuit DRV2 is
In the case of S-type FET (Q1), the output circuit D
Since the voltage drop (potential difference) generated in RV2 can be made sufficiently smaller than the forward voltage of the diode,
The potential difference generation circuit 10 is configured by one diode D1 connected in the forward direction on the power feeding path (first path) to the first load.

As a result, according to the constant voltage power supply circuit of the second embodiment shown in FIG. 3, not only the output voltages VO1 and VO2 to each load can be controlled to the same voltage, but also the first embodiment shown in FIG. Compared with the constant voltage power supply circuit of the example, the configurations of the output circuit DRV2 and the potential difference generation circuit 10 can be simplified, and the potential difference generated in the output circuit DRV2 can be reduced to reduce the output circuit DRV2.
Since the power consumption at V2 can be further reduced, all the circuits except the output circuit DRV1 can be easily incorporated in the IC chip.

In the constant voltage power supply circuit of the second embodiment, the MOS type FET that constitutes the output circuit DRV2 is
It is also possible to use the p-channel one. Then, in this way, the output circuit DRV2 is connected to the p-channel MOS type FE.
When T is used, the source is on the output circuit DRV1 side,
The drain is connected to the second load side, and the input terminal of the divided voltage and the reference voltage Vref in the operational amplifier 2 is made the same as the operational amplifier 2 shown in FIG. Output voltage (in other words, FET
The gate voltage) may be reduced.

Next, FIG. 4 shows a constant voltage power supply circuit of the third embodiment. This constant voltage power supply circuit is different from the constant voltage power supply circuit of the second embodiment in that it determines whether or not the output voltage VO1 is lower than the output voltage VO2, and a voltage judgment circuit 20 as a voltage judgment means and an output. When the voltage VO1 is lower than the output voltage VO2, the n-channel MOS type FET 34 provided in parallel with the potential difference generation circuit 10 is controlled to output the output voltage VO1.
And a potential difference reducing circuit 30 as potential difference reducing means for matching the output voltage VO2 with the output voltage VO2.

The potential difference reducing circuit 30 includes an n-channel MOS type FET 34 having a drain connected to the output circuit DRV1 side and a source connected to the first load side, the output voltage VO1 to the first load, and the voltage determination circuit 20. When the output from the voltage determination circuit 20 is larger than the output voltage VO1, the voltage signal corresponding to the potential difference is output to the gate of the MOS type FET 34 to energize the MOS type FET 34. The voltage determination circuit 20 is composed of an operational amplifier 32. The voltage determination circuit 20 switches between outputting the output voltage VO2 to the potential difference reduction circuit 30 and grounding its output line via a load such as a resistor, and the output voltage VO1. The output voltage VO2 is compared, and when the output voltage VO1 is lower than the output voltage VO2, the switch 24 is switched to the second load side, and the potential difference reducing circuit 30. And a comparator 22 for outputting the output voltage VO2.

The comparator 22 uses a Schmitt trigger circuit provided with hysteresis in the judgment operation so that the judgment result does not hunt due to the fluctuations of the output voltages VO1 and VO2. According to the constant voltage power supply circuit of the third embodiment configured as described above, when the power supply voltage VDD supplied from the vehicle battery decreases, the output voltage VO1 to the first load is the output voltage to the second load. It can be prevented from falling below VO2.

That is, as in the constant voltage power supply circuit of the second embodiment, the output circuit DRV2 is an n-channel MOS type FET.
When the potential difference generation circuit 10 is configured by (Q1) and the diode D1 is configured, the potential difference generated by the potential difference generation circuit 10 is greater than the potential difference generated when the output circuit DRV2 is controlled to maximize the output voltage. Is also large,
When the power supply voltage VDD drops near the output voltages VO1 and VO2, the output voltage VO1 may become lower than the output voltage VO2 due to the potential difference generated by the potential difference generation circuit 10.

Therefore, in the constant voltage power supply circuit of the third embodiment, when the output voltage VO1 becomes lower than the output voltage VO2, the voltage determination circuit 20 outputs the output voltage VO2 to the potential difference reduction circuit 30 to generate the potential difference. On the reducing circuit 30 side, the potential difference generating circuit 1 is adjusted so that the output voltage VO1 matches the output voltage VO2.
The MOS type FET 34 connected in parallel to 0 is controlled. As a result, according to the present embodiment, even if the power supply voltage VDD drops, the output voltage VO1 and the output voltage VO2 can be controlled to the same voltage.

Next, FIG. 5 shows a constant voltage power supply circuit according to the fourth embodiment. In this constant voltage power supply circuit, the potential difference generating circuit 10 in the constant voltage power supply circuit of the second embodiment is replaced with the diode D1, the drain is connected to the output circuit DRV1 side, and the source is connected to the first load side. MO of channel
It is composed of an S-type FET 14 and a charge pump 12 as a first drive circuit that constantly applies a high voltage to the gate of the MOS-type FET 14 to keep the MOS-type FET 14 in an ON state.

According to this constant voltage power supply circuit, the potential difference generated by the potential difference generation circuit 10 is output by the output circuit DRV.
2 becomes the same as the potential difference generated when the output voltage is controlled to be the maximum, and the output voltages VO1 and VO2 can be always matched, and the output circuit DRV2 is different from the constant voltage power supply circuit of the second embodiment. It is possible to further reduce power consumption.

The charge pump 12 boosts the power supply voltage Vcc in the IC chip which is received together with other circuit elements such as the operational amplifiers 1 and 2 when the constant voltage power supply circuit is incorporated in the IC chip. MOS type FET14
For generating the drive voltage of

That is, in order to turn on the MOS type FET 14, at least the MOS type FE is higher than the output voltage VO1.
Since it is necessary to apply a drive voltage higher than the threshold voltage of T14, in this embodiment, the drive voltage obtained by boosting the power supply voltage Vcc using the charge pump 12 is a MOS type FE.
By applying to the gate of T14, when the power supply voltage VCC in the IC chip is equal to or lower than the output voltage VO1 or when the power supply voltage VDD supplied from the battery decreases, the power supply voltage VCC in the IC chip decreases. Even in such a case, the MOS type FET 14 can be surely turned on.

The charge pump 12 may be constructed, for example, as shown in FIG. That is, a series circuit composed of the analog switch S1, the capacitor C1, and the analog switch S3 is connected between the power supply line (voltage VCC) and the ground line (GND) in the IC chip in which the charge pump 12 is incorporated, and the MOS is connected. Type FE
A capacitor C2 is connected between the output line that outputs the driving voltage Vout to T14 and the power supply line in the IC chip,
Further, a capacitor C3 is connected between the output line and the ground line in the IC chip. Also, the capacitor C1
And the connection point between the power line analog switch S1 and
The other end of the analog switch S2 whose one end is connected to the output line is connected, and the other end of the analog switch S4 whose one end is connected to the power supply line is connected to the connection point between the capacitor C1 and the ground line side analog switch S3. To do. Then, the analog switches S1 and S3 are connected to the oscillator 12a.
Is repeatedly turned on and off by a pulse signal repeatedly output at a predetermined cycle, and the analog switches S2 and S4 are turned on and off by a pulse signal obtained by inverting the pulse signal from the oscillator 12a by the inverter 12b.

As a result, in the charge pump 12, the analog switches S1 and S3 and the analog switch S2 are
And S4 are alternately turned on / off. By this on / off operation, first, the capacitor C1 is charged by the power supply voltage Vcc, and then the charge accumulated in the capacitor C1 is transferred to the capacitor C2. Next, capacitor C
The electric charge accumulated in 2 is transferred to the capacitor C3, and the electric charge is repeatedly charged in the capacitor C3. Therefore, the voltage across the capacitor C3 (that is, the drive voltage Vout) becomes higher than the power supply voltage Vcc, and a high voltage (drive voltage Vout) obtained by boosting the power supply voltage Vcc is applied to the gate of the MOS type FET 14 to apply the MOS type FET 14 to the gate. Can be reliably turned on.

Next, FIG. 7 shows a constant voltage power supply circuit of the fifth embodiment. This constant voltage power supply circuit is different from the constant voltage power supply circuit of the fourth embodiment in that it receives the output signal from the operational amplifier 2 and controls the MOS type FET (Q1) in the output circuit DRV2 as a second drive circuit. Charge pump circuit 40
Is provided.

This charge pump circuit 40 has a MOS type FET (Q1) in the output circuit DRV2 when the constant voltage power supply circuit is incorporated in the IC chip due to a decrease in the power supply voltage in the IC chip received by the operational amplifier 2. ), And a charge pump 42 as a booster circuit configured similarly to the charge pump 12 in the potential difference generation circuit 10,
Constant current circuit 44, NPN transistor 46 and PNP
And a transistor 48.

Then, each of these transistors 46, 48
Is the MOS type FET in the output circuit DRV2
It is connected to the gate of (Q1), the collector of the NPN transistor 46 is connected to the output terminal of the charge pump 42, and the collector of the PNP transistor 48 is grounded. The constant current circuit 44 is connected to the output of the charge pump 42, and supplies a constant current from the charge pump 42 side to the bases of the transistors 46 and 48 and the output side of the operational amplifier 2.

In the charge pump circuit 40 thus constructed, when the output voltage VO2 to the second load is high and the output voltage from the operational amplifier 2 is low, most of the output current from the constant current circuit 44 is on the operational amplifier 2 side. And the base current of each of the transistors 46 and 48 decreases, the output voltage from the charge pump circuit 40 to the output circuit DRV2 (gate voltage of the MOS type FET (Q1)) decreases,
Conversely, when the output voltage VO2 to the second load is low, the operational amplifier 2
When the output voltage from the charge pump circuit 40 increases, the current flowing from the constant current circuit 44 to the operational amplifier 2 decreases, and the base current of each of the transistors 46 and 48 increases. Therefore, the output voltage from the charge pump circuit 40 to the output circuit DRV2 ( The gate voltage of the MOS type FET (Q1) rises.
Then, from the charge pump circuit 40 to the output circuit DRV2
Since the voltage output to the output circuit DRV2 is generated by the high voltage from the charge pump 42,
The type FET (Q1) can be controlled by its output voltage.

Therefore, according to the constant voltage power supply circuit of the fifth embodiment, the MOS type FET (Q1) in the output circuit DRV2 is used.
Can be surely controlled according to the output of the operational amplifier 2 without being affected by the output voltage from the operational amplifier 2. When these circuits are incorporated in the IC chip, the power source of the IC chip can be controlled. Even when the voltage is low, it is possible to reliably control the output circuit DRV2.

Next, FIGS. 8A and 8B are electric circuit diagrams showing the configuration (partially omitted) of the constant voltage power supply circuit of the sixth embodiment to which the invention of claim 7 is applied. This constant voltage power supply circuit is designed not only for the second load but also for the first load when an abnormality such as a short circuit occurs in the second load which receives power supply (output voltage VO2) from the output circuit DRV2 as the second output means. It is designed to solve the problem that power cannot be supplied to the device.

That is, in the constant voltage power supply circuit shown in FIG. 1, when an abnormality such as a short circuit occurs in the second load to which the output voltage VO2 is supplied, the resistance value of the second load as seen from the power supply circuit side becomes
Since the resistance value is zero or extremely low, the output end of the output voltage VO2 is grounded to the ground line (VSS) directly or via a resistor having an extremely low resistance value. Then, in this state, the output voltage VO2 becomes zero or an extremely low voltage value, so the operational amplifier 2 controls the output circuit DRV2 to maximize the load current IO2 supplied from the output circuit DRV2 to the second load. Increase. As a result, the output voltage VO1 to the first load also approaches the ground level, and power cannot be supplied to the first load.

Therefore, in the constant voltage power supply circuit shown in FIGS. 8A and 8B, in addition to the constant voltage power supply circuit shown in FIG.
An abnormal voltage drop on the power feeding path (second path) to the second load caused by the increase of the output current IO2 to the second load is detected, and the load current IO2 flowing from the output circuit DRV2 to the second load is detected. The current limiting circuits 50 and 60 for limiting are provided so that even when an abnormality such as a short circuit occurs in the second load, the operation of the current limiting circuits 50 and 60 enables the power supply to the first load to be normally performed. There is.

The constant voltage power supply circuits shown in FIGS. 8A and 8B will be described below. First, FIG.
The output circuit DRV2 in the constant voltage power supply circuit shown in
When an NPN transistor (or n-channel MOS type FET) T3 is provided as a voltage control element, an example of a current limiting circuit 50 suitable for being provided in this constant voltage power supply circuit is shown.

As shown in FIG. 8A, the output circuit DRV
2, the collector of the NPN transistor T3 is connected to the power feeding path (first path) from the output circuit DRV1 to the first load, and the emitter is connected to the power feeding path (second path) to the second load, and the base. Is connected to the output terminal of the operational amplifier 2.

The current limiting circuit 50 has the NP
A resistor RS1 as a voltage drop detecting means provided on a power supply path (second path) from the emitter of the N-transistor T3 to the second load, and an NPN transistor TS1 having a function as a current limiting means are provided. There is.

The base of the NPN transistor TS1 has a resistor RS1 and an output circuit DRV2 (in other words, NPN).
To the second path between the resistor RS1 and the second load.
The collector is connected to the path, and the collector is connected to the path for the control signal from the operational amplifier 2 to the output circuit DRV1 (in other words, the base of the NPN transistor T3).

FIG. 8 equipped with such a current limiting circuit 50.
In the constant voltage power supply circuit shown in (a), the output voltage VO2
If an abnormality such as a short circuit occurs on the side of the second load that receives the supply of the power, the potential of the second path (output voltage VO2) from the output circuit DRV2 to the second load decreases, so the operational amplifier 2
Attempts to increase the load current IO2 by controlling the NPN transistor T3 in the output circuit DRV2 to the full ON state in order to raise this potential. On the other hand, in the current limiting circuit 50, when the load current IO2 increases, the voltage drop across the resistor RS1 increases, and when this voltage drop exceeds the base-emitter threshold voltage Vf of the NPN transistor TS1. , The NPN transistor TS1 operates, and the operational amplifier 2 outputs the NPN transistor T in the output circuit DRV2.
The current supplied to the base of 3 is forcibly drawn out and NP
The N-transistor T3 is turned off.

As a result, even if an abnormality such as a short circuit occurs on the second load side and the potential of the second path (output voltage VO2) from the output circuit DRV2 to the second load becomes the ground level (VSS), the output NPN transistor T in circuit DRV2
Since 3 is off, the voltage drop on the second path side is the first
The output voltage VO1 to the load is not affected, and the desired constant voltage can be supplied to the first load to operate the first load normally.

Next, FIG. 8B shows that the output circuit DRV2 in the constant voltage power supply circuit shown in FIG. 1 uses a PNP transistor (or p-channel MOS type F) as a voltage control element.
An example of the current limiting circuit 60 suitable for being provided in this constant voltage power supply circuit when it is provided with ET) T4 is shown.

As shown in FIG. 8B, the output circuit DRV
In 2, the emitter of the PNP transistor T4 is connected to the power feeding path (first path) from the output circuit DRV1 to the first load, and the collector is connected to the power feeding path (second path) to the second load, Is connected to the output terminal of the operational amplifier 2.

The current limiting circuit 60 is connected to the output circuit DRV2 from the first path in which the output circuit DRV1 is provided.
Resistor RS2 as a voltage drop detecting means provided on the second path to (emitter of PNP transistor T4)
, PNP transistor TS2, resistors RS3 and RS4,
An NPN transistor TS3 is provided.

Here, the emitter of the PNP transistor TS2 is connected to the first path (output circuit DRV1) side of the resistor RS2, the base is connected to the output circuit DRV2 side of the resistor RS2, and the collector is the resistor body. It is grounded to the ground line VS in the power supply circuit via RS3 and RS4.

The base of the NPN transistor TS3 is connected to the connection point between the resistor RS3 and the resistor RS4, and the collector and emitter are connected to the base and emitter of the output transistor (NPN transistor) TO in the operational amplifier 2. It is connected. That is, the operational amplifier 2 compares the voltage at the connection point between the resistors R3 and R4 with the reference voltage Vref by the differential pair 2a, and outputs the output transistor TO.
Is to control. Then, when the reference voltage Vref is higher than the connection point voltage and the differential pair 2a outputs a high level signal, a constant current circuit which receives a power supply from the operational amplifier power supply VOP and supplies a constant current IOP to the output transistor TO. A base current is supplied via 2b to turn on the output transistor To, which turns on the PNP transistor T4 in the output circuit DRV2.

Therefore, on the side of the current limiting circuit 60, it is possible to forcibly prevent the output transistor To of the output transistor To in the operational amplifier 2 from turning on and the PNP transistor T4 in the output circuit DRV2 from turning on. In order to set the output transistor T in the operational amplifier 2
By connecting the output terminal (that is, the collector and the emitter) of the NPN transistor TS3 between the base and the emitter of O and turning on the NPN transistor TS3, the output transistor TO in the operational amplifier 2 (and thus the output circuit D
The PNP transistor T4) on the RV2 side is forcibly turned off.

FIG. 8 equipped with such a current limiting circuit 60.
In the constant voltage power supply circuit shown in (b), the output voltage VO2
If an abnormality such as a short circuit occurs on the side of the second load that receives the supply of the power, the potential of the second path (output voltage VO2) from the output circuit DRV2 to the second load decreases, so the operational amplifier 2
Controls the output transistor TO to be in a full-on state, so that the PNP transistor T in the output circuit DRV2 is
4 is fully turned on to increase the load current I02. On the other hand, in the current limiting circuit 60, when the load current IO2 increases, the voltage drop across the resistor RS2 increases, and when this voltage drop exceeds the base-emitter threshold voltage Vf of the PNP transistor TS2. , PNP transistor TS2 operates to supply current to resistors RS3 and RS4 provided between the collector and ground line (VS) of the PNP transistor TS2. And this current causes resistor RS4
When the voltage drop occurring at the voltage exceeds the threshold voltage Vf between the base and the emitter of the NPN transistor TS3, the transistor TS3 is turned on, the current supplied to the output transistor T0 in the operational amplifier 2 is extracted, and the output transistor T0
Forces O to turn off. As a result, the output circuit DRV2
The PNP transistor T4 inside is also turned off.

Therefore, the current limiting circuit 6 shown in FIG.
Even if 0, when an abnormality such as a short circuit occurs on the second load side, the voltage drop on the second path side causes the output voltage V to the first load.
It is possible to prevent the influence on O1 and supply a desired constant voltage to the first load to operate the first load normally.

In the current limiting circuit 60 shown in FIG. 8B, the PNP transistor TS2, the resistors RS3 and RS4,
The NPN transistor TS3 functions as the current limiting means according to claim 7 . When the constant voltage power supply circuit is integrated as one IC chip, all the constituent elements other than the resistors RS1 and RS2 as the voltage drop detecting means in the current limiting circuits 50 and 60 are the IC chip. It should be built in.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a basic configuration of a constant voltage power supply circuit according to an embodiment.

FIG. 2 is an electric circuit diagram showing a configuration of a constant voltage power supply circuit of a first embodiment in which the constant voltage power supply circuit of FIG. 1 is embodied.

FIG. 3 is an electric circuit diagram showing the configuration of the constant voltage power supply circuit of the second embodiment as well.

FIG. 4 is an electric circuit diagram showing a configuration of a constant voltage power supply circuit of a third embodiment as well.

FIG. 5 is an electric circuit diagram showing the configuration of the constant voltage power supply circuit of the fourth embodiment.

FIG. 6 is an electric circuit diagram showing a configuration of a charge pump.

7 is an electric circuit diagram showing a configuration of a constant voltage power supply circuit of a fifth embodiment in which the constant voltage power supply circuit of FIG. 1 is embodied.

FIG. 8 is an electric circuit diagram illustrating a configuration of a constant voltage power supply circuit according to a sixth embodiment including a current limiting circuit.

FIG. 9 is an electric circuit diagram showing a configuration of a conventional constant voltage power supply circuit.

[Explanation of symbols]

DRV1, DRV2 ... Output circuit, TR, T1, T4, T
S2 ... PNP transistor, T2, T3, TS1, TS3 ... N
PN transistor, 1, 2 ... Operational amplifier, R1 to R4
RS1, RS2 ... Resistor, 10 ... Potential difference generating circuit, D1, D
2 ... Diode, Q1 ... MOS type FET, 20 ... Voltage judging circuit, 30 ... Potential difference reducing circuit, 12, 42 ... Charge pump, 40 ... Charge pump circuit, 50, 60 ... Current limiting circuit.

Continuation of the front page (56) Reference JP-A-8-272463 (JP, A) JP-A-7-141065 (JP, A) JP-A-5-326832 (JP, A) Actual development Sho-62-37321 (JP , U) JP-B-41-2496 (JP, B1) (58) Fields investigated (Int.Cl. ⁷ , DB name) G05F 1 / 445,1 / 56 G05F 1 / 613,1 / 618

Claims (7)

(57) [Claims] 1. A first output means provided on a first path for supplying power from a DC power supply to a first load, the first output means having a first voltage control element capable of controlling an output voltage to the first load, A constant voltage detecting means for detecting an output voltage from the first output means to the first load, and controlling the first voltage control element so that the output voltage becomes a first constant voltage. In the power supply circuit, a second path that is connected to the first path from the first output means to the first load and that supplies power to the second load from the connection point is formed, and on the second path, A second output means including a second voltage control element capable of controlling the output voltage to the second load is provided, and further, the output voltage from the second output means to the second load is detected, and the output voltage is detected. Control means for controlling the second voltage control element so that the voltage becomes a second constant voltage. Provided, moreover, the leading to the first load from the first output means 1
On the path, the second control means outputs to the second load.
The second voltage control element is controlled so that the voltage becomes maximum.
Potential difference that is greater than or equal to the potential difference generated by the second output means
And a potential difference generating means for generating
A first path between the potential difference generating means and the first output means
And the first control means is connected to the potential difference generating means.
Is configured to detect the output voltage to the first load.
Constant voltage power supply circuit according to claim Rukoto. 2. The second voltage control element is a MOS type FE
T, the potential difference generating means is a diode that generates a potential difference by a forward voltage during energization, and the second control means controls the output voltage to the second load by the first control means. Is configured to be controlled to the same voltage as the output voltage to the first load controlled by
The constant voltage power supply circuit according to claim 1 . 3. A voltage determining means for determining whether an output voltage to the first load is lower than an output voltage to the second load, and an output voltage to the first load by the voltage determining means. Is determined to be lower than the output voltage to the second load,
Potential difference reducing means for controlling a MOS FET provided in parallel with the potential difference generating means to reduce the potential difference so that the output voltage to the first load matches the output voltage to the second load. The constant voltage power supply circuit according to claim 2 , wherein Wherein the second voltage control element, MOS type FE
T, the potential difference generating means is composed of a MOS type FET provided on the first path and a first drive circuit for controlling the MOS type FET to be in an ON state, and the second control means is 2. The constant voltage power supply according to claim 1 , wherein the output voltage to the second load is configured to be controlled to the same voltage as the output voltage to the first load controlled by the first control means. circuit. Wherein the second voltage control element n-channel MO
An output from the first control means is formed by an S-type FET, and a booster circuit for boosting the power supply voltage supplied to the second control means and a high voltage boosted by the booster circuit. Generated voltage, and at the voltage, the n-channel M
The 2nd drive circuit which controls OS type FET was provided, The constant voltage power supply circuit in any one of the Claims 1-4 characterized by the above-mentioned. 6. The constant voltage power supply circuit according to claim 1 , wherein all the constituent means except the first output means are formed in the same chip that constitutes a semiconductor integrated circuit. Characteristic constant voltage power supply circuit. 7. The constant voltage power supply circuit according to any one of claims 1 to 6, accompanied by the second output means to increase the output current to the second load, the voltage drop on the second path A voltage drop detecting means for detecting the voltage drop, and a current limiting means for limiting an output current from the second output means to the second load when the voltage drop detected by the voltage drop detecting means becomes a predetermined amount or more, A constant voltage power supply circuit characterized by being provided.