JP6444213B2 - Constant voltage generation circuit, semiconductor device, electronic device, and vehicle - Google Patents

Description

  The present invention relates to a constant voltage generation circuit, a semiconductor device, an electronic device, and a vehicle.

  In recent years, there has been a demand for lower current consumption of semiconductor devices (for example, the current consumption of the entire semiconductor device is 10 μA or less). In order to meet such a demand, it is desirable to keep the current consumption of the constant voltage generation circuit used as the internal power supply of the semiconductor device as small as possible.

  FIG. 7 is a circuit diagram showing a conventional example of a constant voltage generation circuit. In the constant voltage generating circuit 200 of the conventional example, in order to reduce the current consumption, the resistance value of the resistor 208 is set large, and the current Ia (collector current of the transistor 201) flowing to the input side of the current mirror is reduced. There is a need. Further, in order to reduce the current Ib flowing through the input terminal of the chip enable signal EN, it is necessary to set the resistance values of the resistors 209 and 210 large.

JP 2012-226422 A

  However, as the resistance values of the resistors 208 to 210 are set larger in order to reduce the current consumption of the constant voltage generation circuit 200, each element size becomes larger. Therefore, in the constant voltage generation circuit 200 of this conventional example, an increase in the resistance values of the resistors 208 to 210 directly leads to an increase in the chip area.

For example, when the power supply voltage VCC is 16V and the forward saturation voltage Vf of the transistors 201 to 203 is 0.65V, in order to reduce the current Ia to 1 μA, the resistance value of the resistor 208 is 15.35 MΩ (= (16V −0.65 V) / (1 × 10 ⁻⁶ A)), which is a factor that hinders downsizing of the constant voltage generation circuit 200.

For example, when the chip enable signal EN is 5 V, the combined resistance value of the resistors 209 and 210 must be 5 MΩ (= 5 V / 1 × 10 ⁻⁶ A) in order to reduce the current Ib to 1 μA. Also, downsizing of the constant voltage generation circuit 200 has been hindered.

  Further, in the constant voltage generation circuit 200 of the conventional example, the currents Ia and Ib increase as the power supply voltage VCC or the chip enable signal EN increases. Therefore, in order to suppress the current consumption of the constant voltage generation circuit 200 while supporting a high voltage input, the resistance values of the resistors 208 to 210 must be set larger, resulting in a further increase in chip area. It is burned.

  In Patent Document 1 by the present applicant, a reference current generation circuit having a reference voltage generation unit that generates a reference voltage using a depletion type transistor and a voltage / current conversion unit that generates a reference current from the reference voltage. Has been proposed. With such a reference current generation circuit, it is possible to eliminate the trade-off between circuit scale reduction and low current consumption.

  However, Patent Document 1 does not disclose or suggest the chip enable function, and there is room for further study on the circuit scale reduction and low current consumption of the functional unit.

  In view of the above-described problems found by the inventors of the present application, the invention disclosed in the present specification eliminates the trade-off between circuit scale reduction and low current consumption while maintaining the current consumption constant. An object of the present invention is to provide a constant voltage generation circuit with a chip enable function, a semiconductor device, an electronic device, and a vehicle.

  A constant voltage generation circuit disclosed in the present specification is integrated in a semiconductor device, and a constant voltage generation unit that generates a predetermined constant voltage from a power supply voltage using an ED type reference voltage source; A cutoff control unit that receives an input of a chip enable signal, wherein the cutoff control unit has a drain connected to an input end of the chip enable signal and a gate connected to an output end of the ED type reference voltage source. An enhancement type first NMOSFET [N-channel type metal oxide semiconductor field effect transistor] and a depletion type second NMOSFET in which a drain is connected to a source of the first NMOSFET and a gate and a source are both connected to a ground terminal. The constant voltage generator using a node voltage that appears at a connection node between the first NMOSFET and the second NMOSFET. And a configuration (first configuration) for controlling the operation of each part of the semiconductor device.

  In the constant voltage generation circuit having the first configuration, the cutoff controller further includes a gate connected to the node voltage application terminal, a drain connected to the cutoff signal output terminal, and a source connected to the ground terminal. It is preferable to adopt a configuration (second configuration) including an enhancement type third NMOSFET connected to the first and second NMOSFETs.

  Further, in the constant voltage generation circuit having the second configuration, the cutoff control unit further includes a depletion in which a gate and a source are connected to each other between an input end of the power supply voltage and an output end of the cutoff signal. A configuration including at least one type of fourth NMOSFET (third configuration) is preferable.

  In the constant voltage generation circuit having any one of the first to third configurations, the ED type reference voltage source includes a depletion type fifth NMOSFET in which a gate and a source are both connected to an output terminal of the reference voltage, A configuration (fourth configuration) including an enhancement-type sixth NMOSFET in which the gate and the drain are both connected to the output terminal of the reference voltage is preferable.

  In the constant voltage generation circuit having the fourth configuration, the constant voltage generation unit includes a depletion type in which a gate and a source are connected to each other between an input terminal of the power supply voltage and the ED type reference voltage source. The seventh NMOSFET may be configured to include at least one of the seventh NMOSFETs (fifth configuration).

  In the constant voltage generation circuit having any one of the first to fifth configurations, the constant voltage generation unit includes an enhancement type eighth NMOSFET having a gate connected to an output terminal of the ED type reference voltage source, A resistor having one end connected to the source of the eighth NMOSFET, a current mirror connected to the drain of the eighth NMOSFET, a cathode connected to the output end of the current mirror, and an anode connected to the ground end A Zener diode having a drain connected to the input terminal of the power supply voltage, a gate connected to the cathode of the Zener diode, and a source connected to the output terminal of the constant voltage. (Sixth configuration) is preferable.

  In the constant voltage generation circuit having the sixth configuration, the constant voltage generation unit further includes an enhancement type 10th NMOSFET in which a gate and a drain are connected to each other between the ED type reference voltage source and a ground terminal. (7th configuration).

  In the constant voltage generation circuit having the sixth or seventh configuration, the constant voltage generation unit further includes an npn in which a base and a collector are connected between the ED type reference voltage source and a ground terminal. A configuration including an bipolar transistor (eighth configuration) is preferable.

  In the constant voltage generation circuit having any one of the sixth to eighth configurations, the constant voltage generation unit further includes a gate having a drain connected to the second end of the resistor and a source connected to a ground end. Is configured to include an enhancement type eleventh NMOSFET connected to the node voltage application end (the ninth configuration).

  In addition, the semiconductor device disclosed in this specification generates a predetermined constant voltage from an internal circuit and a power supply voltage, supplies the constant voltage to the internal circuit, and controls whether the internal circuit operates according to a chip enable signal. The constant voltage generation circuit having any one of the first to ninth configurations is integrated (tenth configuration).

  In the semiconductor device having the tenth configuration, the internal circuit includes a reference voltage generation circuit that generates a predetermined reference voltage upon receiving the supply of the constant voltage, an output voltage or a feedback voltage corresponding thereto, and the A power supply circuit that generates the output voltage from the power supply voltage so as to match a reference voltage may be used (an eleventh structure).

  Further, the electronic device disclosed in the present specification has a configuration (a twelfth configuration) including the semiconductor device having the eleventh configuration as power supply means to each part of the device.

  Further, the vehicle disclosed in the present specification has a configuration (a thirteenth configuration) including a battery and the electronic apparatus having the twelfth configuration that operates by receiving supply of a power supply voltage from the battery. ing.

  According to the invention disclosed in this specification, a constant voltage generation circuit with a chip enable function and a semiconductor capable of eliminating the trade-off between circuit scale reduction and low current consumption while maintaining current consumption constant An apparatus, an electronic device, and a vehicle can be provided.

The figure which shows one structural example of a power supply device Circuit diagram showing a first embodiment of a constant voltage generation circuit The figure which shows the relationship between the power supply voltage VCC, the electric current I1, and the voltage V1. Circuit diagram showing a second embodiment of the constant voltage generation circuit Circuit diagram showing a third embodiment of the constant voltage generation circuit External view showing a configuration example of the vehicle X Circuit diagram showing a conventional example of a constant voltage generation circuit

<Power supply unit>
FIG. 1 is a block diagram illustrating a configuration example of a power supply device. The power supply device 1 of this configuration example is a step-down regulator that generates a desired output voltage Vout by stepping down the power supply voltage VCC supplied from the DC voltage source (battery) E1 (in this configuration example, an LDO [low drop out] regulator) The semiconductor device 100 and various discrete components (capacitors C1 and C2, a power Zener diode (or Schottky diode) D1, a diode D2, and a load Z1) attached to the semiconductor device 100.

  The semiconductor device 100 includes a silicon monolithic integrated circuit (a so-called LDO regulator) in which a constant voltage generation circuit 110, a reference voltage generation circuit 120, an error amplifier 130, a driver 140, an output transistor 150, and resistors 160 to 180 are integrated. IC). In addition to the above components, the semiconductor device 100 may appropriately include various protection circuits and protection elements (such as a temperature protection circuit, an overcurrent protection circuit, or an electrostatic breakdown protection element).

  Further, the semiconductor device 100 has eight external terminals as means for establishing electrical connection with the outside. Pin 1 (VOUT) is a voltage output terminal. Pins 2 to 4 (NC) are unconnected terminals. Pin 5 (EN) is a chip enable signal input terminal. Pin 6 (GND) is a ground terminal. Pin 7 (NC) is an unconnected terminal. Pin 8 (VCC) is a power supply voltage input terminal. Of course, the number of pins can be designed arbitrarily. For example, the four-terminal IC may be configured by removing the unconnected terminals (2 to 4 pins, 5 pins, and 7 pins).

  The constant voltage generation circuit (preregulator circuit) 110 generates a predetermined constant voltage Vreg from the power supply voltage VCC and supplies it to each unit (the reference voltage generation circuit 120, the error amplifier 130, etc.) of the semiconductor device 100. The constant voltage generation circuit 110 also has a chip enable function that generates a cutoff signal S1 according to the chip enable signal EN and outputs it to each unit (the reference voltage generation circuit 120, the error amplifier 130, the driver 140, etc.) of the semiconductor device 100. I have.

  The reference voltage generation circuit 120 receives the supply of the constant voltage Vreg and generates a predetermined reference voltage Vref.

  The error amplifier 130 operates by receiving supply of the power supply voltage VCC and the constant voltage Vreg, the feedback voltage Vfb (= the divided voltage of the output voltage Vout) input to the non-inverting input terminal (+), and the inverting input terminal ( An error voltage Verr corresponding to a difference from the reference voltage Vref input to −) is generated. The error voltage Verr increases when the feedback voltage Vfb is higher than the reference voltage Vref, and decreases when the feedback voltage Vfb is lower than the reference voltage Vref.

  The driver 140 operates in response to the supply of the power supply voltage VCC, and generates the gate signal G1 of the output transistor 150 according to the error voltage Verr. The gate signal G1 increases as the error voltage Verr increases, and decreases as the error voltage Verr decreases.

  The output transistor 150 is a power transistor connected between the input terminal of the power supply voltage VCC and the output terminal of the output voltage Vout. When it is necessary to receive an input of a high power supply voltage VCC, it is desirable to use a PDMOSFET (P-channel type Double-diffused MOSFET)) having a high breakdown voltage (for example, a 60V breakdown voltage) as the output transistor 150. The source of the output transistor 150 is connected to the input terminal of the power supply voltage VCC. The drain of the output transistor 150 is connected to the output terminal of the output voltage Vout. The gate of the output transistor 150 is connected to the output terminal of the driver 140 (the output terminal of the gate signal G1). The conductivity of the output transistor 150 is controlled according to the voltage value of the gate signal G1. More specifically, the higher the gate signal G1, the smaller the conductivity of the output transistor 150, and the lower the gate signal G1, the greater the conductivity of the output transistor 150.

  The resistors 160 and 170 are connected in series between the application terminal of the output voltage Vout and the ground terminal, and the connection node between them is the non-inverting input terminal (+) of the error amplifier 130 as the output terminal of the feedback voltage Vfb. It is connected. That is, the resistors 160 and 170 function as a voltage dividing circuit that divides the output voltage Vout to generate the feedback voltage Vfb. When the output voltage Vout is within the input dynamic range of the error amplifier 130, the resistors 160 and 170 can be omitted and the output voltage Vout can be directly input to the non-inverting input terminal (+) of the error amplifier 130. It is.

  The resistor 180 is connected between the application terminal of the power supply voltage VCC and the gate of the output transistor 150. The resistor 180 functions as a pull-up resistor for turning off the output transistor 150 by raising the gate signal G1 to a high level (power supply voltage VCC) when the driver 140 is in an inoperative state. Note that an active element (transistor) may be used instead of the resistor 180. The resistor 180 can also be built in the driver 140.

  The error amplifier 130, the driver 140, the output transistor 150, and the resistors 160 to 180 described above perform drive control of the output transistor 150 so that the feedback voltage Vfb (or the output voltage Vout) matches the reference voltage Vref. This corresponds to a power supply circuit that generates a desired output voltage Vout from the power supply voltage VCC.

  When a surge exceeding 50 V is applied to the 8th pin (VCC), it is desirable to insert the power Zener diode D1 between the 8th pin (VCC) and the ground terminal. When there is a possibility that the pin 8 (VCC) has a lower voltage than the ground terminal, it is desirable to insert a Schottky diode instead of the power Zener diode D1. Also, it is desirable to insert an input smoothing capacitor C1 between pin 8 (VCC) and the ground terminal.

  When load Z1 including a large inductance component is connected to pin 1 (VOUT), and back electromotive force is expected to be generated at startup and when the output is turned off, protection is provided between pin 1 (VOUT) and the ground terminal. It is desirable to insert the diode D2. Further, it is desirable to insert an output smoothing capacitor C2 between pin 1 (VOUT) and the ground terminal.

  The semiconductor device 100 having the above-described configuration is optimal for reducing current consumption (reducing dark current) of a battery direct connection system (for example, an in-vehicle power supply system that supplies power to body equipment, car stereos, car navigation, etc.). It is.

<Constant Voltage Generation Circuit (First Embodiment)>
FIG. 2 is a circuit diagram showing a first embodiment of the constant voltage generation circuit 110. The constant voltage generation circuit 110 according to the present embodiment includes a constant voltage generation unit 111 and a cutoff control unit 112.

  The constant voltage generation unit 111 is a circuit unit that generates a predetermined constant voltage Vreg from the power supply voltage VCC using the ED type reference voltage source A, and includes NMOSFETs (N1, N2, N3 (1) to (x), N4 to N6) (where x ≧ 1), PMOSFETs (P1, P2), a resistor R1, and a Zener diode ZD1. The NMOSFETs (N1, N3 (1) to (x)) are all depletion type, and the NMOSFETs (N2, N4 to N6) and the PMOSFETs (P1, P2) are all enhancement type.

  The shut-off control unit 112 is a circuit unit that receives input of the chip enable signal EN and controls whether the constant voltage generation unit 111 and each part of the semiconductor device 100 operate, and includes NMOSFETs (N7 to N9, N10 (1) to (y)). ) (Where y ≧ 1).

  A specific description will be given of the connection relationship of the above elements. The gate and source of the NMOSFET (N1) and the gate and drain of the NMOSFET (N2) are both connected to the output terminal of the reference voltage V1. The drain of the NMOSFET (N1) is connected to the input terminal of the power supply voltage VCC via the NMOSFETs (N3 (1) to (x)). The source of the NMOSFET (N2) is connected to the ground terminal. Thus, the NMOSFETs (N1, N2) connected in series between the input terminal of the power supply voltage VCC and the ground terminal function as an ED type reference voltage source A that generates a predetermined reference voltage V1.

  The drain of the NMOSFET (N3 (1)) is connected to the application terminal of the power supply voltage VCC. The gate and source of the NMOSFET (N3 (i)) (where i = 1, 2,..., X−1) are both connected to the drain of the NMOSFET (N3 (i + 1)). The gate and source of the NMOSFET (N3 (x)) are both connected to the drain of the NMOSFET (N1). As described above, the constant voltage generator 111 includes at least one depletion type NMOSFET having a gate and a source connected to each other between the input terminal of the power supply voltage VCC and the ED type reference voltage source A.

  With such a configuration, it is possible to disperse the voltages applied to the NMOSFETs (N1, N3 (1) to (x)) and increase the breakdown voltage of the entire circuit. In particular, it can be said that the above configuration is very effective when the semiconductor device 100 is used as an in-vehicle device power supply IC that requires both low dark current and high breakdown voltage.

  The gate of the NMOSFET (N4) is connected to the output terminal of the ED type reference voltage source A (= the output terminal of the reference voltage V1). The source of the NMOSFET (N4) is connected to the first end of the resistor R1. A second end of the resistor R1 is connected to the drain of the NMOSFET (N5). The source of the NMOSFET (N5) is connected to the ground terminal.

  The sources of the PMOSFETs (P1, P2) are all connected to the input terminal of the power supply voltage VCC. The gates of the PMOSFETs (P1, P2) are all connected to the drain of the PMOSFET (P1). The PMOSFETs (P1, P2) connected in this way function as a current mirror that generates a mirror current I3 (= α × I2, α is a mirror ratio) corresponding to the drain current I2 of the PMOSFET (P1). The drain of the PMOSFET (P1) corresponding to the input end of the current mirror is connected to the drain of the NMOSFET (N4).

  The drain of the PMOSFET (P2) corresponding to the output end of the current mirror is connected to the cathode of the Zener diode ZD1. The anode of the Zener diode ZD1 is connected to the ground terminal. The drain of the NMOSFET (N6) is connected to the input terminal of the power supply voltage VCC. The gate of the NMOSFET (N6) is connected to the cathode of the Zener diode ZD1. The source of the NMOSFET (N6) is connected to the output terminal of the constant voltage Vreg.

  When the power supply voltage VCC is high, a PDMOSFET or NDMOSFET having a high withstand voltage (for example, 60V withstand voltage) that can withstand the application of the power supply voltage VCC is used as the PMOSFET (P1, P2) or NMOSFET (N6). desirable.

  The drain of the NMOSFET (N7) is connected to the input terminal of the chip enable signal EN. The gate of the NMOSFET (N7) is connected to the output terminal of the ED type reference voltage source A (= the output terminal of the reference voltage V1). The source of the NMOSFET (N7) is connected to the drain of the NMOSFET (N8). The gate and source of the NMOSFET (N8) are both connected to the ground terminal.

  When a high voltage can be applied as the chip enable signal EN, it is desirable to use an NDMOSFET having a high breakdown voltage (for example, 60V breakdown voltage) that can withstand the application as the NMOSFET (N7).

  A connection node between the NMOSFET (N7) and the NMOSFET (N8) is connected to each gate of the NMOSFET (N5, N9) as an output terminal of the node voltage V4. The source of the NMOSFET (N9) is connected to the ground terminal. The drain of the NMOSFET (N9) is connected to the input terminal of the power supply voltage VCC through the NMOSFETs (N10 (1) to (y)) and is also connected to the output terminal of the cutoff signal S1.

  The drain of the NMOSFET (N10 (1)) is connected to the application terminal of the power supply voltage VCC. The gate and source of the NMOSFET (N10 (j)) (where j = 1, 2,..., Y−1) are both connected to the drain of the NMOSFET (N10 (j + 1)). The gate and source of the NMOSFET (N10 (y)) are both connected to the drain of the NMOSFET (N9). As described above, the cutoff control unit 112 includes at least one depletion type NMOSFET in which the gate and the source are connected to each other between the input terminal of the power supply voltage VCC and the output terminal of the cutoff signal S1.

  By adopting such a configuration, the voltage applied to each of the NMOSFETs (N10 (1) to (y)) is dispersed in the same manner as the previous NMOSFETs (N3 (1) to (x)), and the entire circuit is distributed. As a result, the withstand voltage can be increased.

  Next, the operation of the constant voltage generator 111 having the above configuration will be described in detail. In the ED type reference voltage source A, since the depletion type NMOSFET (N1) functions as a kind of constant current source, a constant bias current I1 is supplied to the NMOSFET (N2). As a result, a constant reference voltage V1 corresponding to the on-threshold voltage Vth (N2) of the NMOSFET (N2) appears at the output terminal of the ED type reference voltage source A.

  The bias current I1 consumed by the ED type reference voltage source A is a very small current value (independent of the power supply voltage VCC) by appropriately designing the W / L ratio of the NMOSFETs (N1, N2). (Refer to the upper part of FIG. 3). Therefore, the ED type reference voltage source A can continue to output the constant reference voltage V1 without increasing the bias current I1 even when the power supply voltage VCC increases (see the lower part of FIG. 3).

  The reference voltage V1 is applied to the gate of the NMOSFET (N4). Therefore, a constant node voltage V2 (= V1−Vth (N4)) lower than the reference voltage V1 by the on-threshold voltage Vth (N4) of the NMOSFET (N4) is applied to the first end of the resistor R1. At this time, the constant current flowing through the resistor R1 (= the drain current I2 of the transistor N4) can be expressed by V2 / R1 = {V1−Vth (N4)} / R1.

  A mirror current I3 (= α × I2) corresponding to the drain current I2 flows to the ground terminal via the Zener diode ZD1. At this time, the breakdown voltage V3 of the Zener diode ZD1 is applied to the gate of the NMOSFET (N6). Therefore, a constant voltage Vreg (= V3−Vth (N6)) that is lower than the breakdown voltage V3 by the on-threshold voltage Vth (N6) of the NMOSFET (N6) appears at the source of the NMOSFET (N6).

  In this way, unlike the conventional configuration of FIG. 7, the constant voltage generator 111 does not use a resistance element as a means for generating the bias current I1, so that the bias current I1 increases even when the power supply voltage VCC increases. In addition, the trade-off between circuit scale reduction and low current consumption can be eliminated.

  For example, when the power supply voltage VCC is 16 V and the bias current I1 is 1 μA, the circuit area can be reduced by 50% to 75% compared to the conventional configuration of FIG. Further, if the power supply voltage VCC is higher, the effect of reducing the bias current I1 becomes more remarkable.

  Next, the operation of the cutoff control unit 112 configured as described above will be described in detail. In the cutoff control unit 112, the depletion type NMOSFET (N8) functions as a kind of constant current source (or pull-down resistor), so that a constant bias current I4 is supplied to the NMOSFET (N7). A predetermined reference voltage V1 is applied from the ED type reference voltage source A to the gate of the NMOSFET (N7).

  Therefore, when the chip enable signal EN is at a high level (for example, 5 V), a constant node voltage V4 that is lower than the reference voltage V1 by the on-threshold voltage Vth (N7) of the NMOSFET (N7) at the source of the NMOSFET (N7). (= V1-Vth (N7)) appears. On the other hand, when the chip enable signal EN is at the low level (0 V), the NMOSFET (N7) does not operate, so the node voltage V4 is lowered to the ground voltage (= 0 V) via the NMOSFET (N8). That is, the node voltage V4 is at a high level (= V1-Vth (N7)) when the chip enable signal EN is at a high level, and is at a low level (= 0 V) when the chip enable signal EN is at a low level. .

  When the node voltage V4 is at a high level, the NMOSFET (N5) is turned on, so that the current path through which the drain current I2 flows is conducted. Accordingly, the constant voltage generation unit 111 is enabled (operation permitted state). On the other hand, when the node voltage V4 is at a low level, the NMOSFET (N5) is turned off, so that the current path through which the drain current I2 flows is interrupted. Accordingly, the constant voltage generator 111 is disabled (operation prohibited state). That is, the cutoff control unit 112 controls whether the constant voltage generation unit 111 can operate using the node voltage V4.

  When the node voltage V4 is at a high level, the NMOSFET (N9) is turned on, so that the cutoff signal S1 is at a low level. On the other hand, when the node voltage V4 is at the low level, the NMOSFET (N9) is turned off, so that the cutoff signal S1 is at the high level. When the cut-off signal S1 is at a low level, the internal circuit that receives the input is enabled (operation permitted). On the other hand, when the cutoff signal S1 is at a high level, the internal circuit that receives the input is disabled (operation disabled state). In other words, the cutoff control unit 112 also controls whether each part of the semiconductor device 100 operates by using the node voltage V4.

  As described above, if the chip enable function is incorporated in the constant voltage generation circuit 110, the degree of freedom in set design can be increased.

  In the cutoff control unit 112, unlike the conventional configuration of FIG. 7, no resistive element is used as a means for generating the bias current I4. Therefore, even if the chip enable signal EN rises, the bias current I4 does not increase, and the trade-off between circuit scale reduction and low current consumption can be eliminated.

  For example, when the chip enable signal EN is set to 16 V and the bias current I4 is set to 1 μA, the circuit area can be reduced by 50% to 75% as compared with the conventional configuration of FIG. Further, when the chip enable signal EN is at a higher voltage, the effect of reducing the bias current I4 becomes more prominent.

<Constant Voltage Generation Circuit (Second Embodiment)>
FIG. 4 is a circuit diagram showing a second embodiment of the constant voltage generation circuit 110. The constant voltage generation circuit 110 of the present embodiment has basically the same configuration as that of the first embodiment (FIG. 2), but is an enhancement type NMOSFET between the ED type reference voltage source A and the ground terminal. It is characterized in that (N11) is inserted. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 2, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The gate and drain of the NMOSFET (N11) are both connected to the source of the NMOSFET (N2). The source of the NMOSFET (N11) is connected to the ground terminal. With such a configuration, it is possible to obtain the reference voltage V1 (= Vth (N2) + Vth (N11)) raised by the on-threshold voltage Vth (N11) of the NMOSFET (N11).

  Here, the NMOSFET (N4) and the NMOSFET (N11) are preferably laid out so as to be paired on the semiconductor substrate. With this configuration, the on-threshold voltage Vth (N4) of the NMOSFET (N4) and the on-threshold voltage Vth (N11) of the NMOSFET (N11) can be set to the same value (or almost the same value). . Therefore, the node voltage V2 (= Vth (N2) + Vth (N11) −Vth (N4)) applied to the first end of the resistor R1 is changed to the on-threshold voltage Vth (N2) (that is, the ED type reference voltage) of the NMOSFET (N2). It is possible to match (or almost match) the voltage value set only by the source A).

  Basically, the reference voltage V1 generated by the ED type reference voltage source A has a flat temperature characteristic. Further, by ensuring the pair property of the NMOSFETs (N4, N11), the characteristic variation of the NMOSFETs (N4, N11) can be canceled relatively. Therefore, it is possible to generate a drain current I2 having a flat temperature characteristic by performing voltage / current conversion on the reference voltage V1.

<Constant Voltage Generation Circuit (Third Embodiment)>
FIG. 5 is a circuit diagram showing a third embodiment of the constant voltage generation circuit 110. The constant voltage generation circuit 110 according to the present embodiment has basically the same configuration as that of the second embodiment (FIG. 4), but further includes an npn type between the ED type reference voltage source A and the ground terminal. This is characterized in that the bipolar transistor Q1 is inserted. Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 4, and redundant descriptions are omitted. In the following, the characteristic portions of the third embodiment are mainly described.

  The base and collector of the transistor Q1 are both connected to the source of the NMOSFET (N11). The emitter of the transistor Q1 is connected to the ground terminal. With such a configuration, it is possible to obtain the reference voltage V1 (= Vth (N2) + Vth (N11) + Vf) raised by the forward saturation voltage Vf of the transistor Q1. Note that the use of a bipolar transistor is more advantageous in terms of accuracy than the use of a MOSFET.

<Application to vehicles>
FIG. 6 is an external view showing a configuration example of the vehicle X. The vehicle X of this configuration example includes a battery (not shown) and various electronic devices X11 to X18 that operate by receiving supply of the power supply voltage VCC from the battery. In addition, about the mounting position of the electronic devices X11-X18 in this figure, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is incorporated into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  In addition, the power supply device 1 demonstrated previously can be integrated in any of the electronic devices X11-X18 as a power supply means to each part of an apparatus.

<Other variations>
The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be widely used in, for example, linear regulators such as series regulators and LDO regulators, general consumer power supplies, in-vehicle power supply ICs, or high voltage ICs that require internal power supplies. In particular, the present invention can be used to increase the added value of an in-vehicle LDO regulator IC.

1 Power supply device 100 Semiconductor device (LDO regulator IC)
110 Constant Voltage Generation Circuit 111 Constant Voltage Generation Unit 112 Blocking Control Unit 120 Reference Voltage Generation Circuit 130 Error Amplifier 140 Driver 150 Output Transistor (PDMOSFET)
160 to 180 Resistance E1 DC voltage source (battery)
C1, C2 Capacitor D1 Power Zener diode (or Schottky diode)
D2 Diode Z1 Load A ED type reference voltage source N1, N3, N8, N10 Depletion type NMOSFET
N2, N4 to N7, N9, N11 Enhancement type NMOSFET
P1, P2 Enhancement type PMOSFET
Q1 npn type bipolar transistor R1 resistance ZD1 Zener diode X vehicle X11 to X18 electronic equipment

Claims (13)

A constant voltage generation circuit integrated in a semiconductor device,
A constant voltage generation unit that generates a predetermined constant voltage from a power supply voltage using an ED type reference voltage source;
A shut-off control unit for receiving an input of a chip enable signal;
Have
The cutoff controller includes an enhancement type first NMOSFET [N-channel type metal oxide semiconductor field effect transistor] having a drain connected to an input terminal of the chip enable signal and a gate connected to an output terminal of the ED type reference voltage source. And a depletion type second NMOSFET whose drain is connected to the source of the first NMOSFET and whose gate and source are both connected to the ground terminal, and which appears at the connection node between the first NMOSFET and the second NMOSFET A constant voltage generation circuit that controls whether or not the constant voltage generation unit and each part of the semiconductor device operate by using a voltage.   The cutoff control unit further includes an enhancement type third NMOSFET having a gate connected to the node voltage application terminal, a drain connected to the cutoff signal output terminal, and a source connected to the ground terminal. The constant voltage generation circuit according to claim 1.   The cutoff control unit further includes at least one depletion type fourth NMOSFET having a gate and a source connected to each other between an input end of the power supply voltage and an output end of the cutoff signal. Item 3. The constant voltage generation circuit according to Item 2. The ED type reference voltage source is:
A depletion type fifth NMOSFET in which the gate and the source are both connected to the output terminal of the reference voltage;
An enhancement type sixth NMOSFET in which a gate and a drain are both connected to an output terminal of the reference voltage;
The constant voltage generation circuit according to claim 1, wherein the constant voltage generation circuit includes:   The constant voltage generator includes at least one depletion type seventh NMOSFET having a gate and a source connected to each other between an input terminal of the power supply voltage and the ED type reference voltage source. The constant voltage generation circuit as described in any one of Claims 1-4. The constant voltage generator is
An enhancement type eighth NMOSFET having a gate connected to the output terminal of the ED type reference voltage source;
A resistor having a first end connected to a source of the eighth NMOSFET;
A current mirror having an input terminal connected to the drain of the eighth NMOSFET;
A Zener diode having a cathode connected to the output end of the current mirror and an anode connected to the ground end;
An enhancement-type ninth NMOSFET having a drain connected to the input terminal of the power supply voltage, a gate connected to the cathode of the Zener diode, and a source connected to the output terminal of the constant voltage;
The constant voltage generation circuit according to any one of claims 1 to 5, further comprising:   The constant voltage generator according to claim 6, further comprising an enhancement type 10th NMOSFET in which a gate and a drain are connected to each other between the ED type reference voltage source and a ground terminal. Voltage generation circuit.   8. The constant voltage generation unit according to claim 6, further comprising an npn bipolar transistor having a base and a collector connected to each other between the ED reference voltage source and a ground terminal. The constant voltage generation circuit described.   The constant voltage generation unit further includes an enhancement type 11th NMOSFET having a drain connected to the second end of the resistor, a source connected to the ground terminal, and a gate connected to the node voltage application terminal. The constant voltage generation circuit according to any one of claims 6 to 8, wherein the constant voltage generation circuit is characterized in that: Internal circuitry,
The constant voltage according to any one of claims 1 to 9, wherein a predetermined constant voltage is generated from a power supply voltage and supplied to the internal circuit, and the operation of the internal circuit is controlled according to a chip enable signal. A generation circuit;
An integrated semiconductor device. The internal circuit is
A reference voltage generation circuit for generating a predetermined reference voltage in response to the supply of the constant voltage;
A power supply circuit that generates the output voltage from the power supply voltage so that the output voltage or a feedback voltage corresponding thereto matches the reference voltage;
The semiconductor device according to claim 10, comprising:   An electronic apparatus comprising the semiconductor device according to claim 11 as power supply means to each part of the apparatus. Battery,
The electronic device according to claim 12, wherein the electronic device operates by receiving a power supply voltage from the battery.
The vehicle characterized by having.

Images