JP3466311B2 - Synchronous clock generation circuit and master clock output circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generating circuit and a master clock output circuit for generating a master clock synchronized with a reference clock.

[0002]

2. Description of the Related Art When constructing a high-speed system, there is a problem that a deviation (phase difference) between a system clock and a clock of each LSI has a great influence on an operation margin due to a board design.

For example, the clock of one LSI has a delay of 2 to 3 ns with respect to the system clock, and the other LSI has a delay.
If there is a delay of 3 to 6 ns with respect to the system clock, the LSI receiving the outputs of these two LSIs takes into consideration the phase difference of 1 to 3 ns between the two LSIs with respect to the system clock. It is necessary to assume a delay with a width of 2 to 6 ns, which wastes timing design. As a technique for minimizing the phase difference with respect to the system clock between LSIs, it is possible to form a delay locked loop (hereinafter referred to as DLL) inside the LSI.

FIG. 10 is a block diagram showing a basic circuit configuration of a conventional DLL circuit. As shown in FIG. 10, the basic components are a phase comparator 31, a charge pump 32,
It is composed of a loop filter 33, a voltage control delay element 34, and a clock output buffer BF4.

FIG. 11 is a circuit diagram showing an internal configuration example of the phase comparator 31. As shown in the figure, the phase comparator 31 is composed of inverters G1 to G5 and AND gates G6 to G14, and the reference clock REF. CLK and internal clock INT. CLK and the reference clock RE
F. CLK to the internal clock INT. When the phase of CLK is delayed, the inverted up signal bar UP of "L" is generated for a period corresponding to the phase difference, and the reference clock REF. C
Internal clock INT. When the phase of CLK is advanced, the down signal DOWN of "H" is output for a period corresponding to the phase difference.

FIG. 12 is a circuit diagram showing an internal configuration example of the charge pump 32 and the loop filter 33. As shown in the figure, the charge pump 32 is composed of a current source 41, a PMOS transistor 42, an NMOS transistor 43 and a current source 44 which are connected in series between a power supply and a ground level.

The charge pump 32 having such a structure is
When the inverted up signal bar UP is “L”, the PMOS transistor 41 is turned on, current is supplied from the current source 41 to the node N1 between the drain of the PMOS transistor 42 and the drain of the NMOS transistor 43, and the down signal D
When OWN is "H", the NMOS transistor 43 is turned on, current is drawn from the current source 44 from the node N1, and the voltage of the node N1 is changed.

The loop filter 33 is composed of a resistor R10 and a capacitor C10 and functions as a low pass filter.
Unnecessary high frequency component noise is removed, the voltage of the node N1 is smoothed, and the control voltage VCOIN is changed to the voltage control delay element 3
Output to 4.

FIG. 13 is a circuit diagram showing an internal configuration example of the voltage control delay element 34. As shown in the figure, the voltage control delay element 34 includes a bias setting circuit 50 and a delay circuit 60.

The bias setting circuit 50 includes PMOS transistors 51 and 52 and NMOS transistors 53 and 54.
And the bias voltage V based on the control voltage VCOIN.
P and VN change.

The delay circuit 60 comprises M stages of inverters I1 to I.
The external clock O.M. C
LK is delayed by the time it takes to propagate through the M-stage inverter, and the internal clock INT. CLK is clock output buffer BF
The output of the phase comparator 31 is output via the signal line 4. At this time, the driving capability of each inverter Ii (i = 1 to M) is equal to the bias voltage VP.
And VN, the delay time of each inverter Ii is variably controlled.

That is, the voltage control delay element 34 is
Based on the control voltage VCOIN, the external clock O.D. CLK
To the internal clock INT. C
Output LK.

The conventional DLL circuit having such a configuration has two
Reference signals REF. CLK and internal clock INT. It operates so that the phases of CLK match. Then, the reference clock REF. CLK and internal clock INT. It is said that the DLL circuit is locked when the phase with CLK matches.

Of the basic components of the DLL circuit having such a configuration, only the phase comparator is composed of a digital circuit, and the charge pump, the loop filter and the voltage control delay element are composed of analog circuits.

[0015]

A conventional synchronous clock generating circuit such as a DLL circuit is configured as described above,
There is a problem that since there is a portion configured by an analog circuit, it is easily affected by power supply noise, and since the lock operation is performed by the DLL, the lock time is slow.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a synchronous clock generation circuit which can be locked to a reference clock at a high speed without being affected by power supply noise.

[0017]

According to another aspect of the present invention, there is provided a synchronous clock generating circuit for an external circuit which receives a master clock and operates in synchronization with the internal clock delayed by the internal clock delay time. A circuit for generating the master clock, receiving a reference clock having a cycle of a predetermined time,
The delay means delays the delay time of (n> 1) and outputs the first to n-th delay signals, and each of the delay means comprises a digital circuit and has a first signal propagation delay time. An n-th partial delay means, the first to n-th partial delay means are continuously connected from the first to the n-th, and the input of the first partial delay means receives the reference clock; The outputs of the first to nth partial delay means become the first to nth delay signals, respectively, and the nth delay signal becomes a signal obtained by delaying the reference clock by the predetermined time, and the reference clock and the internal A clock-related internal clock-related signal is received, and the reference clock is changed to the first clock when a predetermined waveform change of the internal clock-related signal occurs.
˜Sampling delay means for outputting the first to nth sampling delay signals by delaying and sampling the nth sampling delay time, respectively, wherein the sampling delay means each comprises a digital circuit and a second signal A first to an nth partial sampling delay means having a propagation delay time, wherein the first to the nth partial sampling delay means are continuously connected from the first to the nth , and the first partial sampling delay receiving said reference clock input means, the output of each partial sample delay means of the first to n is the sampling delay signal of said first to n, wherein the sampling delay signal of said first to n internal Based on a timing control signal that indicates the presence or absence of the predetermined waveform change of the clock-related signal,
It further comprises a master clock output means for outputting any one of the first to nth delayed signals as the master clock to the external circuit, the master clock output means from the start of operation to the timing control signal. The internal clock-related signal defined by the timing control signal, the n-th delay signal being output as the master clock for the first period until the predetermined waveform change of the internal clock-related signal defined by Recognizing the internal clock delay time of the internal clock with respect to the reference clock based on the first to nth sampling delay signals during a second period after the predetermined waveform change of
Where TR is the predetermined time and ΔT is the internal clock delay time, the signal closest to the signal delayed in (TR-ΔT) time phase from the reference clock among the first to n-th delay signals. It is output as the master clock.

According to a second aspect of the present invention, each of the first to nth partial delay means has first and second inverters connected in series between its input and output. , The time taken for the reference clock to propagate through the first and second inverters to be the first signal propagation delay time, and the first to nth partial sampling delay means respectively include third to fifth inverters. And the third and fourth inverters are connected in series between the input and output, the fourth and fifth inverters are loop-connected, and the time for the reference clock to propagate through the third and fourth inverters is set. The master clock output means may be configured by a digital circuit with the second signal propagation delay time.

According to a third aspect of the present invention, a synchronous clock generating circuit is formed of a digital circuit, receives the reference clock, counts the number of clocks of the reference clock from the start of the operation, and the count number is predetermined. Switching means may be further provided for stopping the supply of the internal clock related signal to the sampling delay means when the number is exceeded.

According to a fourth aspect of the present invention, there is provided a first signal buffer means for receiving an external reference clock from the outside, buffering the external reference clock, and outputting the reference clock. Further comprising second signal buffer means for buffering the internal clock and outputting the internal clock related signal, even if the signal propagation delay times by the first and second signal buffer means are set to be the same. Good.

Further, as in the synchronous clock generating circuit according to the fifth aspect, the internal clock related signal may be an output internal clock for supplying to a circuit other than the external circuit.

According to a sixth aspect of the present invention, the master clock output means includes the first clock
A master clock instruction signal for instructing which signal is the master clock among the nth delay signals, the delay means further receiving the master clock instruction signal, and the master clock instruction signal. The signal is
Of the first to nth delay signals, the kth delay signal (k
= 1 to n) as the master clock, delay stop means for stopping the delay operation by the (k + 1) th to nth partial delay means may be provided.

According to a seventh aspect of the present invention, a master clock output circuit receives a first signal having a cycle of a predetermined time and delays the first signal by delay times of 1st to nth (n> 1). And delaying means for outputting the first to nth delayed signals, the delaying means having first to nth partial delaying means each having a first signal propagation delay time and each being composed of a digital circuit. , The first to n-th partial delay means are the first to n-th.
Continuously connected to the first partial delay means, receives the first signal at the input of the first partial delay means, and outputs of the first to nth partial delay means become the first to nth delayed signals, The n-th delay signal becomes a signal obtained by delaying the first signal by the predetermined time, receives the first signal and a second signal having a cycle of the predetermined time, and determines the predetermined second signal. The first signal is changed to the first to n-th
Sampling delay means for outputting the first to nth sampling delay signals by delaying and sampling each of the sampling delay times, the sampling delay means each comprising a digital circuit and a second signal propagation delay time. The first to n-th partial sampling delay means having, and the first to n-th partial sampling delay means are continuously connected from the first to the n-th ,
The first sub-sampling delay means receives the first
Signal, the outputs of the first to nth partial sampling delay means become the first to nth sampling delay signals, and the nth sampling delay signal becomes a signal delayed by the predetermined time, and One of the first to nth delay signals based on a first to nth sampling delay signal and a timing control signal that indicates the presence or absence of the predetermined waveform change of the second signal. Is further provided as the master clock to the external circuit, and the master clock output means is provided when the predetermined waveform of the second signal defined by the timing control signal changes from the start of operation. To the second delay signal defined by the timing control signal, the nth delay signal being output as the master clock during a first period up to The second of the subsequent predetermined waveform changes in No.
During the period, the signal delay time of the second signal with respect to the first signal is recognized based on the first to nth sampling delay signals, and TR ′ is the predetermined time, ΔT ′ is the signal delay time, and At this time, among the first to nth delayed signals, the signal closest to the signal delayed in (TR'-ΔT ') time phase from the first signal is output as the master clock.

According to the eighth aspect of the present invention, the synchronous clock generating circuit receives the first and second master clocks, respectively, and the first and second master clocks are the first and second master clocks, respectively.
And second internal clock delay time delayed first and second
8. The circuit for generating the first and second master clocks for the first and second external circuits, which operate in synchronization with the internal clocks of, respectively, the same as the master clock output circuit according to claim 7. 8. A first master clock output circuit, which is formed by a configuration, receives a first reference clock having a predetermined period as the first signal, and receives the first internal clock as the second signal. A second reference clock, which has the same configuration as the master clock output circuit described above and has a period of the predetermined time and a phase different from that of the first reference clock, is received as the first signal, and the second internal clock is received. And a second master clock output circuit that receives the second signal.

[0025]

In the synchronous clock generating circuit according to the first aspect of the present invention, the master clock output means has the first period from the start of operation to the predetermined waveform change of the internal clock related signal defined by the timing control signal, Nth
Of the internal clock-related signal based on the first to nth sampling delay signals for a second period after a predetermined waveform change of the internal clock-related signal defined by the timing control signal is output as the master clock. Recognizing the internal clock delay time, TR: predetermined time, Δ
T: When the internal clock delay time is set, among the first to n-th delay signals, the signal closest to the signal delayed in (TR-ΔT) time phase from the reference clock is output as the master clock, and thus the operation is started. It is possible to quickly output the master clock in which the phases of the reference clock and the internal clock match with each other as the first period elapses from the time until the predetermined waveform of the internal clock related signal changes.

Further, in the synchronous clock generating circuit according to the second aspect of the present invention, all the constituent means including the master clock output means are constituted by digital circuits, so that the synchronous clock generation circuit is resistant to power supply noise.

Further, the switching means of the synchronous clock generating circuit according to claim 3 counts the number of clocks of the reference clock from the start of input of the reference clock,
When the count number exceeds a predetermined number, the supply of the internal clock related signal to the sampling delay means is stopped.

Therefore, by setting the above-mentioned predetermined number to the minimum number of clocks that secures the period from the start of operation until the master clock is reliably locked to the reference clock, the sampling delay of the internal clock related signal is promptly performed after locking. The supply to the means can be stopped.

According to a fourth aspect of the present invention, there is provided a synchronous clock generating circuit, wherein the first signal buffer means buffers an external reference clock and outputs the reference clock, and the internal clock buffers an internal clock related signal. Further comprising second signal buffer means for
By setting the signal propagation delay times of the second signal buffer means to be the same, the master clock can be output so that the phase of the internal clock matches the phase of the external reference clock.

Further, in the synchronous clock generating circuit according to the present invention, since the internal clock related signal is the output internal clock for supplying to the circuits other than the external circuit, the phase of the output internal clock is in the reference clock. The master clock can be output to match.

In the delay stop means included in the delay means of the synchronous clock generation circuit according to the sixth aspect, the master clock instruction signal is the k- th delay signal among the first to n-th delay signals.
When the delay signal (k = 1 to n) is designated as the master clock, the delay operation by the (k + 1) th to nth partial delay means is stopped. The delay operation by the n-th partial delay means can be stopped.

In the master clock output circuit according to claim 7 of the present invention, the master clock output means is:
The second specified by the timing control signal from the start of operation
A second period after the predetermined waveform change of the second signal defined by the timing control signal by outputting the n-th delay signal as a master clock until a predetermined waveform change of the signal When the signal delay time of the second signal with respect to the first signal is recognized based on the first to nth sampling delay signals and TR ′ is a predetermined time and ΔT ′ is a signal delay time, the first to nth Of the delayed signals of (1), the signal closest to the signal delayed in (TR'-ΔT ') time phase from the first signal is output as the master clock, so when the predetermined waveform of the second signal changes from the start of the operation. It is possible to quickly output the master clock whose phase is advanced by ΔT ′ from the second signal with the lapse of the first period up to.

Therefore, when there is an external circuit which receives the master clock and operates using the second signal delayed by the signal delay time as the internal clock,
The master clock is promptly supplied to the external circuit so that the phases of the first signal and the second signal coincide with each other with the lapse of the first period from the start of the operation until the predetermined waveform change of the second signal. Can be output.

The synchronous clock generating circuit according to claim 8 is formed with the same configuration as the master clock output circuit according to claim 7, and receives a first reference clock having a predetermined period as a first signal, A first master clock output circuit that receives a first internal clock as a second signal, and a master clock output circuit that has the same configuration as the master clock output circuit according to claim 7, and has a cycle of a predetermined time and a phase of a first reference clock. By providing a second master clock output circuit that receives a different second reference clock as the first signal and receives the second internal clock as the second signal, the first internal clock and the first reference clock are different from each other. The first master clock can be output so that the phases of the second master clock and the second reference clock can be matched, and the second master clock can be output so that the phases of the second internal clock and the second reference clock match. It is possible to output the lock.

[0035]

【Example】

<First Embodiment> FIG. 1 is an explanatory diagram schematically showing a synchronous clock generating circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing the details. As shown in these figures, the DLL unit 10 which is the master clock output circuit forming the main part of the synchronous clock generation circuit is
It comprises a tap delay line 1, a selector 2, an N tap sampling delay line 3, a decoder 4 and a set / reset signal generation circuit 8 (only shown in FIG. 1).

As shown in these figures, the N-tap delay line 1 is connected to the system clock S.S. Reference clock RE whose CLK is obtained via the clock input buffer BF1
F. CLK, and receives n delay signals D0 to D (n-
1) is output. The delay signal Di (i = 0 to 0)
(N-1)) is the reference clock REF. CLK
Is a signal obtained by delaying (i + 1) tap time.

In the N tap delay line 1, n 1 tap delay sections DL0 to DL (n-1) are connected in series. Each 1-tap delay unit DLi is composed of two-stage inverters IG connected in series, and the propagation delay time of the two inverters IG is 1-tap delay time Δt1. Then, the 1-tap delay units DL0 to DL (n-
The signals respectively output from 1) are the delay signals D0 to D0.
It becomes D (n-1).

The number of taps of the N-tap delay line 1 is determined by the phase error detection accuracy (spec), and the delay value of the n-tap is REF. One clock of CLK (one cycle TR)
And

For example, the reference clock REF. If the CLK frequency is 20 MHz and the phase error detection accuracy is 10%, the number of taps is n = 10, and the delay time for one tap is Δt1 =
It will be 5 nsec.

The selector 2 receives the delay signals D0 to D (n-
1) and the decode signal S4 obtained from the decoder 4
Based on the master clock M.P. It is output to the external circuit 20 as CLK. This master clock M. CLK becomes an internal clock output from the synchronous clock generation circuit.

The external circuit 20 receives the master clock M.P.M. due to various factors existing inside the external circuit 20. CLK is the internal clock IN delayed by the designer's unexpected time ΔT2
T. It operates in synchronization with CLK.

The internal clock INT. CL
K is detected on the internal clock detection line L1 and is fed back to the N tap sampling delay line 3 of the synchronous clock generation circuit of the first embodiment via the switch 6.

N-tap sampling delay line 3
Is a reference clock REF. CLK and internal clock IN
T. CLK, the internal clock INT. Using the rising edge of CLK as a trigger, n sampling signals S0 to S (n-1) are output.

In the N tap sampling delay line 3, n 1 tap sampling delay units SDL are connected in series. Each 1-tap sampling delay section SDLi is composed of three inverters IG1 to IG3, the inverters IG1 and IG2 are connected in two stages in series between the input and the output, and the inverters IG2 and IG3 are connected in a loop.

A switch SW0 (PMOS transistor T0) is provided in the preceding stage of the 1-tap sampling delay unit SDL0, the output of the 1-tap sampling delay unit SDLj (j = 0 to (n-2)), and the 1-tap sampling delay. The switch SW (j + 1) (PMOS transistor Tj) is connected to the input of the section SDL (j + 1).
Is inserted, and the PMOS transistors T0 to T (n-1)
The internal clock INT. CLK is commonly applied.

The driving capability of the inverter IG3 is set sufficiently smaller than that of the inverters IG1 and IG2 so that the sampling process by the inverters IG1 and IG2 is hindered when the transistors T0 to T (n-1) are on. To be able to do without.

Therefore, the N tap sampling delay line 3 receives the internal clock INT. CLK at the rising time of CLK. CLK is a signal delayed by 1 to n taps and sampling signals S0 to S (n-1)
Is output to the decoder 4.

The set / reset signal generation circuit 8 uses the internal clock INT. CLK, the internal clock INT. C
Based on LK, the set signal SET and the reset signal RSET are output to the decoder 4 as timing control signals. That is, the set / reset signal generation circuit 8 sets the set signal SET to “H” and reset signal R at the start of operation.
SET is set to "L", and thereafter, the internal clock INT. CL
The set signal SE is triggered by the "H" rising of K.
T is set to "H" and the reset signal RSET is set to "L".

The decoder 4 has sampling signals S0 to S.
(N-1), set signal SET and reset signal RSE
In response to T, the set signal SET is "H" and the reset signal R
When SET is “L”, the decode signal S4 instructing the selection of the delay signal D (n−1) is output to the selector 2,
When the set signal SET is “L” and the reset signal RSET is “H”, the delay time ΔT2 by the external circuit 20 is recognized based on the sampling signals S0 to S (n−1), and the delay signals D0 to D (n−1) are recognized. Of the reference clock R
EF. Decode signal S instructing to select the signal closest to the signal delayed by (TR-ΔT2) with respect to CLK.
4 is output to the selector 2.

The decoder 4 has n AND gates GA0.
To GA (n-1), each AND gate GAj
(J = 0 to (n-2)) outputs the decode signal Qj with one input as the sampling signal Sj and the other input as the inverted signal bar S (j + 1) of the sampling signal S (j + 1). The AND gate GA (n-1) has one input as a sampling signal S (n-1) and the other input as an inverted signal bar S0 of the sampling signal S0, and outputs a decode signal Q (n-1).

The selector 2 includes (2n-1) AND gates GB0 to GB (n-1) and GC0 to GC (n-1).
And two OR gates GD1 and GD2. The AND gate GBj (j = 0 to (n-2)) has a decode signal Qj at one input and a reset signal RS at the other input.
Get an ET. The OR gate GD1 has a decode signal Q (n-1) at one input and a set signal SET at the other input.
Receive.

The AND gate GC0 has one input for the output of the AND gate GB0 and the other input for the delay signal D (n-
2), the AND gate GC1 receives the output of the AND gate GB1 at one input and the delay signal D (n-
3), the AND gate GC (n-3) receives the output of the AND gate GB (n-3) at one input, the delay signal D1 at the other input, and the AND gate GC (n-).
2) receives the output of the AND gate GB (n-2) at one input, receives the delay signal D0 at the other input, and the AND gate GC (n-1) receives the output of the OR gate GD1 at one input and the other input Receives the delay signal D (n-1).

The OR gate GD2 is an AND gate GC0.
The output of the GC (n-1) is used as an input, and the logical sum thereof is set to the master clock M. CLK and output.

The counter 5 uses the reference clock REF. CLK
In response to the reference clock REF. CLK is input, the switch 6 is turned on, and the reference clock REF. The number of clocks of CLK is counted, and when the counted number exceeds 5, the switch 6 is turned off.

The operation of the synchronous clock generating circuit of the first embodiment will be described below. In order to make the description easy to understand, the description will be made assuming that n = 10 and the delay time ΔT2 of the external circuit 20 is (2 · Δt1 + α (<Δt1)).

At the start of the operation, the set / reset signal generation circuit 8 outputs a set signal SET of "H" and a reset signal RSET of "L". At this time, the reset signal RSET of “L” changes to the AND gate GB0 of the selector 2.
To GB (n−2), and the set signal SET of “H” is input to the OR gate GD1, the selector 2 outputs the delay signal D9 (= D (n−1)) to the master clock M.D. Output as CLK.

Therefore, as shown in FIGS. 3 and 4,
Internal clock INT. CLK is the reference clock REF.
It appears with a time delay obtained by adding the delay time ΔT2 (2 · Δt1 + α) of the external circuit 20 to the N tap delay time ΔTN (= cycle TR) in CLK. Then, the reference clock REF. CL
It rises to "H" at time t0 of the third clock of K.

This time t0 is the sampling time of the N tap sampling delay line 3. Therefore,
As shown in FIG. 5, “H” and “L” of the sampling signals S0 to S9 at time t0 are given to the decoder 4.

On the other hand, the internal clock INT. Using the rising edge of CLK as a trigger, the set / reset signal generation circuit 8 causes the set signal SET to fall to "L" and the reset RSET to rise to "H", as shown in FIG.

Then, the AND gate GA in the decoder 4
Of the 1 to GA9, only the AND gate GA1 has 2 inputs (the inverted signal bar S2 of the sampling signal S1 and the sampling signal S2) becomes “H”, so that the decode signal Q
When 1 is "H", the other decode signals Q0, Q2 to Q9 are set to "L" and the decode signal S4 is output.

The selector 2 receiving the decode signal S4 (Q0 to Q9) receives AND gates GB0 to GB (n-
2) and only the output of the AND gate GB1 of the OR gate GD1 becomes “H”, so that the delay signal D7 (=
(N-3)) is the master clock M. Selected as CLK.

Master clock M. CLK is the reference clock REF. CLK (period TR−2 · Δt1), that is, the reference clock REF. It is a signal with a phase advance of 2 · Δt1 with respect to CLK.

As a result, the master clock M. CLK, the internal clock INT.CLK for the external circuit 20 obtained with a delay time ΔT2. CLK and the reference clock REF. Since the phase difference from CLK is α, which is 1 tap delay time Δt1 or less,
Internal clock INT. CLK and the reference clock REF. C
Synchronize with LK.

As a result of the above operation, the synchronous clock generating circuit of the first embodiment is operated by the reference clock REF. CLK 4 ~
At the 5th clock, the reference clock REF. CLK and internal clock INT. CLK so that the phases of the master clock M. CLK is the reference clock REF. Lock to CLK. Therefore, it is possible to lock at a higher speed than the lock time of the conventional DLL circuit (on the order of several μsec).

In addition, the synchronous clock generating circuit component (N
Tap delay line 1, selector 2, N tap sampling delay line 3, decoder 4 and counter 5)
Since all are composed of digital circuits, they are not affected by power supply noise.

The reference clock REF. The number of clocks of CLK is counted, and when the counted number exceeds 5, the switch 6 is turned off. After the output of CLK, the internal clock detection line L1 and the N tap sampling delay line 3 are immediately shut off, and the internal clock INT. The signal propagation of the CLK to the N tap sampling delay line 3 is stopped.

As a result, the internal clock INT. The signal propagation processing to the N tap sampling delay line 3 of CLK is performed by the counter 5 and the switch 6.
By omitting it, the power consumption can be reduced.

In the first embodiment, the signal propagation delay time of the 1-tap delay unit DL and the signal propagation delay time of the 1-tap sampling delay unit SDL are made the same, and the number of stages of the 1-tap delay unit DL and 1-tap sampling are set. Although the number of stages of the delay unit SDL is set to be the same, it is not necessary for both to be the same. However, the N tap delay line 1 uses the reference clock REF. A signal in which CLK is delayed by one cycle can be output. The sampling signal obtained from the N tap sampling delay line 3 causes the decoder 4
Is the master clock M. Internal clock IN for CLK
T. It is necessary to configure so that the delay time of CLK can be detected.

<Second Embodiment> FIG. 6 is a circuit diagram showing a synchronous clock generating circuit according to a second embodiment of the present invention. In the synchronous clock generation circuit of the second embodiment, the N-tap sampling delay line 3 of the DLL unit 10 has an internal clock INT. CLK is the internal clock INT.CLK obtained via the clock input buffer BF3. CLK 'is fed back. The clock input buffer BF3 has the same signal propagation delay time as the clock input buffer BF1.

The synchronous clock generating circuit of the second embodiment is
By providing the clock input buffer BF3 having the same signal propagation delay time as the clock input buffer BF1 on the feedback line to the N-tap sampling delay line 3, the delay time ΔT2 of the external circuit 20 is added to the delay time of the clock input buffer BF1. System clock S.C. The internal clock INT. The phases of CLK can be matched.

<Third Embodiment> FIG. 7 is a block diagram showing a synchronous clock generating circuit according to a third embodiment of the present invention.

The external circuit 23 uses the internal clock INT. C
LK has a function of outputting to another circuit, and outputs the internal clock INT.INT through the clock output buffer BF2.
CLK. Output as OUT. Therefore, the master clock M.M.I. CLK is delayed and the output internal clock INT. CLK. OUT.

The synchronous clock generating circuit of the third embodiment is
Output internal clock INT. CLK. OUT is an output internal clock INT.OUT obtained through the internal clock detection line L2, the switch 6 and the clock input buffer BF3. CL
K. OUT ′ is fed back to the N tap sampling delay line 3 of the DLL unit 10.

Therefore, the synchronous clock generating circuit of the third embodiment outputs the output internal clock I from the external circuit 23 having the function of outputting the internal clock to other circuits.
NT. CLK. OUT and system clock S.C. It is possible to match the phase with CLK. That is, the synchronous clock generating circuit of the third embodiment takes into consideration the system clock S.S.C. in consideration of the delay time generated between the external circuit and other circuits and in the external circuit. CLK and output internal clock INT. CL
K. It is possible to match the phase with OUT.

<Fourth Embodiment> FIG. 8 is a block diagram showing a structure of a synchronous clock generating circuit according to a fourth embodiment of the present invention.

As shown in FIG.
CLK is the reference clock REF.CLK via the clock input buffer BF1. It is output to the phase conversion circuit 7 as CLK. The phase conversion circuit 7 uses the reference clock REF. CLK based on the reference clocks REF. CLK
1 to the DLL unit 11 and the reference clock R
EF. CLK2 is output to the DLL unit 12.

The DLL unit 11 is the DLL unit 1 of the first embodiment.
0 has the same configuration as the reference clock REF. CL
K1 and internal clock INT. CLK1 and the master clock M. CLK1 is output to the external circuit 21.

The external circuit 21 receives the master clock M.P.M. due to various factors existing inside the external circuit 21. CLK1 is the internal clock INT.CLK delayed by a time ΔT21 unexpected to the designer. It operates in synchronization with CLK1.

This internal clock INT. CLK1 is detected on the internal clock detection line L1, and the switch 6
It is fed back to the DLL unit 11 via 1.

The counter 51 uses the reference clock REF. CL
K1 is received to control ON / OFF of the switch 61, and the reference clock REF. The switch 61 is turned on when CLK1 is input, and the reference clock REF. The number of clocks of CLK1 is counted, and when the counted number exceeds 5, the switch 61 is turned off.

Therefore, the DLL unit 11 is similar to the DLL unit 10 of the first embodiment in that the reference clock REF. CLK1
With respect to the reference clock REF. Phase is about 2 for CLK1
ΔT21 Master clock M.2 which is a signal advanced. CLK1
Is output.

As a result, the master clock M. CLK1 is an internal clock INT.CLK obtained by delaying the delay time ΔT21 of the external circuit 21. CLK1 is the reference clock REF. CL
Synchronize with K1.

Like the DLL unit 11, the DLL unit 12 has a first
Of the external reference clock REF. CLK2 and internal clock INT. C
LK2 and the master clock M. CLK2 is output to the external circuit 22.

The external circuit 22 receives the master clock M.P.M. due to various factors existing inside the external circuit 22. CLK2 is the internal clock INT.CLK delayed by a designer's unexpected time ΔT22. It operates in synchronization with CLK2.

This internal clock INT. CLK2 is detected on the internal clock detection line L12, and the switch 6
It is fed back to the DLL unit 12 via 2.

The counter 52 uses the reference clock REF. CL
In response to K2, the switch 62 is controlled to be turned on and off, and the reference clock REF. The switch 62 is turned on when CLK2 is input, and the reference clock REF. The clock number of CLK2 is counted, and when the counted number exceeds 5, the switch 62 is turned off.

Therefore, the DLL unit 12 is the DLL unit 1
1, the reference clock REF. CLK2, a signal delayed by about (cycle TR-ΔT22), that is, the reference clock REF. CLK2, which is a signal whose phase is advanced by about 2 · ΔT22. Output CLK2.

As a result, the master clock M. CLK2 is an internal clock INT.CLK obtained by delaying the delay time ΔT22 of the external circuit 22. CLK2 is the reference clock REF. CL
Synchronize with K2.

As described above, the synchronous clock generating circuit according to the fourth embodiment has the DLL unit 11, the counter 51 and the switch 6.
A first clock synchronization circuit composed of 1 and a DLL unit 12,
Since the second clock synchronization circuit including the counter 52 and the switch 62 is provided, even when clocks of different phases exist between different semiconductor integrated circuits or within the same semiconductor integrated circuit, the delay time by the external circuit with respect to each master clock. Of the two master clocks M. CLK1 and master clock M.C. The CLK selector 2 can be output.

<Fifth Embodiment> FIG. 9 is a circuit diagram showing an internal structure of an N tap delay line in a synchronous clock generating circuit according to a fifth embodiment of the present invention.

As shown in the figure, in addition to the 1-tap delay units DL1 to DL (n-1), the N-tap delay line 1'includes NMOS transistors T11 to T1 (n-1) and switches SW0 to SW (n-). 2) is provided and receives the decode signal S4 (decode signals Q0 to Q (n-1)). The drains of the NMOS transistors T10 to T1 (n-1) are 1-tap sampling delay units SDL1 to SDL.
DL (n-1) is connected to the input section, and the decode signals Q0 to Q (n-2) are applied to the gates.
The sources are commonly grounded. Further, the switch SWj is inserted between the 1-tap delay units DLj (j = 0 to (n−2)) and DL (j + 1).

The switches SW0 to SW (n-2) receive the inverted decode signal bars Q0 to Q (n-2), respectively, and the switches SWk (k = 0 to (n-2)) respectively. Turns off when is "L".

The other structure is the same as that of the synchronous clock generating circuit of the first embodiment shown in FIGS.

The circuit operation will be described by taking as an example the case where the selector 2 outputs the delay signal D2 based on the decode signal S4 in such a configuration.

In this case, the decode signals Q0 to Q (n-
In 2), only the decode signal Q2 is "H" and the rest is "L" (only the inverted decode signal Q2 is "L" and the rest are "H"). Therefore, as shown in Table 1, among the transistors T11 to T (n-1), only the transistor T13 is turned on and the others are turned on. On the other hand, switch S
Among W0 to SW (n−2), only the switch SW12 is turned off and the other switches SW are turned on.

[0096]

[Table 1]

As a result, the 1-tap delay units DL2, D
The L3 is electrically disconnected and the 1-tap delay unit DL3
Since the input section of is fixed to "L", the delay operation between the 1-tap delay sections DL3 to DL (n-1) is stopped.

Thus, the decode signal S4 instructing the selection of the delay signal D2 is the N tap delay line 1 '.
When the input signal is input to, the delay lines of the 1-tap delay units DL0 to DL2 necessary for outputting the delay signal D2 are activated. The operation of unnecessary delay lines after the 1-tap delay unit DL3 is stopped. As a result, the power consumption of the delay line is reduced.

[0099]

As described above, according to the present invention, in the synchronous clock generating circuit according to claim 1, the master clock output means has a predetermined internal clock-related signal defined by the timing control signal from the start of operation. Output the n-th delay signal as the master clock during the first period until the waveform change of the second waveform, and change the second waveform after the predetermined waveform change of the internal clock related signal defined by the timing control signal.
, The internal clock delay time of the internal clock with respect to the reference clock is recognized based on the 1st to nth sampling delay signals, and TR is a predetermined time and ΔT is an internal clock delay time. Of the signals, the signal closest to the signal delayed in (TR-ΔT) time phase from the reference clock is output as the master clock. Therefore, the first period from the start of operation to the time when the predetermined waveform of the internal clock related signal changes With the passage of time, it is possible to quickly output the master clock in which the phases of the reference clock and the internal clock match.

As a result, the number of reference clocks is three.
Since the master clock can be locked to the reference clock within a period of about 5 clocks, the lock time can be significantly shortened.

Further, in the synchronous clock generating circuit according to the second aspect of the present invention, all the constituent means including the master clock output means are configured by digital circuits, so that the synchronous clock generation circuit is resistant to power supply noise.

Further, the switching means of the synchronous clock generating circuit according to claim 3 counts the number of clocks of the reference clock from the start of inputting the reference clock,
When the count number exceeds a predetermined number, the supply of the internal clock related signal to the sampling delay means is stopped.

Therefore, by setting the above-mentioned predetermined number to the minimum number of clocks that secures the period from the start of the operation until the master clock is locked to the reference clock without fail, the sampling delay of the internal clock related signal can be promptly performed after locking. The supply to the means can be stopped.

As a result, the power consumption can be reduced by omitting the signal propagation processing of the internal clock related signal to the sampling delay means, which is unnecessary after locking, by the switching means.

Further, in the synchronous clock generating circuit according to the present invention, the first signal buffer means for buffering the external reference clock and outputting the reference clock, and the internal clock for buffering the internal clock related signal. Further comprising second signal buffer means for
By setting the signal propagation delay times of the second signal buffer means to be the same, the master clock can be output so that the phase of the internal clock matches the phase of the external reference clock.

According to another aspect of the synchronous clock generation circuit of the present invention, the internal clock related signal is the output internal clock for supply to the circuits other than the external circuit, and therefore the phase of the output internal clock is the same as the reference clock. The master clock can be output to match.

Further, in the delay stop means included in the delay means of the synchronous clock generation circuit according to claim 6, the master clock instruction signal is the k- th delay signal among the first to n-th delay signals.
When the delay signal (k = 1 to n) is designated as the master clock, the delay operation by the (k + 1) th to nth partial delay means is stopped. The delay operation by the n-th partial delay means can be stopped.

As a result, the power consumption can be reduced by omitting the delay operation by the (k + 1) th to nth partial delay means by the delay stopping means means.

In the master clock output circuit according to claim 7 of the present invention, the master clock output means is:
The second specified by the timing control signal from the start of operation
A second period after the predetermined waveform change of the second signal defined by the timing control signal by outputting the n-th delay signal as a master clock until a predetermined waveform change of the signal When the signal delay time of the second signal with respect to the first signal is recognized based on the first to nth sampling delay signals and TR ′ is a predetermined time and ΔT ′ is a signal delay time, the first to nth Of the delayed signals of (1), the signal closest to the signal delayed in (TR'-ΔT ') time phase from the first signal is output as the master clock, so when the predetermined waveform of the second signal changes from the start of the operation. It is possible to quickly output the master clock whose phase is advanced by ΔT ′ from the second signal with the lapse of the first period up to.

Therefore, when there is an external circuit which receives the master clock and operates using the second signal delayed by the signal delay time as the internal clock,
The master clock is promptly supplied to the external circuit so that the phases of the first signal and the second signal coincide with each other with the lapse of the first period from the start of the operation until the predetermined waveform change of the second signal. Can be output.

As a result, the number of clocks of the first signal is 3 to
Since the master clock can be locked to the first signal within a period of about 5 clocks, the lock time can be significantly shortened.

The synchronous clock generating circuit according to claim 8 is formed with the same configuration as the master clock output circuit according to claim 7, and receives a first reference clock having a predetermined period as a first signal, A first master clock output circuit that receives a first internal clock as a second signal, and a master clock output circuit that has the same configuration as the master clock output circuit according to claim 7, and has a cycle of a predetermined time and a phase of a first reference clock. By providing a second master clock output circuit that receives a different second reference clock as the first signal and receives the second internal clock as the second signal, the first internal clock and the first reference clock are different from each other. The first master clock can be output so that the phases of the second master clock and the second reference clock can be matched, and the second master clock can be output so that the phases of the second internal clock and the second reference clock match. It is possible to output the lock.

As a result, even when there are internal clocks having different phases between different semiconductor integrated circuits or within the same semiconductor integrated circuit, two clocks having different phases are taken into consideration with respect to the respective clocks by considering the delay time by the external circuit. The master clock can be output.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an internal configuration of a synchronous clock generating circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing details of the first embodiment.

FIG. 3 is a timing diagram showing the operation of the first embodiment.

FIG. 4 is a timing diagram showing the operation of the first embodiment.

FIG. 5 is a timing diagram showing the operation of the first embodiment.

FIG. 6 is an explanatory diagram showing an internal configuration of a synchronous clock generating circuit according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an internal configuration of a synchronous clock generation circuit according to a third embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an internal configuration of a synchronous clock generating circuit according to a fourth embodiment of the present invention.

FIG. 9 is an explanatory diagram showing an internal configuration of an N tap delay line of a synchronous clock generation circuit according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing an internal configuration of a conventional DLL circuit.

11 is a circuit diagram showing an internal configuration of the phase comparator of FIG.

12 is a circuit diagram showing the internal configuration of the charge pump and loop filter of FIG.

13 is a circuit diagram showing an internal configuration of the voltage control delay element in FIG.

[Explanation of symbols]

1,1 'N tap delay line, 2 selector, 3
N tap sampling delay line, 4 decoder, 5,51,52 counter, 6,61,62 switch, 7 phase conversion circuit, 8 set / reset signal generation circuit, 10, 11, 12 DLL section, BF1, BF3
Clock input buffer, BF2, BF21, BF22
Clock output buffer.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 61-70831 (JP, A) JP-A 63-105515 (JP, A) JP-A 2-10922 (JP, A) JP-A 5- 101531 (JP, A) JP-A-8-8730 (JP, A) JP-A-6-301441 (JP, A) Actual development 4-75430 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03L 7/06 H03K 19/003 H03K 19/0175

Claims (8)

(57) [Claims] 1. A synchronous clock generating circuit for generating the master clock to an external circuit which receives the master clock and operates in synchronization with the internal clock delayed by the internal clock delay time, the synchronous clock generating circuit having a predetermined cycle. A delay means is provided for receiving a time reference clock, delaying the reference clock by a first to nth (n> 1) delay time, and outputting a first to nth delay signal. The first to nth partial delay means, which are digital circuits and have a first signal propagation delay time, are provided, and the first to nth partial delay means are continuously connected from the first to the nth. The reference clock is received at the input of the first partial delay means, the outputs of the first to nth partial delay means become the first to nth delay signals, and the nth delay signal is the reference clock. In front Becomes a predetermined time delayed by a signal, receives the internal clock related signal related to the reference clock and the internal clock, when a predetermined waveform change of said internal clock related signal, the reference clock first the first to
Sampling delay means for outputting the first to nth sampling delay signals by delaying and sampling each of the n sampling delay times are provided, and the sampling delay means each comprises a digital circuit and a second signal propagation delay. 1st to nth partial sampling delay means having time, said 1st to nth partial sampling delay means are connected continuously from 1st to nth , and said 1st partial sampling delay means receiving said reference clock input, the output of each partial sample delay means of the first to n is the sampling delay signal of said first to n, the internal clock associated with the sampling delay signal of said first to n The first to n-th delays based on a timing control signal that indicates the presence or absence of the predetermined waveform change of the signal. The apparatus further comprises master clock output means for outputting any one of the signals as the master clock to the external circuit, wherein the master clock output means is related to the internal clock defined by the timing control signal from the start of operation. During the first period until the predetermined waveform change of the signal, the nth delay signal is output as the master clock, and after the predetermined waveform change of the internal clock related signal defined by the timing control signal. For the second period of time, recognizing the internal clock delay time of the internal clock with respect to the reference clock based on the first to nth sampling delay signals, and TR: the predetermined time ΔT: the internal clock delay time , (TR-ΔT) time phase from the reference clock among the first to n-th delay signals A synchronous clock generation circuit that outputs a signal closest to a delayed signal as the master clock. 2. The first to n-th partial delay means each have first and second inverters connected in series between the input and output, and the first and second inverters are connected to the reference clock. Is the first signal propagation delay time, each of the first to nth partial sampling delay means includes third to fifth inverters, and the third and fourth
Inverters are connected in series between the input and output, the fourth and fifth inverters are loop-connected, and the time during which the reference clock propagates through the third and fourth inverters is the second signal propagation delay time. The synchronous clock generation circuit according to claim 1, wherein the master clock output means is a digital circuit. 3. A digital circuit, which receives the reference clock, counts the number of clocks of the reference clock from the start of the operation, and when the count exceeds a predetermined number, the sampling of the internal clock related signal. 3. The synchronous clock generation circuit according to claim 2, further comprising switching means for stopping the supply to the delay means. 4. A first signal buffer means for receiving an external reference clock obtained from the outside and buffering the external reference clock to output the reference clock; and a buffer for the internal clock to relate to the internal clock. The second signal buffer means for outputting a signal is further provided, and the signal propagation delay times of the first and second signal buffer means are set to be the same. The synchronous clock generation circuit according to any one of items. 5. The synchronous clock generating circuit according to claim 1, wherein the internal clock related signal is an output internal clock for supplying to a circuit other than the external circuit. . 6. The master clock output means further outputs a master clock instruction signal for instructing which one of the first to nth delay signals is the master clock, and the delay means. Further receiving the master clock instruction signal, wherein the master clock instruction signal is the kth delay signal (one of k = 1 to n) among the first to nth delay signals.
Is designated as the master clock, the (k +
4. The synchronous clock generating circuit according to claim 1, further comprising delay stop means for stopping the delay operation by the first to nth partial delay means. 7. A first signal having a cycle of a predetermined time is received, and the first signal is delayed by delay times of 1st to nth (n> 1) to output 1st to nth delay signals. Delaying means, each of the delaying means includes first to nth partial delaying means, each of which is a digital circuit and has a first signal propagation delay time, and the first to nth partial delaying means are 1 to n are connected in series, the first signal is received at the input of the first partial delay means, and the output of each of the first to nth partial delay means is set to the first to nth. A delay signal, the nth delay signal is a signal obtained by delaying the first signal by the predetermined time, receives the first signal and a second signal having a cycle of the predetermined time, and outputs the second signal. during, the first signal the first to n sampling delay time of a predetermined signal waveform change First to by respectively delaying samples by
Sampling delay means for outputting n sampling delay signals is further provided, said sampling delay means comprising first to nth partial sampling delay means each comprising a digital circuit and having a second signal propagation delay time. The first to n-th partial sampling delay means are the first to n-th.
Are continuously connected to each other, and receive the first signal at the input of the first partial sampling delay means,
The output of each of the nth partial sampling delay means becomes the first to nth sampling delay signals, the nth sampling delay signal becomes a signal delayed by the predetermined time, and the first to nth sampling delay signals And a timing control signal for instructing the presence or absence of the predetermined waveform change of the second signal, one of the first to nth delay signals is supplied to the master clock to the external circuit. Further comprising a master clock output means for outputting as a first period from the start of operation to the time when the predetermined waveform of the second signal defined by the timing control signal changes. n delay signals are output as the master clock, and the predetermined waveform variation of the second signal defined by the timing control signal is output. A second period after said first through
When the signal delay time of the second signal with respect to the first signal is recognized based on the nth sampling delay signal, and TR ′: the predetermined time ΔT ′: the signal delay time, the first to the first Of the n delayed signals, the signal closest to the signal delayed in (TR'-ΔT ') time phase from the first signal is output as the master clock.
Master clock output circuit. 8. Receiving first and second master clocks respectively, said first and second master clocks respectively being first and second internal clocks delayed by first and second internal clock delay times. First and second that operate in synchronization
9. A synchronous clock generation circuit for generating the first and second master clocks to the external circuit of claim 1, which is formed with the same configuration as the master clock output circuit according to claim 7, and has a period of a predetermined time. 8. A first master clock output circuit that receives the reference clock of claim 1 as the first signal and receives the first internal clock as the second signal, and is formed with the same configuration as the master clock output circuit of claim 7. A second master clock that receives as the first signal a second reference clock whose cycle is the predetermined time and whose phase is different from that of the first reference clock, and which receives the second internal clock as the second signal And an output circuit,
Synchronous clock generation circuit.