JP3461257B2 - Detection circuit and device using this detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection circuit and an apparatus using the detection circuit, and more particularly to converting an external signal such as an optical signal or a magnetic signal into a current signal to obtain a predetermined threshold level (slice level). Is preferably used in a circuit that outputs a signal with reference to.

[0002]

2. Description of the Related Art A detection circuit is, for example, a laser beam printer (LBP) or a compact disc player (C
It is used when horizontal synchronization is achieved for the optical signal scanning such as D).

FIG. 9 is a circuit diagram showing a case where it is used as a horizontal scanning detection circuit for an LBP laser beam. In the figure, when light is incident on a photodiode D as a photosensor, a current corresponding to the amount of incident light flows, and an NPN bipolar transistor (hereinafter referred to as a bipolar transistor) T4 having a base connected to the photodiode D4. Of the NPN bipolar transistor T4, current also flows through the resistor R1 which is the load of the transistor T4. Then, the base potentials of the bipolar transistors T1 and T2 whose bases are commonly connected to the emitter of the bipolar transistor T4 rise.
Here, the size ratio of the bipolar transistors T1 and T2 is 1: L (for example, L = 10). This size ratio can be easily obtained by setting the ratio of the base-emitter junction area to 1: L. Thus, assuming that the photocurrent flowing through the bipolar transistor T1 is 1, the bipolar transistor T2
A current L times the photocurrent flows through the resistor R2. Then, the potential of the output terminal b decreases, the signal is inverted by the output buffer B, and a high level signal is output.

FIG. 10 is a characteristic diagram showing the relationship between the optical signal and the IC output. When an optical signal above a certain slice level is input at time t1, there is a certain delay time and time t
In the vicinity of 2, the IC output changes from L level to H level. In the above circuit, the slice level is defined by the amount of light incident on the photodiode, the resistance value of the resistor R2, and the size ratio of the bipolar transistors T1 and T2. Similarly, when the slice level becomes lower than the slice level at time t3, the IC output is inverted around time t4.

[0005]

In order to maintain the performance, it is required that the slice level be within a certain range with respect to the maximum light amount by the optical system including the light source, etc. (for example, 20 to 50% of the maximum light amount). .

However, in the detection circuit shown in FIG. 9, the photocurrent of the photodiode D is received by the current mirror circuits T1 and T2, and the output is loaded by the resistor R2 which is a passive element. Therefore, the slice level is determined not by the relative value of what percentage of the peak light amount incident on the photodiode D, but by the absolute light amount to the photodiode D.

Therefore, when the detection circuit shown in FIG. 9 is used for several types of LBPs having different laser beam amounts for each model, the resistor R2 is connected to the transistors T1, T2, T4.
Composed of an external resistor provided separately from the IC chip having
It is required to adjust the slice level by external resistance.

However, in the type in which the slice level is adjusted by the external resistance, the load resistance is drawn from the output terminal to the outside, so that a parasitic capacitance of several pF to several tens of pF is generated, and the time constant defined by CR becomes large. , The delay time becomes large. In particular, when trying to set the slice level to a low light amount, it is required to increase the external resistance value, but in this case, the delay time reaches several μsec.

There is also a problem that the jitter performance is significantly deteriorated accordingly. As shown in FIG. 10, the fluctuation of the delay time is jitter, and the large jitter means that the detection position varies, and
Speaking of BP, it leads to lateral shift of characters. Further, in the printer, a higher scanning speed is required as the resolution becomes higher, and accordingly, a good jitter performance is required.

Even in the LBP of the same model in which the laser beam light amount is set to be the same, the light amount input to the sensor is greatly reduced due to the change of the optical system such as the output of the laser beam and the reflectance of the reflection mirror. If you do, you will need to adjust the slice level. Further, in order to make the slice levels uniform, the photosensitivity is required to be accurate. However, the photosensitivity of the entire IC varies due to variations in the sensitivity of the package and the photodiode, and if accuracy is required for the photosensitivity, it becomes a major factor of yield reduction.

An object of the present invention is to provide a highly versatile detection circuit.

Another object of the present invention is to set the slice level to
An object of the present invention is to provide a detection circuit capable of setting a relative value based on the output peak value of a signal source.

[0013]

[Means for Solving the Problems]
Means for achieving the above object is a current mirror circuit having an input terminal connected to a signal supply means and first and second output terminals for flowing a current corresponding to the current supplied to the input terminal. And a first terminal connected to the first output terminal
Active load, a second active load connected to the second output terminal and the external output terminal, and a control electrode of the second active load according to a voltage value or a current value of the first output terminal. and a control circuit for controlling the potential, the current mirror
-The circuit is equipped with a current source for the idling current.
The detection circuit is characterized in that

Means for achieving the above object are as follows: an input terminal connected to the signal supply means, and first and second output terminals for flowing a current corresponding to the current supplied to the input terminal. A current mirror circuit, a first active load connected to the first output terminal, a second active load connected to the second output terminal and an external output terminal, and a first active load connected to the first output terminal.
A control circuit for controlling the potential of the control electrode of the second active load according to the voltage value or the current value of the output terminal of the second active load, and the current flowing to the first output terminal is the second circuit. It is designed to be larger than the current flowing through the output terminal .
The idling current through the current mirror circuit.
The detection circuit is characterized by being provided with a current source for switching .

Means for achieving the above object are as follows: an input terminal connected to the signal supply means, and first and second output terminals for passing a current corresponding to the current supplied to the input terminal. A current mirror circuit, a first active load connected to the first output terminal, a second active load connected to the second output terminal and an external output terminal, and a first active load connected to the first output terminal.
A peak hold circuit for holding the potential of the control electrode of the second active load according to the peak current flowing through the second output terminal, and the current flowing through the first output terminal is the second output. It is designed to be larger than the current flowing through the terminal, and the current mirror circuit has an idling current.
The detection circuit is characterized in that a current source for flowing a current is provided .

Means for achieving the above object are as follows: an input terminal connected to the signal supply means, and first and second output terminals for flowing a current corresponding to the current supplied to the input terminal. A current mirror circuit, a first active load connected to the first output terminal, a second active load connected to the second output terminal and an external output terminal, and a first active load connected to the first output terminal.
A transistor having a control electrode connected to the output terminal of the first active terminal and a main electrode connected to the control electrode of the second active load, the transistor being turned on or off in response to a current flowing to the first output terminal. , wherein the first and the current flowing through the output terminal is configured to be larger than the current flowing through the second output terminal, the said current mirror circuit Aidori
The detection circuit is characterized by being provided with a current source for supplying a ringing current .

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic structure of a detection circuit according to the present invention. The detailed circuit configuration will be described later with reference to the drawings starting from FIG.

Sin is an input terminal of the current mirror circuit 2 and is connected to a signal supply means (not shown) in FIG. Reference numerals a and b are output terminals of the current mirror circuit 2.

Reference numeral 6 is a first load and an active element is used. The active load 6 is the first output terminal a of the mirror circuit 2.
It is connected to the.

A second load 4 is an active element. This active load 4 is the second output terminal b of the mirror circuit 2.
It is connected to the. The terminal b is an output terminal for outputting a signal to the outside of the detection circuit.

A control circuit 3 controls the potential of the control electrode of the active load 4. That is, the current flowing through the second active load 4 is controlled according to the voltage value or the current value of the terminal b.

Here, the ratio of the current supply capacities of the two active loads 4 and 6 or the ratio of the current supply capacities of the two output terminals of the current mirror circuit is set to an appropriate ratio in advance.

When the input signal current is is supplied from the signal supply means to the input terminal Sin, N times the current is is flows to the output terminals a and b of the mirror circuit 2 according to the current is.

N is a ratio determined by the current supply capability of the transistors forming the current mirror circuit 2.

The control circuit 3 is connected to the output terminal a, and sets the potential of the control electrode (gate or base) of the active load so that a current flows through the active loads 4 and 6 when the potential of the terminal a reaches a predetermined potential. Control.

At this time, if the current supply capacity of the two active loads 4 and 6 is set to 1: M, is.N /
A current of M flows, and a current of isN flows to the terminal a.
Thus, at the terminal b, one-Mth of the peak value of the current is
The output is switched with the threshold value.

Further, the signal supply means 1 is not limited to a means for converting an external signal into a current as long as it can supply a current. In addition, the means for converting an external signal into a current is not limited to the one for converting an optical signal into a current signal, and may be a means for converting a magnetic signal or the like into a current signal.

Specifically, it is a photosensor or a magnetic sensor, and a typical example of the former is a photodiode.

The signal supply means may be integrated on the same IC chip as the detection circuit of the present invention.

The current mirror circuit used in the present invention can be constructed using field effect transistors or bipolar transistors.

The active load used in the present invention is 1
One or more field effect transistors or one or more bipolar transistors may be used.

When a MOS transistor is used as an active load, the write range is compressed to the square root of Ip (Ip indicates a photocurrent), and when a bipolar transistor is used, it is logarithmically compressed to In (Ip). , A wide dynamic range can be obtained.

The current supply capability of the current mirror circuit or active load can be determined by the area of the base-emitter junction of a bipolar transistor and the gate width of a MOS transistor.

When a bipolar transistor having multiple emitters is used as an active load,
The current supply capacity is determined by the sum of the areas of the emitter junctions.

Further, a plurality of transistors are connected to each active load 4
Or when used for 6, a plurality of transistors are connected in parallel so that a source (emitter) and a drain (collector) as main electrodes are commonly connected, and a control electrode (gate or base) is also commonly connected. To do.

[0037]

EXAMPLES Examples of the present invention will be further described below.

(Embodiment 1) FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a signal supply means for supplying a current signal (photodiode D here), 2 is a photodiode connected to the photodiode D, and a current mirror which outputs a first output terminal a and a second output terminal b. Circuits 3 are switch means (here, PMOS transistor M1) controlled based on the voltage value or current value of the first output terminal a, and 4 are active loads (here, PMOS transistor) connected to the second output terminal b. Transistors M3), 5 are capacitance means (here, capacitance C) for holding the peak value of the voltage value or current value, and 6 is an active load (here, PMOS transistor M2) connected to the first output terminal a. is there.

The capacitance means 5 need not be specially formed as a capacitance element as long as the capacitance value due to the parasitic wiring capacitance or parasitic gate capacitance has a sufficient value.

The current mirror circuit 2 includes bipolar transistors T1 to T3 whose bases are commonly connected, a bipolar transistor T4 whose emitter is connected to the commonly connected bases, and one terminal which is connected to the commonly connected bases. It consists of a resistor R1. The collector of the bipolar transistor T4 is connected to a power source (Vdd) as a reference voltage source, and the base is connected to the anode side of the photodiode D and the collector of the bipolar transistor T1. Incidentally, a reverse bias voltage is usually applied to the photodiode having a PN junction.

The size ratio of the bipolar transistor T1 and the bipolar transistors T2 and T3 is 1: N (N> N).
1), the size ratio between the PMOS transistor M2 and the PMOS transistor M3 is 10: M (M <10).

The peak hold operation in the above circuit will be described below.

Now, the potentials of the gate electrodes of the PMOS transistors M2 and M3 are in the vicinity of the power supply voltage Vdd, and PM
The OS transistors M2 and M3 are in the off state in which almost no current flows. Since no current flows through the current mirror circuit when no photocurrent is input, the potentials of the first and second output terminals a and b in the floating state are near Vdd.

Here, when light is incident on the photodiode D, a current corresponding to the amount of incident light flows and the base of the bipolar transistor T is connected to the photodiode D.
The base potential of 4 rises and a current flows through the NPN bipolar transistor T4. The base potentials of the bipolar transistors T1 to T3 whose bases are commonly connected to the emitter of the bipolar transistor T4 also rise. As described above, the size ratio of the bipolar transistors T1, T2 and T3 is 1: N.
Photocurrent flows through 1 and bipolar transistors T2 and T3
A current N times as high as the photocurrent can flow through.

However, the PMOS transistor M2 is OF
Since it is in the F state, no current can flow through the PMOS transistor M2. When the potential of the first output terminal a drops from the Vdd level and approaches the ground potential as the reference voltage, P
The switch means composed of the MOS transistor M1 is turned on. Then, the gate potential of the PMOS transistor M2 lowers and approaches the ground potential as the reference voltage PM
The OS transistor M2 is turned on so that the current can flow.

Here, if the gate-source potential difference of the PMOS transistor M2 is Vgs2, the amount of current (IDpm2) that the PMOS transistor M2 can flow is given by IDpm2 = β2 (Vgs2-Vth) ² . Here, β2 is the mutual conductance of the MOS transistor. Expressing the photocurrent as Ip, if condition (1) β2 (Vgs2-Vth) ² <N · Ip, the first output terminal a is at low level, and condition (2) β2 (Vgs2-Vth) ² > N · If it is Ip, the first output terminal a becomes High level, and PM
Since the OS transistor M2 is an active load, the first output terminal a is immediately set to the high level at the moment when the condition (2) is satisfied, and the switch means composed of the PMOS transistor M1 is closed.

As a result, a voltage satisfying the relation of IDpm2 = β2 (Vgs2-Vth) ² = N · Ip is written in the gate electrode (or the gate electrode and the capacitor C1) of the PMOS transistor M2, and the peak hold can be achieved. .

Next, setting and output of the slice level will be described.

Since the size ratio of the PMOS transistor M2 and the PMOS transistor M3 is 10: M (M <10), the current supply capacity of the PMOS transistor M3 is PM.
It becomes M / 10 (M <10) of the OS transistor M2.
When the equation of the above condition (1) is applied to the PMOS transistor M3, the current supply capacity is M / 10, so the second output terminal b outputs a low level at M / 10 of the peak current value. That is, the second output terminal b outputs a Low level signal with a light quantity of M / 10 of the peak light quantity.

As described above, according to the present invention, by using the active load, a simple and high-speed peak hold can be achieved, and the output from the second output terminal can be steep.

Further, according to the present invention, since the peak hold function is provided and the slice level is determined on the basis of this peak value, it is not necessary to consider the problems of sensitivity variation and light quantity change. Also, even when the slice level is set to a low light level, there is no large parasitic capacitance as in the past,
The delay time does not reach several μsec.

(Embodiment 2) FIG. 3 shows a detection circuit according to another embodiment of the present invention. The part of the current mirror circuit 2 is configured using the same circuit as that shown in FIG. 2, for example. The difference from the circuit of the first embodiment is that the capacitance means 5 is configured by connecting the capacitance C1 and the capacitance C2 in series, and the connection point between the capacitance C1 and the capacitance C2 is connected to the PMOS transistor M3 serving as an active load. ,
The other terminal of the capacitor C1 is connected to the PMOS transistor M2 and the PMOS transistor M1 which are active loads. In the circuit configured as shown in FIG. 4, the PMOS transistor M
The size ratio between 2 and the PMOS transistor M3 may be 1: 1. Since the voltage applied to the PMOS transistor M2 and Vdd are capacity-divided to the gate of the PMOS transistor M3, the voltage supply is applied to the PMOS transistor M3. The capacity is smaller than that of the PMOS transistor M2 and is smaller than the peak light quantity (the value is defined by the capacity ratio of the capacity C1 and the capacity C2) to the second output terminal b.
Outputs a low level signal.

Furthermore, the present invention can improve the jitter performance which is the fluctuation of the delay time shown in FIG.
As a result of earnest studies to improve the jitter performance, the present inventor has found that the three major causes of jitter are as follows.

(1) Fluctuation of light source (2) Shot noise of IC including current mirror circuit (3) Fluctuation of slice level of output buffer due to power supply noise In the present invention, the slice level is set inside the IC. , The large parasitic capacitance is drastically reduced, especially the above (1),
Jitter due to (3) is greatly reduced.

The jitter caused by the above (1) is as follows. The delay time τ depends on the light quantity Ip, and the delay time τ increases as the light quantity decreases. Therefore, if the amount of light varies by ΔIp, the delay time Δτ also varies, that is, jitter. The size of the jitter is given by:

Δτ = (∂τ / ∂Ip) × ΔIp At this time, if τ is small, naturally Δτ also becomes small. In the present invention, since the slice level is set inside the IC, a large parasitic capacitance does not occur and the delay time τ becomes small.
Along with this, the jitter Δτ is similarly improved.

Next, the improvement of the jitter caused by the above (3) will be described with reference to FIG.

An output buffer is provided when actually manufacturing an IC, but jitter occurs when a signal is sent to this output buffer. Broadly interpreting the IC relating to the present invention, the signal current (photocurrent Ip) is converted into a voltage by the load, and this voltage change is transmitted to the output buffer. The output buffer has a value with this voltage change (slice level)
A signal is output when the value exceeds. If the power supply voltage fluctuates,
The slice level fluctuates. That is, it has a certain width ΔV. On the other hand, the voltage change caused by the signal current requires time. If the time derivative of this voltage change is g, the jitter is represented by ΔV / g. If this g is large, the jitter is small. In the present invention, the delay time τ becomes small.
That is, g increases and jitter decreases.

(Embodiment 3) FIG. 5 is a circuit diagram showing a detection circuit according to another embodiment of the present invention. The detection circuit of FIG. 5 is manufactured as a one-chip monolithic IC on a silicon semiconductor substrate.

In the present embodiment, the gate terminal of the PMOS transistor M2 is connected with a minute current source Isl of about several tens pA in addition to the peak holding capacitance C.

Now, considering a situation in which a sufficient time has passed after the power is turned on, the potential of the gate electrode of the PMOS transistor M2 reaches very close to the power supply voltage Vdd by the minute current source Isl. This is the reset state. The reset method is not limited to the one using the minute current source, and the reset potential may be set from the outside or the inside by the reset signal via the reset switch.

Further, in this embodiment, the size ratio of the input bipolar transistor T1 and the output bipolar transistors T2 and T3 of the current mirror circuit is 1: 5. As a result, a photocurrent generated in the photodiode D flows through the bipolar transistor T1, and a current five times as large as this photocurrent flows through the bipolar transistors T2 and T3. For example, when the photocurrent is 10 μA, a current of 50 μA can flow through the bipolar transistors T2 and T3.

Further, in this embodiment, the size ratio of the PMOS transistor M2 and the PMOS transistor M3 is set to 10: 3.
And Therefore, the current supply capacity of the PMOS transistor M3 is 3/10 of that of the PMOS transistor M2. Therefore, in this embodiment, the second output terminal b outputs the Low level with the light amount of 3/10 = 30% of the peak. Then, this output is output via the buffer amplifier B. In this embodiment, the slice level can be set to 30% of the peak light amount.

Fourth Embodiment In this embodiment, the slice level is changed by changing the size ratio between the bipolar transistor T2 and the bipolar transistor T3 without changing the size ratio between the PMOS transistor M2 and the PMOS transistor M3. is there.

That is, in FIG. 5, the size ratio between the PMOS transistor M2 and the PMOS transistor M3 is 1: 1 and the size ratio between the bipolar transistor T2 and the bipolar transistor T3 is 10: 3. Also in the present embodiment, the slice level can be set to 30% of the peak light amount as in the third embodiment.

(Embodiment 5) FIG. 6 is a circuit diagram showing a detection circuit according to another embodiment of the present invention. In the present embodiment, as shown in FIG. 6, the idling current source Is2 is connected to the first output terminal a side of the PMOS transistor M2, and the idling current source I2 is connected.
s3 is connected to the second output terminal b side of the PMOS transistor M3, and the idling current source Is4 is connected to the collector side of the bipolar transistor T1. Also, P
A level shift circuit 7 is provided between the MOS transistor M1 and the first output terminal a.

The present embodiment is intended to improve the peak writing accuracy and the rising characteristics of the current mirror circuit.

Generally, even if a signal is applied to the base of a bipolar transistor, the collector current does not flow immediately and a certain delay occurs. Therefore, the current mirror circuit composed of bipolar transistors also has a delay from the input of the current signal to the shift to the current mirror operation. In this embodiment, in order to improve the rising characteristics of the current mirror circuit, a current is supplied from the idling current source Is4 and a base current is supplied, and a current is supplied from the idling current sources Is2 and Is3 to the output terminal of the current mirror circuit. Is supposed to flow. Since the size ratio of the bipolar transistor T1 to the bipolar transistors T2 and T3 is 1: 5, the idling current source I
Five times the current value from s4 is the idling current source I
Set to be supplied from s2 and Is3.

In this embodiment, the first output terminal a and PM
By providing the level shift circuit 7 between the gate electrode of the OS transistor M1 and the gate electrode of the OS transistor M1, the gate potential of the PMOS transistor M1 is raised above the potential of the terminal a to improve the peak write accuracy. The reason is as follows.

The accuracy of peak writing is required to have no delay between the potential of the first output terminal a and the opening and closing of the switch. In the case where there is no level shift, in order for the PMOS transistor M2 to flow a current, the potential of the first output terminal a is lowered only by 2Vth of the threshold voltage Vth of the PMOS transistor M2 and the threshold voltage Vth of the switch M1 and is effective. It becomes writing. Therefore, 2 Vth is a useless voltage drop, and this amount leads to delay in opening / closing of the switch. If there is a delay in closing the switch, overwriting will occur. If the level shift circuit shifts 2Vth in advance, there will be no unnecessary voltage drop and overwriting will not occur.

(Sixth Embodiment) FIG. 7 is a circuit diagram showing a detection circuit according to still another embodiment of the present invention. In the present embodiment, as shown in FIG. 7, PNP bipolar transistors T4 and T5 were used as active loads without using PMOS transistors. The gate of the PNP bipolar transistor T4 and the gate of the PNP bipolar transistor T5 are commonly connected, and both gates are grounded via the PMOS transistor M4 and connected to Vdd via the resistor R3 having a relatively large resistance value. The gate of the PMOS transistor M4 has capacitance C and PM
It is connected to the OS transistor M1. In this embodiment, the size ratio between the bipolar transistor T1 and the bipolar transistors T2 and T3 is 1: 5, and the size ratio between the PNP bipolar transistor T4 and the PNP bipolar transistor T5 is 10: 3. Therefore, P
The current supply capacity of the NP bipolar transistor T5 is PN
It is 3/10 of the P bipolar transistor T4.

The PNP bipolar transistor T4
The amount of current (IDpm4) that can flow is given by IDpm4 = Ies · exp (q · Vbe / kT).

If the photocurrent is expressed as Ip, the condition (1) Ies · exp (q · Vbe / kT) <5Ip
If so, the first output terminal is at a Low level condition (2) Ies · exp (q · Vbe / kT)> 5Ip
Then, the first output terminal becomes High level, and since the PNP bipolar transistor T4 is an active load, the first output terminal a immediately becomes High level and the PMOS transistor M1 is turned off at the moment the condition (2) is satisfied. It becomes a state.

As a result, a voltage satisfying the relation of IDpm4 = Ies · exp (q · Vbe / kT) = 5Ip is written in the gate electrode and the capacitance C of the PMOS transistor M4, and the peak hold can be achieved.

In this embodiment, the PNP is used as described above.
The current supply capacity of the bipolar transistor T5 is 3/10 of that of the PNP bipolar transistor T4, and the second output terminal b is Low at the light amount of 3/10 = 30% of the peak.
The level is output, and the slice level can be set to 30% of the peak light amount also in this embodiment.

FIG. 8 is a schematic diagram showing a laser beam printer (an electrophotographic apparatus using laser light as light for exposure) in which the detection circuit of the present invention is used.

Reference numeral 101 is a laser light source having a semiconductor laser which emits laser light, 102 is a polygon mirror, and 1 is a polygon mirror.
Reference numeral 03 denotes a mirror, which constitutes an optical system for exposure. 1
Reference numeral 04 is a photoconductor, and 105 is a controller.

The detection circuit of the present invention is provided in the horizontal scanning detection circuit 106 together with the light receiving element in order to synchronize the timing of horizontal scanning of one line and the timing of rotation of the photosensitive member.

The laser light emitted from the laser light source 101 is horizontally scanned by the polygon mirror 102 and the mirror 1 is scanned.
It is irradiated onto the surface of the photoconductor through 03. The circuit 106 detects the laser beam for each horizontal scanning, and the timing of receiving the laser beam is fed back to the controller 105. As a result, the horizontal scanning timing in the SH direction and the scanning timing in the rotational direction VH of the photoconductor are synchronized. It should be noted that the developing device, the charging device, and the conveying means for the recording medium are omitted in FIG.

[0080]

As described above, according to the present invention,
By using an active load, a simple and high-speed peak hold is possible, and a steep output from the output terminal can be obtained. Further, in the present invention, since the peak hold function is provided and the slice level is determined by this peak value, it is not necessary to consider the problems of sensitivity variation and light amount change. Even when the slice level is set to a low light amount, the delay time does not reach several μsec.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an outline of a detection circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a partial circuit diagram showing another example of the above embodiment.

FIG. 4 is a diagram for explaining the effect of improving jitter according to the present invention.

FIG. 5 is a circuit diagram showing a detection circuit according to another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a detection circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a detection circuit according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of a laser beam printer having a detection circuit according to the present invention.

FIG. 9 is a circuit diagram showing a case where it is used as a horizontal scanning detection circuit for an LBP laser beam.

FIG. 10 is a characteristic diagram showing a relationship between an optical signal and an IC output.

[Explanation of symbols]

1 Signal supply means 2 Current mirror circuit 3 switch means 4,6 Active load 5 capacity means 7 Level shift circuit C, C1, C2 capacity B output buffer D photodiode Is1 to Is4 current source M1 to M4 PMOS transistors R1 to R3 resistance T1 to T3 NPN bipolar transistor T4, T5 PNP bipolar transistor

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Claims (29)

(57) [Claims] 1. An input terminal connected to the signal supply means,
A current mirror circuit having first and second output terminals for flowing a current corresponding to the current supplied to the input terminal; a first active load connected to the first output terminal; A second active load connected to the second output terminal and the external output terminal, and for controlling the potential of the control electrode of the second active load according to the voltage value or current value of the first output terminal A control circuit,
Has, for supplying an idling current to said current mirror circuit
The detection circuit is provided with a current source of . 2. The detection circuit according to claim 1, wherein the control electrodes of the first and second active loads are commonly connected. 3. The detection circuit according to claim 1, wherein the control circuit includes a transistor having a control electrode connected to the first output terminal. 4. The detection circuit according to claim 1, wherein the control circuit has means for selecting one of a high impedance state and a state in which the control electrode of the second active load is held at a predetermined potential. A detection circuit characterized by the above. 5. The detection circuit according to claim 1, wherein the control circuit includes a level shift circuit that level-shifts the potential of the first output terminal. 6. The detection circuit according to claim 1, further comprising a transistor for controlling a potential of a control electrode of a transistor forming the current mirror circuit. 7. The detection circuit of claim 1, wherein said detection circuit control electrodes of the first and second active load, characterized in that the capacitively coupled. 8. The detection circuit of claim 1, wherein the first and the detection circuit by the current source to the second control electrode of the active load, characterized in that it is connected. 9. The detection circuit according to claim 1 , wherein the current source causes a current to flow from the power supply to the first and second output terminals. 10. The detection circuit according to claim 1, wherein the control circuit includes a transistor connected to the control electrodes of the first and second active loads and a capacitive element connected to the control electrode of the transistor. A detection circuit including. 11. The detection circuit according to claim 1, wherein the control circuit includes a transistor having a control electrode connected to the first input terminal and one of the main electrodes connected to a reference voltage source. Detection circuit. 12. The detection circuit according to claim 1, wherein a buffer amplifier is connected to the external output terminal. 13. The detection circuit according to claim 1, wherein the current supply capability of the first active load and the current supply capability of the second active load are different. 14. The detection circuit according to claim 1, wherein the current supply capability of the transistor connected to the first output terminal of the current mirror circuit and the current supply capability of the transistor connected to the second output terminal of the current mirror circuit. , A detection circuit characterized by different. 15. The detection circuit according to claim 1, wherein a current flowing through the first output terminal is larger than a current flowing through the second output terminal. 16. The detection circuit according to claim 1, wherein the detection circuit is a one-chip IC. 17. A device comprising: the detection circuit according to claim 1; and a light source for generating light incident on a photosensor as the signal supply means. 18. The apparatus according to claim 17 , wherein the apparatus is a laser printer. 19. A current mirror circuit having an input terminal connected to a signal supply means and first and second output terminals for flowing a current corresponding to the current supplied to the input terminal, and the first mirror circuit. A first active load connected to the output terminal of the first output terminal, a second active load connected to the second output terminal and an external output terminal, and a voltage value or a current value of the first output terminal A control circuit for controlling the potential of the control electrode of the second active load,
And a current flowing through the first output terminal is larger than a current flowing through the second output terminal, and an idling current flows through the current mirror circuit.
The detection circuit is provided with a current source of . 20. The detection circuit according to claim 19 , wherein the control electrodes of the first and second active loads are commonly connected, and the control circuit is a control circuit connected to the first output terminal. A detection circuit comprising a transistor having an electrode, wherein the transistor sets a control electrode of the second active load to either a high impedance state or a state in which the control electrode is held at a predetermined potential. 21. The detection circuit according to claim 19 , wherein the control electrodes of the first and second active loads are capacitively coupled to each other, and the current supply capacities of the first and second active loads are the same. A detection circuit characterized by being. 22. The detection circuit according to claim 19 , wherein the current supply capacity of the second active load is lower than the current supply capacity of the first active load. 23. The detection circuit according to claim 19 , wherein the transistor connected to the first output terminal of the current mirror circuit is connected to the second output terminal of the current mirror circuit due to the current supply capability of the transistor. A detection circuit characterized in that the transistor has a low current supply capability. 24. A current mirror circuit having an input terminal connected to a signal supply means and first and second output terminals for flowing a current corresponding to a current supplied to the input terminal; A first active load connected to the output terminal of the first output terminal, a second active load connected to the second output terminal and the external output terminal, and a second active load connected to the first output terminal according to the peak current flowing through the first output terminal And a peak hold circuit for holding the potential of the control electrode of the active load, the current flowing to the first output terminal is larger than the current flowing to the second output terminal. The current mirror circuit has an idling current flowing through it.
The detection circuit is provided with a current source of . 25. The detection circuit according to claim 24 , wherein the control electrodes of the first and second active loads are commonly connected, and the control circuit is a control circuit connected to the first output terminal. A detection circuit comprising a transistor having an electrode, wherein the transistor sets a control electrode of the second active load to either a high impedance state or a state in which the control electrode is held at a predetermined potential. 26. The detection circuit according to claim 24 , wherein the control electrodes of the first and second active loads are capacitively coupled to each other, and the current supply capacities of the first and second active loads are the same. A detection circuit characterized by being. 27. The detection circuit according to claim 24 , wherein the current supply capacity of the second active load is lower than the current supply capacity of the first active load. 28. The detection circuit of claim 24, wherein from the first current supply capability of the transistor connected to the output terminal of the current mirror circuit is connected to the second output terminal of said current mirror circuit A detection circuit characterized in that the transistor has a low current supply capability. 29. A current mirror circuit having an input terminal connected to a signal supply means and first and second output terminals for supplying a current corresponding to the current supplied to the input terminal, and the first mirror circuit. A first active load connected to the output terminal, a second active load connected to the second output terminal and an external output terminal, a control electrode connected to the first output terminal, and a second active load connected to the first output terminal. A main electrode connected to the control electrode of the active load, and
A transistor that is turned on or off in response to a current flowing through the output terminal of the first output terminal, and the current flowing through the first output terminal is larger than the current flowing through the second output terminal . Since an idling current is passed through the current mirror circuit
The detection circuit is provided with a current source of .