JP3457720B2 - Test facilitation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention relates to a so-called boundary
The present invention relates to a test facilitation circuit called a scan circuit. [0002] 2. Description of the Related Art In recent years, with the increasing integration of LSIs,
How to test the quality of the manufactured LSI efficiently
Is one of the big issues.
Various tests mounted inside the LSI to perform efficiently
An easy circuit has been proposed. One of such test facilitation circuits is:
There is a so-called boundary scan circuit. This bounder
The rescan circuit has a number of free circuits around the circuit under test.
Flip-flops and flip those flip-flops
Connected to Leeds to configure a shift register,
Test data is sent serially to the shift register,
After sending, the test data is sent to the circuit under test.
Signals supplied in parallel and generated by the circuit under test
Into the flip-flops in parallel.
Real-time transmission, which corrects the operation of the circuit under test
It is usually a circuit configured to test for abnormalities. [0004] FIG.
Circuit block showing parts related to two flip-flops
FIG. 4 is a timing chart. Illustrated
The serial output data SO of the circuit is
Connected to become data SI to form a shift register
Is done. In normal operating mode, test enable
Signal T is at the "L" level,
The kusa 10 converts the input data DI as it is to the output data DO.
And output. In the test mode, as shown in FIG.
When the test enable signal T is switched to "H" level
As a result, the multiplexer 10 is connected to the latch circuit 11
Is switched to a state of passing the output of This test
In the mode, first, the shift enable signal S is
It is switched to the 'H' level. This allows serial input
Force data SI is flipped via multiplexer 12
The signal is transmitted to the input terminal of the flop 13. Its state
In section T of FIG.₁ As shown in FIG.
And this flip-flop is connected many times.
Test data is sent to the subsequent shift register
It is. When the transmission of the test data is completed, the section T_Two
As shown in FIG. _{_} To 'H' level
, The latch of the latch circuit 11 is temporarily released ("H" level).
The latch shall be released by the bell)
The data of the flop 13 is taken into the latch circuit 11 and
Latch. The data taken into the latch circuit 11 is
Sent to circuit under test via multiplexer 10
It is. Next, the section T_Three As shown in the figure, shift rice
By switching the cable signal S to the ‘L’ level,
The output of the circuit under test, that is, the output of this boundary scan circuit
In a state where the input data DI passes through the multiplexer 12
Is switched, and one clock pulse TCK is
Input data DI (output of the circuit under test)
The data is taken into the flip-flop 13. After that, the scan enable signal SI is sent again.
The level is set to "H" level, and a clock pulse TCK is sent.
Then, the test target taken into the flip-flop 13
The circuit response data is sequentially shifted and output to the outside.
The data under test is used to determine the quality of the circuit under test.
It is. Also, serial output of response data of the circuit under test and
At the same time, the next test data is serially input. [0008] SUMMARY OF THE INVENTION
To perform a pass / fail test on the circuit under test using
First, send the test data pattern serially,
Each flip-flop 1 of the boundary scan circuit
It is necessary to set the test pattern in
When the scale of the strike circuit is large, the boundary
The number of flip-flops 13 in the can circuit becomes enormous,
It takes time to set the data pattern,
When testing a circuit under test, a large number of data
It is necessary to repeat the test after setting the turn, the test
Requires a lot of time. [0009] In view of the above circumstances, the present invention provides a so-called bow.
Reduce test time in dirty scan circuits
The porpose is to do. [0010] [MEANS FOR SOLVING THE PROBLEMS]
Ming's test facilitation circuit is
The test data is supplied in parallel to the circuit under test, and the test
Response data of the circuit under test due to data supply
Shift register that takes in parallel and sends out serially
In a test facilitation circuit with (1) Invert test data sent serially
Data inversion to generate new test data
Road (2) The test target that is caused by the supply of test data before inversion
Supply of test data and test data after inversion
And the response data of the circuit under test caused by the
This allows the data compression circuit to generate new response data.
It is characterized by having a road. [0011] The test facilitating circuit according to the present invention transmits serially.
Invert the test data that was
Send test data because it is used
The number of clocks to halve, and therefore test time
Is almost halved. Further, the test facilitating circuit of the present invention has
A compression circuit is provided to compress the response data of the circuit under test.
Response data of the circuit under test
When sending, the number of clocks is halved, and
Simultaneous sending of answer data and sending of test data
Can be done. [0013] Embodiments of the present invention will be described below. Figure
1 is one of the test facilitation circuits of one embodiment of the present invention.
Circuit block showing parts related to flip-flops
FIG. 2 and FIG. 2 are timing charts. Figures 3 and 4
The same elements as those of the conventional example shown in FIG.
The same reference numerals are given to the same reference numerals, and differences will be described.
You. The circuit shown in FIG.
Inverter 20 for inverting, output of latch 11 and its output
A multiplexer that inputs the inverted output of
Lexer 21, AND gate 22, and data referred to in the present invention.
Exclusive OR (EO) which is an example of a data compression circuit
R) A gate is provided. The mode switching signal M is
Section T at "L" level₁ ~ T_Three Then, the conventional example mentioned above
And the flip-flop 13 is tested.
Response data of the reset circuit is stored. Then, in this embodiment,
Is section T_Four Are added, and the section T_Four Then first mode
The switching signal M changes to "H" level. Then, multi
The multiplexer 21 outputs the inverted output of the latch circuit 11.
Is switched to the new test data.
To be tested via the multiplexers 21 and 10
Input to the road. Also with it, flip-flops
Response due to test data before reversal stored in 13
Data is output via the AND gate 22 and EOR
The signal is input to one input terminal of the gate 23. Latch circuit
11 is the input data DI
Is input to the other input terminal of the EOR gate 23 as
From the EOR gate 23 to the test data before and after the inversion
The response data to the response is output in a compressed form.
Then, the shift enable signal S is still at the ‘L’ level.
The compressed response data is passed through the multiplexer 12
At the timing when the clock pulse TCK is input.
The compressed response data is stored in the flip-flop 13.
Will be delivered. Thereafter, the shift enable signal S is changed to the "H" level.
Is switched to the bell and the clock pulse TCK is sent.
The compressed response data is sent out serially. As described above, in the above-described embodiment, once the feed
Invert the test data and use it again as test data
Compress the response data before and after inversion and send it out.
As a result, the number of test patterns to be sent is halved,
Time is reduced. Here, the conventional example described above (FIGS.
4) and this embodiment (Figs. 1 and 2) are required for testing
Comparing the number of the various clock pulses, the result is as follows. A flip-flop constituting a shift register
NFF is the number of test data, and N is the number of test data required for the test.
Assuming that SP and the number of clocks are NCK, NCK = (NFF + 1 + 1) × NSP In this embodiment, NCK = (NFF + 1 + 1 + 1) × NSP / 2 Becomes That is, usually, the number NFF of flip-flops is
Because it is quite large, test with about half the number of clock pulses.
Will be completed. The above embodiment is an example, and the present invention
Invert the test data sent to the serial and test again.
Response data before and after inversion.
It is enough to have a configuration to send out serially. [0018] As described above, serial data is sent.
The test data is inverted and used as test data again.
And the response data of the circuit under test before and after inversion.
Data is output after compression.
Time is halved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram showing a portion related to one flip-flop of a test facilitation circuit according to an embodiment of the present invention. FIG. 2 is a timing chart of the circuit shown in FIG. FIG. 3 is a circuit block diagram showing a portion related to one flip-flop of the boundary scan circuit. FIG. 4 is a timing chart of the circuit shown in FIG. 3; [Description of Reference Codes] 10, 12, 21 Multiplexer 11 Latch circuit 13 Flip-flop 20 Inverter 22 AND gate 23 Exclusive OR gate

Claims (1)

(57) [Claim 1] Serially supplied test data is supplied to a circuit under test in parallel, and response data of the circuit under test resulting from the supply of the test data is taken in parallel. In the test facilitation circuit equipped with a shift register that sends in and sends out serially, the data inversion circuit generates new test data by inverting the test data sent in serially, and the test data supply before inversion A data compression circuit that generates new response data by compressing the response data of the circuit under test and the response data of the circuit under test resulting from the supply of the inverted test data. Test facilitation circuit.