JP3457503B2 - Insulated gate type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type insulated gate semiconductor device in which a device and an electrode are pressure-connected.

[0002]

2. Description of the Related Art IGBT (Insulated Gate Bipolar Tra
nsistor) and IEGT (Injection Enhanced Gate Tran)
Insulated gate type semiconductor devices (hereinafter referred to as "devices") represented by sistors are generally devices that are mounted on an insulating substrate, and the emitter part of the device and the copper plate that is the terminal part are connected by a lead wire. There are a type and a pressure welding type in which the emitter portion of the element and the copper plate which is the terminal portion are pressure-connected.

Recently, with the progress of higher voltage devices, the IG has a high withstand voltage of 1.7 kV or 2.5 kV.
BT has also been commercialized. Furthermore, withstand voltage is 3.3k
New devices with high withstand voltage, such as V IGBT and 4.5 kV IEGT, have also been developed.

However, when it is attempted to cut off the current of these high withstand voltage elements, the element may be destroyed because the dv / dt at the time of the current interruption is extremely high. Also,
Due to the higher withstand voltage of the elements, the current increase rate di / dt = E / L (L is the wiring inductance of the circuit, etc.) also increases with the increase in the voltage E, and when the elements are connected in parallel, Another problem phenomenon in which the current is concentrated on the element of the part and the element is destroyed has become remarkable.

This defect phenomenon hardly appears in the bonding type element, but appears in the pressure contact type element.
The reason is as follows.

As a structure for solving the above-mentioned trouble phenomenon,
As shown in FIG. 8, a small amount of inductance Ind is connected to the emitter portion E of the element, and the inductance In
The gate emitter terminal Eg is formed from the position including d, and the inductance I is generated by the cutoff current at turn-off.
A configuration in which the voltage generated at nd is used to alleviate the gate voltage and dv / dt applied to the element is alleviated to prevent the element from being destroyed can be considered.

When the current is cut off when the inductance Ind is inserted in this way, the voltage L has the polarity shown in FIG.
The gate voltage Vge actually generated by (di / dt) and applied to the device is not (Eoff) but (Eoff-L.
(Di / dt)) to alleviate the turn-off voltage and the cut-off phenomenon does not occur suddenly.
The v / dt also becomes gentle, and the effect of preventing the element 1 from being destroyed can be obtained. When cutting off a large current, di / d
Since t is further increased, the OFF gate voltage is automatically reduced, and dv / dt is further relaxed, so that the element is prevented from being destroyed.

As shown in FIG. 9, in the bonding type element, a chip 2, a collector terminal electrode copper plate 3 and an emitter terminal electrode copper plate 4 are mounted on an insulating substrate 1, and the chip 2 has a gate portion G, Collector-emitter CE
It consists of Then, the collector-emitter portion C
It is configured by bonding the emitter portion of E and the emitter terminal electrode copper plate 4 with a lead wire 5. The bonding-type element thus configured is controlled in gate drive by supplying power to the gate portion G from the gate power supply circuit 6 including the DC power supplies E1 and E2, the switches S1 and S2, and the resistor R. ing. Therefore, in the case of a bonding type element, since the emitter portion of the collector-emitter portion CE and the emitter terminal electrode copper plate 4 are bonded by the lead wire 5, this lead wire 5
Is an inductance element.

[0009]

However, in the above-mentioned bonding type insulated gate type semiconductor element, the inductance due to the lead wire can sufficiently suppress dv / dt at the time of current interruption, but a pressure contact type insulated gate is used. In the case of a type semiconductor element, since the emitter portion of the element and the emitter terminal electrode are connected by a pressure contact structure, they are not connected by a lead wire unlike a bonding type insulated gate type semiconductor element. 5
Since it cannot be used as an inductance element itself, the structure has almost no inductance element. Therefore, the pressure contact type insulated gate semiconductor element is more severe in dv / dt described above than the bonding type insulated gate semiconductor element, and the element is more likely to be destroyed due to the high dv / dt. Further, in the pressure contact type insulated gate semiconductor element, in order to form an inductance element, it is conceivable to thicken the electrode that pressure contacts the element, but in this case, since the outer shape of the element becomes large,
The scale merit as a pressure contact type insulated gate semiconductor device cannot be exhibited.

Therefore, in order to solve the above problems, the present invention relaxes dv / dt and current imbalance at the time of turn-off in parallel connection while making the most of the merit of scale as a pressure contact type insulated gate semiconductor device. Provided is a pressure contact type insulated gate semiconductor element having an inductance element capable of suppressing the above.

[0011]

In order to achieve the above object, the invention according to claim 1 is an insulated gate semiconductor device in which an element and an electrode are pressure-connected to each other, and at least one end of the element and the electrode. A cylindrical and spirally formed inductance element is provided between and.

The invention according to claim 2 is an insulated gate semiconductor device in which a device and an electrode are pressure-connected,
It is characterized in that a rectangular tube-shaped and spirally formed inductance element is provided at least between one end of the element and the electrode.

Further, the invention according to claim 3 is an insulated gate semiconductor device in which a device and an electrode are pressure-connected,
A coil-shaped inductance element is provided at least between one end of the element and the electrode.

Further, according to the invention of claim 4, in an insulated gate semiconductor element in which an element and an electrode are pressure-connected, a heat buffer plate is provided at both ends of the element, and the heat buffer plate is interposed therebetween. The element and the electrode, and the element and the inductance element are connected to each other.

The invention according to claim 5 is characterized in that the turns of the inductance element are insulated, and the invention according to claim 6 is such that the insulation treatment inserts an electrical insulator between the turns of the inductance element. It is characterized by being done by doing.

Further, the invention according to claim 7 is characterized in that the insulating treatment is carried out by insulating coating between the turns of the inductance element. Further, the invention according to claim 8 is characterized in that a plurality of inductance elements are connected in parallel. The invention according to claim 9 is
It is characterized in that the electrode and the plurality of inductance elements are integrally formed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. As the present embodiment, a flat type I
The EGT will be described with reference to FIGS. 1 to 3. Figure 1
Is a cross-sectional view of a flat type IEGT package.
The upper and lower sides are joined by an alloy plate 11 serving as a lid, and the copper posts 12, 13 which are plastically deformable conductors serving as the collector electrode and the emitter electrode are joined. The copper post 12,13
In order to suppress thermal distortion of the element due to energization, a heat buffer plate 14 made of molybdenum is placed at both ends of the chip 2 composed of a gate portion and a collector-emitter portion, and X- of FIG. A plurality of rectangular tube-shaped chips shown in FIG. 2 of the arrow X are inserted to form a flat IEGT. Then, the copper post 13 and the thermal buffer plate 14 which will be the emitter electrode
A coil 1 made of copper as an inductance element between
Insert 5a. A gate pin 16 is formed at the end of the predetermined chip 2.

Then, as shown in FIG. 3, the coil 15a
Is a configuration in which a copper rod is machined into a cylindrical shape, a groove is spirally cut in the cylinder, and an insulating sheet 17 such as Nomex is inserted into the spiral groove as insulation between the coils.

As described above, by using the cylindrical coil 15a as the inductance element, the voltage E across the coil 15a generated at the time of interruption is 50 V or less, so that the voltage applied to the insulating sheet 17 is the voltage E above the coil 15a. It is a value divided by the number of turns of, which is a value with no problem in terms of dielectric strength.

The value of the coil 15a is kept below 50 nH. The reason for this is that the limit withstand voltage of the gate of the device is about 50 V, and if a voltage higher than this is applied, dielectric breakdown may occur. Therefore, the cut-off current di / dt in a high voltage device is generally 1 kA / μS.
Since it is about ec, L = E / (di / dt) = 5
It becomes 0 V / 1 kA = 50 nH. For example, the outer shape of the coil 15a at 25 nH with a safety factor of 2 is 10 mm in diameter,
It is formed with 5 turns and a length of about 6 mm.

Therefore, according to the present embodiment, since the material of the coil 15a is copper, the copper post 1 which is an electrode is used.
By pressurizing the coils 2 and 13, the coil 15a undergoes plastic deformation, so that a dimensional error can be absorbed and a uniform pressure contact force of each element can be secured. In terms of characteristics, as in the case of the bonding type device, the voltage L · di / dt is generated when the current is cut off, and the gate voltage Vge actually applied to the device is not Eoff,
Since the turn-off voltage is reduced by reducing to Eoff-L · di / dt, the cutoff phenomenon does not occur rapidly, so that dv / dt at the time of turn-off also becomes gentle and element breakdown can be prevented. Further, when a large current is cut off, the gate voltage for turning off automatically decreases as di / dt further increases. Therefore, dv / dt is further relaxed to further prevent device breakdown. be able to.

Further, according to the present embodiment, as with the bonding type element, with the increase in withstand voltage of the element,
When the voltage E becomes high, conversely, the rate of increase of the current di
/ Dt = E / L (L is the wiring inductance of the circuit)
Therefore, when the elements are connected in parallel, it is possible to suppress the destruction of the elements due to the current concentration on some elements.
A modified example of the inductance element shown in the above embodiment will be described with reference to FIGS. 4 to 7.

The inductance element shown in FIG. 4 is a coil 15b in the shape of a rectangular tube, as opposed to the cylindrical coil 15a shown in FIG. Compared with the cylindrical coil shown in FIG. 3, the energization cross section can be increased and the current capacity can be increased.

Also in the case of the rectangular tube-shaped coil 15b, it is necessary to limit the voltage to the gate-emitter voltage withstand voltage or less, as in the cylindrical coil shown in FIG.
The voltage E across the coil 15b generated at the time of interruption is 50 V or less. Therefore, the voltage applied to the insulating sheet 16 is a value obtained by dividing the voltage E by the number of turns of the coil 15b, which is a value that does not cause any problem in terms of the dielectric strength.

FIG. 5 is a central sectional view of the cylindrical coil 15a shown in FIG. 3 and the rectangular tube-shaped coil 15b shown in FIG. As shown in this figure, the gate electrode Eg in the cylindrical coil 15a shown in FIG. 3 and the rectangular tube-shaped coil 15b shown in FIG. 4 has an electric wire in the cutout portion 20 provided in the lower portion of the coil 15b. The gate pin 21 having a spring property is connected to and formed.

Further, FIG. 6 shows the cylindrical coil 15a.
Is coated with an insulating coating 30 such as epoxy. In this case, the cylindrical coil 15a is targeted, but the same effect can be obtained by applying the insulating coating 30 such as epoxy to the rectangular tubular coil 15b shown in FIG.

FIG. 7 is a central cross section of FIG. 6, in which the insulating coating 30 has a spiral grooved coil 15a.
Is heated in advance by the fluidized-bed method and the electrostatic coating method to coat and insulate the spiral groove. Electrodes are formed by removing the insulating coating 30 attached to both ends of the coil 15a by machining.

This insulating coating 30, like the insulating sheet 16 described above, has no problem in terms of electrical insulation and withstand capacity. Although not shown, when a plurality of the coils 15a shown in FIG. 1 or the coils 15a shown in FIG. 4 are arranged in parallel to increase the current, the copper posts 12 and 13 to be the emitter electrodes are formed.
And a plurality of cylindrical coils 15a or rectangular tubular coils 15b are arranged. As a method of arranging the plurality of coils, the individual coils 15a or 15b are joined to the copper posts 13 of the emitter electrode by silver brazing, or the individual coils 15a or 15b and the copper posts 13 of the emitter electrode are integrated. Press molding or casting.
After that, a spiral groove is processed to form the insulating sheet 16
And the insulating coating 30.

[0029]

As described above, according to the present invention, the inductance element capable of uniformly pressure-contacting each element is provided. Therefore, dv / It is possible to provide a pressure contact type insulated gate semiconductor element capable of relaxing dt and suppressing current imbalance at turn-off in parallel connection.

[Brief description of drawings]

FIG. 1 is a sectional view of a flat IEGT package according to an embodiment of the present invention.

FIG. 2 is a view taken in the direction of arrow X1X in FIG.

FIG. 3 is a perspective view of the cylindrical coil 15a shown in FIG.

FIG. 4 is a perspective view of a rectangular tubular coil as the inductance element shown in FIG. 1.

5 is a central cross-sectional view of the coil shown in FIGS. 3 and 4. FIG.

6 is a perspective view of an insulating coating applied to the cylindrical coil 15a shown in FIG.

7 is a central cross-sectional view of the cylindrical coil 15a shown in FIG.

FIG. 8 is a schematic configuration diagram of a bonding type insulated gate semiconductor element.

FIG. 9 is a circuit diagram of a bonding type insulated gate semiconductor device.

[Explanation of symbols]

2 ... Chip, 12, 13 ... Electrode, 14 ... Thermal buffer plate, 15a, 15b ... Coil (inductance element), 17 ... Insulation sheet, 30 ... Insulation coating

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 25/07 H01L 25/18 H01L 29/78 H01L 21/52

Claims (9)

(57) [Claims] 1. An insulated gate semiconductor device in which an element and an electrode are pressure-connected to each other, wherein a cylindrical and spirally formed inductance element is provided between at least one end of the element and the electrode. A characteristic insulated gate semiconductor device. 2. An insulated gate semiconductor element in which an element and an electrode are pressure-connected to each other, wherein a rectangular tube-shaped and spirally formed inductance element is provided between at least one end of the element and the electrode. An insulated gate type semiconductor device characterized by: 3. An insulated gate semiconductor device in which an element and an electrode are pressure-connected to each other, wherein an inductance element formed in a coil shape is provided at least between one end of the element and the electrode. Gate type semiconductor device. 4. In an insulated gate semiconductor device in which an element and an electrode are pressure-connected, thermal buffer plates are provided at both ends of the element, and the element and the electrode and the element and the inductance are interposed via the thermal buffer plates. The insulated gate semiconductor device according to any one of claims 1 to 3, wherein the elements are connected to each other. 5. The insulated gate semiconductor device according to claim 1, wherein the turns of the inductance element are insulated. 6. The insulated gate semiconductor device according to claim 5, wherein the insulating process is performed by inserting an electrical insulator between turns of the inductance element. 7. The insulated gate semiconductor device according to claim 5, wherein the insulating treatment is performed by insulating coating between turns of the inductance element. 8. The insulated gate semiconductor device according to claim 1, wherein a plurality of the inductance elements are connected in parallel. 9. The insulated gate semiconductor device according to claim 8, wherein the electrode and a plurality of the inductance elements are integrally formed.