JP3455405B2 - Memory address generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface device for writing a digital signal to a memory and reading a digital signal from the memory, and more particularly to a memory address generating device in a memory interface device for generating an address of a memory. It is a thing.

[0002]

2. Description of the Related Art In recent years, signal digitization and digital processing have become widespread in the audio signal processing and video signal processing fields. In addition, with the introduction of multimedia,
The signal sources are diversified, and higher-level processing is required for digital signals. Among such high-level processing, processing using memory is emphasized.

In particular, regarding video signals, it is required to process digital video signals of different formats such as NTSC, PAL, HDTV, VGA, SVGA in one television system. In order to handle video signals of such multiple formats, a digital signal processing system capable of processing the video signals in real time at the rate of the video signals using a memory is indispensable. The address control method is becoming more and more complicated.

The conventional memory control device has been realized by designing dedicated hardware for calculating the memory address for each of a plurality of address pointers.

[0005]

However, in the television system which handles various video signals as described above, a plurality of dedicated hardware are used to perform memory address control corresponding to video signals of a plurality of formats. Since it was prepared, the circuit scale tended to be large.

Further, in the frame synchronization processing for converting a video signal of a certain synchronization system into a video signal of a different synchronization system, a dedicated memory has to be used for the frame synchronization.

Therefore, the present invention has been made in view of the above-mentioned problems, and it is possible to generate a plurality of types of addresses in a memory with a simple structure. Further, by using only one memory, The present invention provides a memory address generator capable of processing a plurality of asynchronous video signals.

[0008]

In order to solve the above-mentioned problems, the present invention is a memory address generating device for generating a plurality of addresses for accessing a memory, wherein N (N) A natural number) is updated based on a predetermined relative relationship of each address, and the updated address is incremented.

With the above structure, it is not necessary to prepare the arithmetic means for the number of addresses, and a plurality of addresses can be updated by only one arithmetic means, so that the memory address generator can be realized in a small circuit scale. Become. Further, by updating a plurality of addresses based on a predetermined relative relationship, it is possible to allocate each address in the memory space while always maintaining the relative relationship of each address.

In one embodiment, the predetermined relative relationship between the respective addresses is represented by K (K is a natural number) predetermined values, and the address updating means sets the respective addresses by the K
It is updated by a predetermined value of K (a natural number).

In one embodiment, the K number (K is a natural number)
The predetermined value of is an offset value, and the address updating means uses a predetermined add address determined from the address.
After the reference address the less selectively Update by calculation based on the offset value by calculation based on the calculation result and the offset value of the reference address, the group
Update addresses other than quasi-addresses .

With the above configuration, the control of a plurality of addresses is calculated by the relative value with respect to the reference address, so that even if the calculation is erroneous at the time of updating the address, each address can be led to the correct relative relationship again at the time of the next address updating. Becomes

[0013] In one embodiment, the address update unit, and one of the update directions of the respective address to which the reference address, the the update direction in another of the each address Conversely, the The update direction is the addition / subtraction identification signal
Then, the information of the address updating means is input .

With the above configuration, by reversing the updating direction of the reference address and the updating direction of other addresses, it is not necessary to store the code information of the arithmetic unit in the register, and the number of bits of the register can be reduced. Furthermore, the number of bits of the arithmetic unit can be reduced.

In one embodiment, the first at a different frequency
A synchronization signal and a second synchronization signal, wherein the address updating means selectively uses the first and second synchronization signals,
The respective addresses are selectively updated.

With the above-mentioned structure, a necessary offset address is updated for each H blanking start signal, so that an offset in the horizontal direction can be given to the address. For example, a small screen is formed on a memory. It becomes possible to do.

In one embodiment, the address updating means logically divides the address space of one memory into a plurality of areas, and increments the address pointers in respective different ways for each area. To generate an address.

With the above configuration, when writing and reading each video signal having a different number of bits and a required number of fields, a plurality of storage areas are formed in one memory space, and each storage area is Since each advances the pointer at different speeds, the memory space can be effectively used.

In one embodiment, the address updating means includes a first address space of one memory including a first address.
Divide the area and the second area including the final address by a single boundary value, perform the address operation with the logical address based on address 0 for both areas, and invert the operation result for the second area Outputs the real address.

With the above configuration, when the memory space is divided into two storage areas at a single boundary, both storage areas can be handled in the same way by introducing a logical address, so that the circuit scale can be reduced. It will be possible.

In one embodiment, M types (M is a natural number) of synchronization signals and K types (K is a natural number) of asynchronous signals that are asynchronous with the synchronization signals are provided, and the address updating means is 1 A dedicated area for writing and reading asynchronous signals is provided in the address space of one memory.
Set the read address of the asynchronous signal to the specified timing.
Write address held for each group and write
Is calculated based on the identification signal corresponding to the frequency difference between read and .

With the above configuration, even when a plurality of asynchronous video signals are written and read out, an address is generated by one memory address generator, and an asynchronous signal is synchronized with a synchronous signal in one memory without any contradiction. It becomes possible to read.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the memory address generator of the present invention. In the first embodiment, it is premised that an address of a memory for writing and reading a digital video signal is generated, and a plurality of types of addresses are calculated for each field based on their respective offset values. I am updating.

In FIG. 1, reference numeral 500 denotes an input terminal for inputting a register update start signal (V blanking start signal), 501
Is an input terminal for inputting the address generation timing signal, 50
2 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 504 is a selector for selecting and outputting each value A, B, C, D in the address update register 503 and a fixed value "1", 50
5 is an arithmetic unit, 506 is a limiter for limiting the address of the arithmetic result of the arithmetic unit 505 within the memory space, 507 is an address updating circuit, and 508 is an address register for storing each memory address corresponding to each address pointer. , 509 is a selector for selecting each memory address in the address register 508, 510 is an output terminal for outputting the memory address, 519
Is a latch that holds the output of the selector 509, and 515 is a calculator 50
5, a control signal generation circuit for controlling each selector 504, 509, address register 508 and latch 519, and 511 a selector 504
Update register selection signal that controls the address register, 512 is an address register load signal that controls the address register 508, 513 is an address register selection signal that controls the selector 509, and 520
Is an address load signal indicating the timing of loading an address to the selector 519, and 514 is an addition / subtraction identification signal for instructing the type of operation of the arithmetic unit 505.

In the present embodiment, the luminance signal Y and the color difference signal C are mentioned as digital video signals which are written to and read from the memory (not shown), and the luminance signal Y and the color difference signal C are listed. Is written in and read from the memory to delay one field. The write address pointers of the luminance signal Y and the color difference signal C in the memory are represented by W0 and W1 and the read address pointers R0 and R1.

The address update register 503 has offset values A, B, and B corresponding to the address pointers W0, R0, W1, and R1, respectively.
Stores C and D.

Access to the image area in the memory where the luminance signal Y and the color difference signal C are stored is performed by incrementing the address. The operation will be described below.

Upon receiving the pointer identification signal from the input terminal 502, the control signal generation circuit 515 outputs the address register selection signal 513 corresponding to the pointer identification signal to the selector 5
Output to 09. The address register 508 stores each address corresponding to each address pointer W0, R0, W1, R1. The selector 509 has an address register selection signal 513.
One of the address pointers W0, R0, W1, and R1 indicated by is selected, and the address corresponding to the selected address pointer is fetched from the address register 508.

Further, the control signal generating circuit 515 has the input terminal 5
When the address generation timing signal from 01 is input, the address load signal 520 corresponding to this address generation timing signal is generated and output to the latch 519. In response to the address load signal 520, the latch 519 is connected to the selector 50.
Holds the address from 9. The address in the latch 519 is output as the address of the memory corresponding to any of the address pointers W0, R0, W1 and R1, and the memory is accessed based on this address.

Further, the address output from the selector 509 is also added to the arithmetic unit 505. At this time, the control signal generation circuit 515 causes the update register selection signal 51 indicating the fixed value "1".
1 is given to the selector 504, and in response to this, the selector
The fixed value "1" is output from the 504 to the computing unit 505. The control signal generation circuit 515 outputs an addition / subtraction identification signal 514 indicating addition to the calculator 505. In response to the addition / subtraction identification signal 514, the computing unit 505 adds a fixed value “1” to the address from the selector 509, updates this address, and stores the updated address in the address register 508 via the limiter 506. return. The address register 508 rewrites the address with the updated address in response to the address register load signal 512 from the control signal generation circuit 515. For example, when the memory is accessed according to the address pointer W0, the address corresponding to the address pointer W0 in the address register 508 is selected and output from the latch 519,
A fixed value "1" is added to this address, and the updated address is written in the address register 508 as one corresponding to the address pointer W0. Each other address pointer R0,
Similar operations are performed for W1 and R1. As a result, each address pointer W0, R0, W1, R1 is incremented.

FIGS. 2A, 2B and 2C show storage areas corresponding to a plurality of fields in the memory, in which a luminance signal Y and a color difference signal C are stored for each field. The luminance signal and color difference signal of one field are represented by Y2 and C2, and the luminance signal and color difference signal of the next field are represented by Y1 and C1.
, And the luminance and color difference signals of the next field
It is represented by Y0 and C0.

If the address pointers W0, R0, W1, and R1 are in the state shown in FIG. 2A at the start of reading and writing of the two fields, the address register 508 will be stored in the address register 508 of FIG.
Addresses corresponding to the address pointers W0, R0, W1, and R1 shown in are stored. By the above-described operation, for each of the address pointers W0, R0, W1, and R1, this address pointer is incremented each time the address pointer is selected. Address pointer W
0, R0, W1, and R1 are in the state shown in FIG. 2 (b).

At the start of reading and writing of the next two fields, it is necessary to update each address pointer W0, R0, W1, R1 to the state shown in FIG. 2 (b) to FIG. 2 (c). The operation for this update is performed by using the address update register 503 in the following procedure.

The address register 508 may be updated once for each field, but normally it must be updated when the memory is not being accessed. In this embodiment,
The register update start signal input from the input terminal 500 is a V blanking start signal, that is, a signal indicating the start of vertical blanking, and the address register 508 is updated in response to the start of vertical blanking. ing.

Upon receiving the V blanking start signal, the control signal generation circuit 515 outputs an update register selection signal 511 indicating the address pointer W0 to the selector 504, and an address register selection signal 513 indicating the address pointer W0 to the selector 509. And the addition / subtraction identification signal 514 indicating addition is output to the calculator 505. In response to the update register selection signal 511, the selector 504 selects the offset value A corresponding to the address pointer W0 from the address update register 503, and outputs this offset value A to the calculator 505. Also,
In response to the address register selection signal 513, the selector 509 selects the address corresponding to the address pointer W0 from the address register 508 and outputs this address to the arithmetic unit 505.
Output to.

The arithmetic unit 505 adds the value A corresponding to the address pointer W0 to the address corresponding to the address pointer W0, updates this address, and stores the updated address in the address register 508 via the limiter 506. return. The address register 508 rewrites the old address corresponding to the address pointer W0 with the updated address in response to the address register load signal 512 from the control signal generation circuit 515. As a result, the address pointer W0 becomes
The state is updated from (b) to the state shown in FIG. 2 (c).

At the time of updating the address pointer W1, an addition / subtraction identification signal 514 indicating addition is given to the arithmetic unit 505.
Then, the offset value C corresponding to the address pointer W1 is taken out from the address update register 503, the already updated address corresponding to the address pointer W0 is taken out from the address register 508, and the offset value C is obtained at this already updated address. The added value is added, and the added value is written in the address register 508 as an address corresponding to the address pointer W1.

When the address pointer R0 is updated, the addition / subtraction identification signal 514 indicating subtraction is given to the arithmetic circuit 505. Then, the offset value B corresponding to the address pointer R0 is retrieved from the address update register 503,
The already updated address corresponding to the address pointer W0 is fetched from the address register 508, the offset value B is subtracted from this already updated address, and this subtracted value is written to the address register 508 as the address corresponding to the address pointer R0. Be done. Address pointer R
The update of 1 is performed by subtracting the offset value D from the already updated address corresponding to the address pointer W0.

By the above operation, each address pointer
W0, R0, W1 and R1 shift from the state shown in FIG. 2 (b) to the state shown in FIG. 2 (c).

Whether to add or subtract the offset value depends on
It is determined for each offset value of the address update register 503. Therefore, if the control signal generation circuit 515 incorporates a register storing either addition or subtraction corresponding to each offset value of the address update register 503, the control signal generation circuit 515 can store one address pointer. When outputting the address register selection signal 513 indicating, the addition / subtraction identification indicating whether addition or subtraction is made by identifying whether to add or subtract the offset value corresponding to the address pointer by referring to a built-in register. A signal can be output.

Next, the address space of the memory and the limiter 50.
The operation of 6 will be described with reference to FIG.

Consider the case where the memory has a p-bit memory space. This memory space is in the range from the p-bit start address to the p-bit end address. If the p-bit address is output from the address register 508,
Since the arithmetic unit 505 adds / subtracts the offset value to / from the p-bit address, the p + 2-bit address (the p + 1-bit address indicates a memory space larger than the p-bit memory space, and the remaining 1-bit indicates the p + 1-bit address). Indicates the direction out of the p-bit memory space).

FIG. 3A shows p + output from the computing unit 505.
The operation of the limiter 506 when the 1-bit address exceeds the final address by "+ a" is shown. In this case, the limiter 506 obtains the "p + 1-bit address output from the calculator 505-final address-1" as an address and outputs this address. This address is within the address space, and the limiter 506 outputs a p-bit address.

FIG. 3B shows p + output from the computing unit 505.
It shows the operation when the 1-bit address is short of "-b" from the start address. In this case, the limiter 506
Calculates the address of "p + 1-bit address output from computing unit 505 + final address + 1" and outputs this address. This address is in the address space,
The limiter 506 outputs a p-bit address.

As described above, by updating each address pointer and each address with a relative value with respect to the reference address, these address pointers are allocated in the memory space while always maintaining the relative relationship of each address pointer. You can

In this embodiment, an example in which another address is relatively obtained with respect to one reference address has been shown, but the number of reference addresses is not limited to one and may be plural. Also, the number of each offset value in the address update register may be different from the number of each address in the address register. Further, although the arithmetic unit 505 is controlled by the addition / subtraction identification signal, for example, a value based on the two's complement may be stored in the address update register 503 and the arithmetic unit may have a simple adder configuration. Further, although the value by which the address is incremented is set to "1", other values may be used. Also, by combining the selectors 504 and 509 and the arithmetic unit 505, each address is updated by one arithmetic unit 505. However, each arithmetic unit is prepared for each address and each address is updated. I don't mind.

(Second Embodiment) FIG. 4 shows a second embodiment of the memory address generator of the present invention. In the second embodiment, the control signal generating circuit 515 to the limiter 506 are used.
The address output from the computing unit 505 to the limiter 506 is set to p + 1 bits by applying the addition / subtraction identification signal to the. That is, in the first embodiment, p + 2
Although the bits were output from the arithmetic unit 505, in the second embodiment, 1 bit indicating the direction in which the address is out of the p-bit memory space is reduced from the p + 2 bits to p + 1 bits.

In FIG. 4, reference numeral 500 denotes an input terminal for inputting a register update start signal (V blanking start signal), 501
Is an input terminal for inputting the address generation timing signal, 50
2 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 504 is a selector for selecting and outputting each value A, B, C, D in the address update register 503 and a fixed value "1", 50
5 is an arithmetic unit, 506 is a limiter for limiting the address of the arithmetic result of the arithmetic unit 505 within the memory space, 507 is an address updating circuit, and 508 is an address register for storing each memory address corresponding to each address pointer. , 509 is a selector for selecting each memory address in the address register 508, 510 is an output terminal for outputting the memory address, 519
Is a latch that holds the output of the selector 509, and 515 is a calculator 50
5, a control signal generation circuit for controlling each selector 504, 509, limiter 506, address register 508 and latch 519, 511
Is an update register selection signal that controls the selector 504, 512 is an address register load signal that controls the address register 508, 513 is an address register selection signal that controls the selector 509, and 520 is an address load that indicates the timing of loading the address to the selector 519. A signal 514 is an addition / subtraction identification signal for instructing the type of calculation of the calculator 505.

In the present embodiment, the luminance signal Y and the color difference signal C are mentioned as digital video signals which are written to and read from the memory (not shown), and these luminance signal Y and color difference signal C are given. Is written in and read from the memory to delay one field. The write address pointers of the luminance signal Y and the color difference signal C in the memory are represented by W0 and W1 and the read address pointers R0 and R1.

The address update register 503 has offset values A, B, and B corresponding to the address pointers W0, R0, W1, and R1, respectively.
Stores C and D.

The memory is accessed by the address register 50.
The operation is performed by incrementing the address for each address in 8, and the operation is exactly the same as that of the first embodiment, so the description thereof is omitted here.

FIGS. 5A, 5B and 5C show storage areas corresponding to a plurality of fields in the memory, in which the luminance signal Y and the color difference signal C are stored for each field. The luminance signal and color difference signal of one field are represented by Y2 and C2, and the luminance signal and color difference signal of the next field are represented by Y1 and C1.
, And the luminance and color difference signals of the next field
It is represented by Y0 and C0.

At the start of reading and writing of two fields, if the address pointers W0, R0, W1, and R1 are in the state shown in FIG. 5 (a), the address register 508 stores in the address register 508 shown in FIG. 5 (a).
Addresses corresponding to the address pointers W0, R0, W1, and R1 shown in are stored. By the above-described operation, for each of the address pointers W0, R0, W1, and R1, this address pointer is incremented each time the address pointer is selected. Address pointer W
0, R0, W1, and R1 are in the state shown in FIG. 5 (b).

At the start of reading and writing of the next two fields, it is necessary to update each address pointer W0, R0, W1, R1 to the state shown in FIG. 5 (b) to FIG. 5 (c). The operation for this update is performed by using the address update register 503 in the following procedure.

The address register 508 may be updated once for each field, but normally it must be updated when the memory is not being accessed. In this embodiment,
The register update start signal input from the input terminal 500 is a V blanking start signal, that is, a signal indicating the start of vertical blanking, and the address register 508 is updated in response to the start of vertical blanking. ing.

When the V blanking start signal is input, the control signal generation circuit 515 outputs, for example, an update register selection signal 511 indicating the address pointer W1 to the selector 504 and an address register selection signal 513 indicating the address pointer W1 by the selector 509. And the addition / subtraction identification signal 514 indicating addition is output to the calculator 505. In response to the update register selection signal 511, the selector 504 selects the offset value C corresponding to the address pointer W1 from the address update register 503, and outputs this offset value C to the calculator 505. Also,
In response to the address register selection signal 513, the selector 509 selects the address corresponding to the address pointer W1 from the address register 508 and outputs this address to the arithmetic unit 505.
Output to.

The arithmetic unit 505 adds the value C corresponding to the address pointer W1 to the address corresponding to the address pointer W1, updates this address, and stores the updated address in the address register 508 via the limiter 506. return. The address register 508 rewrites the address corresponding to the address pointer W1 with the updated address in response to the address register load signal 512 from the control signal generation circuit 515. As a result, the address pointer W1 is moved to the position shown in FIG.
Is updated to the state shown in FIG.

The other address pointers R0, W0, R1 are updated by using the already updated address corresponding to the address pointer W1 as a reference and subtracting the offset value from the reference address.

That is, when the address pointer W1 is updated, the addition / subtraction identification signal 514 indicating subtraction is given to the calculator 505. Then, the offset value A corresponding to the address pointer W0 is taken out from the address update register 503, the already updated address corresponding to the address pointer W1 is taken out from the address register 508, and the offset value A is obtained from this already updated address. Subtraction is performed, and the subtraction value is written in the address register 508 as an address corresponding to the address pointer W0. Similarly, the update of the address pointer R0 is performed by subtracting the offset value B from the already updated address corresponding to the address pointer W1, and the update of the address pointer R1 is
This is done by subtracting the offset value D from the already updated address corresponding to the address pointer W1.

As described above, in this embodiment, only the address pointer W1 is updated by adding the offset value C, and the other address pointers R0, W0, R1 are updated by the offset values B, A, D, respectively. It is done by subtracting.

By the above operation, each address pointer
W0, R0, W1 and R1 shift from the state shown in FIG. 5 (b) to the state shown in FIG. 5 (c).

Whether to add or subtract the offset value depends on
Determined only by the value of the update register select signal 511,
The value of the addition / subtraction identification signal 514 is determined according to the value of the update register selection signal 511.

Next, the address space of the memory and the limiter 50.
The operation of 6 will be described with reference to FIG.

Consider the case where the memory has a 4-bit memory space. This memory space is in the range from the 4-bit start address to the 4-bit end address. If the 4-bit address is output from the address register 508, the arithmetic unit 505 adds or subtracts the offset value to or from the 4-bit address, so that the 5-bit address (the 5-bit address is out of the 4-bit memory space). (There is no 1 bit indicating the direction).

FIG. 6A shows the operation of the limiter 506 when the 5-bit address output from the arithmetic unit 505 exceeds the final address by "+ a". Also, FIG. 6 (b) shows
The operation when the 5-bit address output from the computing unit 505 is "-b" short of the start address is shown.

Since the 5-bit address output from the arithmetic unit 505 does not have 1-bit indicating the direction in which the 5-bit address is out of the 4-bit memory space,
The state of FIG. 6 (a) and the state of FIG. 6 (b) cannot be distinguished based only on the 5-bit address.

Therefore, the limiter 506 inputs the addition / subtraction identification signal, and if the addition / subtraction identification signal indicates addition, the limiter 506 determines that the state of FIG. If it is shown, it is determined to be in the state of FIG.

When the limiter 506 receives the addition / subtraction identification signal indicating addition, the limiter 506 obtains "5-bit address output from arithmetic unit 505-final address-1" as an address as shown in FIG. Output this address. Further, when the limiter 506 receives the addition / subtraction identification signal indicating the subtraction, as shown in FIG. 6 (b), the limiter 506 obtains "5-bit address output from the calculator 505 + final address + 1" as an address, and this address Is output.

That is, when the 5-bit address exceeds the address space by the addition, the limit processing of FIG. 6A is performed, and when the 5-bit address exceeds the address space by the subtraction, the limit processing of FIG. 6B is performed. The processing is performed, and the number of bits output from the arithmetic unit 505 is reduced by 1 bit, and the same operation as that of the first embodiment is performed.

As described above, by updating each address pointer and each address with the relative value with respect to the reference address, these address pointers are allocated in the memory space while always maintaining the relative relationship of each address pointer. You can Also, set the update direction of the reference address and the update direction of other addresses in the opposite direction, and
Since the 5-bit address output from 1 does not need 1 bit indicating the direction out of the 4-bit memory space, it is not necessary to store this 1 bit in the control signal generator 515 or the address update register 503. The number of register bits can be reduced. Further, by inputting the addition / subtraction identification signal 514 to the limiter 506, the number of bits of the address output from the calculator 505 can be reduced.

In this embodiment, an example in which another address is relatively obtained with respect to one reference address has been shown, but the number of reference addresses is not limited to one and may be plural. Also, the number of each offset value in the address update register may be different from the number of each address in the address register. Further, although the arithmetic unit 505 is controlled by the addition / subtraction identification signal, for example, a value based on the two's complement may be stored in the address update register 503 and the arithmetic unit may have a simple adder configuration. Further, the updating direction of the reference address and the updating direction of other addresses are not limited to this embodiment. Further, although the value by which the address is incremented is set to "1", other values may be used. In addition, each selector 504,
Although each address is updated by combining the 509 and the arithmetic unit 505, each arithmetic unit may be prepared for each address and each address may be updated.

(Third Embodiment) FIG. 7 shows a third embodiment of the memory address generator of the present invention. In the third embodiment, more address pointers H, W0, R
0, W1, R1, W2, W3 are set, and these address pointers are updated not only by the first register update start signal (V blanking start signal) but also by the second register update start signal (H blanking start signal). Signal), that is, a signal indicating the start of horizontal / vertical blanking.

In FIG. 7, reference numeral 500 is an input terminal for inputting a first register update start signal (V blanking start signal), 516 is an input terminal for inputting a second register update start signal (H blanking start signal), 501 Is an input terminal for inputting an address generation timing signal, 502 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 5
04 is a selector that selects and outputs each value G, A, B, C, D, E, F in the address update register 503 and a fixed value "1", 505 is a computing unit,
506 is a limiter for limiting the address of the operation result of the operation unit 505 in the memory space, 507 is an address update circuit, 508
Is an address register that stores each memory address corresponding to each address pointer, and 509 is an address register 5
A selector for selecting each memory address in 08, 510 is an output terminal for outputting the memory address, 519 is a latch for holding the output of the selector 509, 515 is a calculator 505, each selector 50
4, 509, a control signal generation circuit that controls the address register 508 and the latch 519, 511 is an update register selection signal that controls the selector 504, 512 is an address register load signal that controls the address register 508, and 513 is an address register that controls the selector 509. A selection signal, 520 is an address load signal indicating the timing of loading an address to the selector 519, and 514 is an addition / subtraction identification signal for instructing the type of operation of the arithmetic unit 505.

In this embodiment, the luminance signal of the main screen is first displayed.
Write Y and color-difference signal C to the memory and set the luminance signal of the sub-screen.
It is premised that SY and the color difference signal SC are overwritten in a partial area of the main screen delayed by 1 field and the main screen with 2 field delay and the slave screen with 1 field delay are read out together. The write address pointers for the luminance signal Y and the color difference signal C in the memory are represented by W0 and W2, and the read address pointers are represented by R0 and R1. Similarly, set the write address pointers for the luminance signal SY and color difference signal SC.
It is represented by W1 and W3, and each read address pointer is represented by R1 and R3.

The address update register 503 stores offset values A, B, C, D, E, F corresponding to the address pointers W0, R0, W1, R1, W2, W3. Also, an offset value G used together with the write address pointers W1 and W3 is stored.

The address register 508 stores each address corresponding to each address pointer W0, R0, W1, R1, W2, W3.

The memory is accessed by the address register 50.
The operation is performed by incrementing the address for each address within 8, and the operation is exactly the same as in the first and second embodiments, so the description thereof is omitted here.

FIGS. 8A, 8B and 8C show storage areas corresponding to a plurality of fields in the memory, and the luminance signal Y and the color difference signal C are stored for each field. The luminance signal and color difference signal of a certain field are represented by Y3 and C3, and the luminance signal and color difference signal of the next field are represented by Y2 and C2
, And the luminance and color difference signals of the next field
It is represented by Y1 and C1, and the luminance signal and color difference signal of the next field are represented by Y0 and C0.

Further, in each field, a part of the luminance signal Y of the main screen is replaced with the luminance signal SY of the small screen, and a part of the color difference signal C of the main screen is replaced with the color difference signal SC of the small screen. The images of the main screen and the sub-screen on the display screen are based on the positional relationship between the storage area of the luminance signal Y and the storage area of the luminance signal SY, or the positional relationship of the storage area of the color difference signal C and the storage area of the color difference signal SC. expressed.

At the start of reading and writing of two fields, if the address pointers W0, R0, W1, R1, W2 and W3 are in the state shown in FIG.
Addresses corresponding to the address pointers W0, R0, W1, R1, W2, W3 shown in FIG. 8A are stored. By the above-mentioned operation, each of the address pointers W0, R0, W1, R1, W2, W3 is incremented every time the address pointer is selected.

At the end of one horizontal scanning, the address pointers W0, W1, W2, W3 for writing are shown in FIG. 8 (a).
Move to each black circle position. For each of the address pointers W0 and W2 related to the main screen, the increment may be continued as in the first and second embodiments. On the other hand, with respect to the respective address pointers W1 and W3 relating to the child screen, the following processing is required in order to access only the storage area of the luminance signal SY and the storage area of the color difference signal SC.

That is, when the control signal generation circuit 515 receives the H blanking start signal 516, it outputs the update register selection signal 511 indicating the address pointer W1 to the selector 504.
The address register selection signal 513 indicating the address pointer W1 is output to the selector 509, and the addition / subtraction identification signal 514 indicating addition is output to the calculator 505. The selector 504 is
In response to the update register selection signal 511, the offset value G is selected from the address update register 503, and this offset value G is output to the calculator 505. Also, the selector 509 is
In response to the address register selection signal 513, the address corresponding to the address pointer W1 is selected from the address register 508, and this address is output to the arithmetic unit 505.

The computing unit 505 adds the offset value G to the address corresponding to the address pointer W1, updates this address, and returns the updated address to the address register 508 via the limiter 506. The address register 508 is
In response to the address register load signal 512 from the control signal generation circuit 515, the address corresponding to the address pointer W1 is rewritten to the updated address. As a result, the address pointer W1 points to the start address of the storage area of the luminance signal SY.

After that, when the address corresponding to the address pointer W1 in the address register 508 is incremented and the next H blanking start signal 516 is input, the same operation is repeated again.

Similarly, for the address pointer W3, H
When the blanking start signal 516 is input, the offset value G
Is added to the address corresponding to the address pointer W3,
When this address is updated, the updated address is returned to the address register 508, the address corresponding to the address pointer W3 in the address register 508 is incremented, and the next H blanking start signal 516 is input, the same operation is performed again. repeat.

At the end of reading and writing of each field, each address corresponding to each address pointer W0, R0, W1, R1, W2, W3 becomes the state shown in FIG. 8 (b).

At the start of reading and writing of the next two fields, each address pointer W0, R0, W1, R1, W2, W
It is necessary to update 3 to the state shown in FIG. 8 (b) to FIG. 8 (c). The operation for this update is the address update register 50.
Using 3, the procedure is as follows.

When the V blanking start signal is input, the control signal generation circuit 515 outputs, for example, an update register selection signal 511 indicating the address pointer W0 to the selector 504 and an address register selection signal 513 indicating the address pointer W0 to the selector 509. And the addition / subtraction identification signal 514 indicating addition is output to the calculator 505. In response to the update register selection signal 511, the selector 504 selects the offset value A corresponding to the address pointer W0 from the address update register 503, and outputs this offset value A to the calculator 505. Also,
In response to the address register selection signal 513, the selector 509 selects the address corresponding to the address pointer W0 from the address register 508 and outputs this address to the arithmetic unit 505.
Output to.

The calculator 505 adds the offset value A corresponding to the address pointer W0 to the address corresponding to the address pointer W0, updates this address, and updates the updated address via the limiter 506 to the address register 508.
Return to. The address register 508 is a control signal generation circuit 515.
In response to the address register load signal 512 from, the address corresponding to the address pointer W0 is rewritten to the updated address. This causes the address pointer W0
Is updated from the state shown in FIG. 8B to the state shown in FIG. 8C.

When updating the address pointer W2, an addition / subtraction identification signal 514 indicating addition is given to the arithmetic circuit 505. Then, the offset value E corresponding to the address pointer W2 is taken out from the address update register 503, the already updated address corresponding to the address pointer W0 is taken out from the address register 508, and the offset value E is obtained at this already updated address. The added value is added, and the added value is written in the address register 508 as an address corresponding to the address pointer W2.

When the address pointer R0 is updated, the addition / subtraction identification signal 514 indicating subtraction is given to the calculator 505. Then, the offset value B is subtracted from the already updated address corresponding to the address pointer W0, and this subtracted value is written in the address register 508 as the address corresponding to the address pointer R0. Address pointer R
The update of 1 is performed by subtracting the offset value D from the already updated address corresponding to the address pointer W0.

Similarly, when the address pointers W1 and W3 are updated, the addition / subtraction identification signal 514 indicating subtraction is output to the arithmetic circuit 505.
Given to. Then, the respective offset values C and F are subtracted from the already updated address corresponding to the address pointer W0, and these subtracted values are added to the address register 508.
Written in.

By the above operation, each address pointer
W0, R0, W1, R1, W2 and W3 are moved from the state shown in FIG. 8 (b) to the state shown in FIG. 8 (c).

Whether to add or subtract the offset value depends on
It is determined for each offset value of the address update register 503. Therefore, if the control signal generation circuit 515 incorporates a register storing either addition or subtraction corresponding to each offset value of the address update register 503, the control signal generation circuit 515 can store one address pointer. When outputting the address register selection signal 513 indicating, the addition / subtraction identification indicating whether addition or subtraction is made by identifying whether to add or subtract the offset value corresponding to the address pointer by referring to a built-in register. A signal can be output.

In the present embodiment, the operation of the limiter 506 is exactly the same as that of the first and second embodiments, so the description of this operation will be omitted.

As described above, by updating each address pointer and each address with a relative value with respect to the reference address, these address pointers are allocated in the memory space while always maintaining the relative relationship of each address pointer. You can For the necessary ones of each address pointer, the H blanking start signal 5
Every time 16 is input, it is updated and the offset value G in the horizontal direction is given to the address pointer.

In the present embodiment, the address pointer is updated by adding or subtracting the offset value to or from the address pointer for each address pointer, as in the first embodiment. As in the embodiment, the reference address pointer is set to W2 and this pointer is
It is also possible to add the offset value only for W2 and subtract the respective offset values for the other address pointers. Also, a plurality of address update registers 503 may be used. Also, an example in which another address is relatively obtained with respect to one reference address has been shown, but the number of reference addresses is not limited to one, and may be a plurality. Also, the number of each offset value in the address update register may be different from the number of each address in the address register. Further, although the arithmetic unit 505 is controlled by the addition / subtraction identification signal, for example, a value based on the two's complement may be stored in the address update register 503 and the arithmetic unit may have a simple adder configuration.
Further, the updating direction of the reference address and the updating direction of other addresses are not limited to this embodiment. Further, although the value by which the address is incremented is set to "1", other values may be used. Also, by combining the selectors 504 and 509 and the arithmetic unit 505, each address is updated by one arithmetic unit 505. However, each arithmetic unit is prepared for each address and each address is updated. I don't mind.

(Fourth Embodiment) FIG. 9 shows a fourth embodiment of the memory address generator of the present invention. In the fourth embodiment, the address space of the memory is logically divided into two, and each divided storage area is accessed only by each address pointer W0, R0, W1, R1. The memory area identification signal 517 is transmitted from the signal generation circuit 515 to the limiter 506.

In FIG. 9, reference numeral 500 denotes an input terminal for inputting a register update start signal (V blanking start signal), 501
Is an input terminal for inputting the address generation timing signal, 50
2 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 504 is a selector for selecting and outputting each value A, B, C, D in the address update register 503 and a fixed value "1", 50
5 is an arithmetic unit, 506 is a limiter for limiting the address of the arithmetic result of the arithmetic unit 505 within the memory space, 507 is an address updating circuit, and 508 is an address register for storing each memory address corresponding to each address pointer. , 509 is a selector for selecting each memory address in the address register 508, 510 is an output terminal for outputting the memory address, 519
Is a latch that holds the output of the selector 509, and 515 is a calculator 50
5, a control signal generation circuit for controlling each selector 504, 509, limiter 506, address register 508 and latch 519, 511
Is an update register selection signal for controlling the selector 504, 512 is an address register load signal for controlling the address register 508, 513 is an address register selection signal for controlling the selector 509, and 514 is for indicating the type of operation of the arithmetic unit 505. 520 is an add / subtract identification signal, 520 is an address load signal indicating the timing of loading an address to the selector 519, and 517 is a memory area identification signal.

In this embodiment, the operations other than the memory area identification signal 517 and the limiter 506, that is, the generation and updating of the address pointers W0, R0, W1, and R1 are the same as those in the first embodiment. The description is omitted.

FIG. 10 shows a memory space divided into two storage areas. A storage area for three fields for writing and reading the luminance signal Y and a storage area for two fields for writing and reading the motion signal M are shown. The storage area of is divided by the boundary value B.

Next, the operation of the limiter 506 will be described. The control signal generation circuit 515 gives the limiter 506 a memory area identification signal 517 indicating either a storage area for the luminance signal Y or a storage area for the motion signal M. Limiter 506 is
Two types of operations are performed according to the memory area identification signal 517.

FIG. 11 shows the luminance signal Y including the start address.
Shows the operation of the limiter 506 when accessing the storage area for.

When the offset value is added to the address pointer and the address is updated, as shown in FIG. 11A, if the updated address A exceeds the boundary value B, the limiter 506 changes the address. Address A- (B + 1) instead of A
Is output. Also, when the offset value is subtracted from the address pointer and the address is updated, as shown in FIG. 11B, if the updated address A is less than the start address, the limiter 506 causes the address A Instead, it outputs the address A + B + 1.

FIG. 12 shows the motion signal M including the final address.
Shows the operation of the limiter 506 when accessing the storage area for.

When the offset value is added to the address pointer to update the address, as shown in FIG. 12A, if the updated address A exceeds the final address C, the limiter 506 changes the address. Instead of A, the address A-
Output C + B. In addition, when the offset value is subtracted from the address pointer to update the address, as shown in FIG.
When the updated address A is less than the boundary B + 1, as shown in, the limiter 506 outputs the address A-B + C instead of the address A.

Thus, in both the storage area for the luminance signal Y and the storage area for the motion signal M,
The address pointer can be rotated and incremented.

As described above, in this embodiment, like the luminance signal Y and the motion signal M, signals with different numbers of bits and signals with different numbers of fields can be assigned to the respective storage areas in one memory space. In each storage area, each address pointer can be incremented at a different speed from each other, and the memory space can be effectively used.

Although the memory space is divided into two areas in this embodiment, it may be divided into any number of areas as long as it is divided into a plurality of areas. Further, the reference address is not limited to one, and one may be provided in each storage area. Further, the operation of the limiter 506 of this embodiment may be applied to the second and third embodiments.

(Fifth Embodiment) FIG. 13 shows a memory address generator according to a fifth embodiment of the present invention. In the fifth embodiment, the memory space is logically divided into two,
In addition to accessing each of the two divided storage areas, the address is started from 0 in each of the storage areas. For this purpose, a bit inversion circuit 518 is inserted between the selector 509 and the latch 519, the addition / subtraction identification signal 514 is added to the limiter 506, and the memory area identification signal 517 is added to the limiter 506.
And added to the bit inversion circuit 518.

In FIG. 13, reference numeral 500 denotes an input terminal for inputting a register update start signal (V blanking start signal), and 5
01 is an input terminal for inputting the address generation timing signal,
502 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 504 is a selector for selecting and outputting each value A, B, C, D in the address update register 503 and a fixed value "1",
505 is an arithmetic unit, 506 is a limiter for limiting the address of the arithmetic result of the arithmetic unit 505 within the memory space, 507 is an address update circuit, and 508 is an address register for storing each memory address corresponding to each address pointer. , 509 is a selector for selecting each memory address in the address register 508, 518 is a bit inverting circuit which can select whether to output the selector 509 and output it as it is or invert it and output 510, which outputs the memory address Terminal, 519 is a latch that holds the output of the bit inverting circuit 518, and 515 is a computing unit
505, each selector 504, 509, limiter 506, address register 508, control signal generation circuit for controlling bit inverting circuit 518 and latch 519, 511 is an update register selection signal for controlling selector 504, 512 is an address register for controlling address register 508 A load signal, 513 is an address register selection signal for controlling the selector 509, 520 is an address load signal indicating the timing of loading an address to the selector 519, 514 is an addition / subtraction identification signal for instructing the type of operation of the arithmetic unit 505, 517 Is a memory area identification signal.

In this embodiment, the operation other than the memory area identification signal 517, the limiter 506 and the bit inversion circuit 518, that is, the mechanism of generating and updating a plurality of address pointers is the same as that of the first embodiment, and therefore, here, The description is omitted.

FIG. 14 shows a 4-bit memory space, which is divided by a boundary value B into a storage area 0 containing the start address "0000" and a storage area 1 containing the final address "1111".

Here, the memory space is divided into two storage areas, but the address is updated based on the address "0000" in both storage areas. That is, as shown in FIG. 14, the absolute address is applied to the storage area 0, the logical address obtained by inverting the absolute address is applied to the storage area 1, and the absolute address "1" is applied.
It is assumed that the logical address "0000", which is the inverse of "111", is the reference address.

Next, the operation of the bit inverting circuit 518 will be described. First, the limiter 506 includes a memory area identification signal 517.
Is input, which determines which of storage area 0 and storage area 1 is to be accessed. As is clear from the description of the fourth embodiment, the address of the calculation result of the calculator 505 is the limiter 506, the address register 508, the selector 509.
Is input to the bit inverting circuit 518. The bit inversion circuit 518 inputs the memory area identification signal 517, and if the memory area identification signal 517 indicates the storage area 0, outputs the address as it is, and the memory area identification signal 517 indicates the storage area 1. If so, all bits of the address are inverted and output. This address is output from the output terminal 510 as a memory address at a predetermined timing via the latch 519. By this operation, the address pointer can be assigned to the storage area 0 and the storage area 1.

Next, the operation of the limiter 506 will be described. Figure 1
5 shows the operation of the limiter 506 when accessing the storage area 0 including the absolute address "0000".

When the offset value is added to the address pointer to update the address, if the updated address A exceeds the boundary value B as shown in FIG. 15 (a), the limiter 506 changes the address. Instead of A, the address A- (B + 1) =
Output A + not (B). However, not () is the bit in () inverted. Also, when the offset value is subtracted from the address pointer to update the address,
As shown in 5 (b), when the updated address A is less than the absolute address "0000", the limiter 506 outputs the address A + B + 1 instead of the address A.

FIG. 16 shows the operation of the limiter 506 when accessing the storage area 1 including the absolute address "1111".

When the offset value is added to the address pointer and the address is updated, as shown in FIG. 16A, if the updated address A is less than the logical address "0000", the limiter 506 , Instead of address A,
The address A + B '+ 1 = A + not (B) is output. However, B'is the boundary value of the storage area 1 and is equal to not (B) -1. Further, when the offset value is added to the address pointer and the address is updated, as shown in FIG. 16B, when the updated address A exceeds the logical address B ′, the limiter 506
Instead of address A, address A- (B '+ 1) = A-not (B) = A + B
Output +1.

By carrying out such a processing, the address can be started from "0000" with reference to the address "0000" in each of the storage areas 0 and 1. Further, the limiter 506 can be realized with a simple circuit configuration because its output is limited to any of A, A + B + 1, and A + not (B).

As described above, the memory is divided into two by a single boundary.
When dividing into one storage area, by introducing a logical address, any storage area can be accessed equally. Further, the circuit configuration of the limiter is not significantly complicated and the scale is not increased.

The reference address is not limited to one, and there may be one reference address in each area. Further, the operation of the limiter 506 of this embodiment may be applied to the second and third embodiments, and it may be used for other circuit configurations as a method of dividing one memory space.

(Sixth Embodiment) FIG. 17 shows a memory address generating apparatus according to a sixth embodiment of the present invention. In the sixth embodiment, a plurality of asynchronous signals are written in or read from one memory. For this purpose, the bit inverting circuit 518 is connected between the selector 509 and the latch 519.
To the asynchronous address register 521 and selector 522.
Is provided.

In FIG. 17, reference numeral 500 denotes an input terminal for inputting a register update start signal (V blanking start signal), and 5
01 is an input terminal for inputting the address generation timing signal,
502 is an input terminal for inputting a pointer identification signal, 503 is an address update register, 504 is a selector for selecting and outputting each value in the address update register 503, fixed values "1" and "0",
505 is an arithmetic unit, 506 is a limiter for limiting the address of the arithmetic result of the arithmetic unit 505 within the memory space, 507 is an address update circuit, and 508 is an address register for storing each memory address corresponding to each address pointer. , 509 is a selector for selecting each memory address in the address register 508, 518 is a bit inverting circuit which can select whether to output the selector 509 and output it as it is or invert it and output 510, which outputs the memory address Terminal, 519 is a latch that holds the output of the bit inverting circuit 518, and 515 is a computing unit
505, selectors 504 and 509, limiter 506, address register 508, bit inverting circuit 518, selector 522 and latch 5
Control signal generation circuit for controlling 19; 511, update register selection signal for controlling selector 504; 512, address register 5
Address register load signal for controlling 08, 513 for address register selection signal for controlling selector 509, 514 for addition / subtraction identification signal for instructing the type of operation of arithmetic unit 505, 517 for memory area identification signal, and 524 for asynchronous system Input terminal to input V blanking start signal, 521 is selector 5
The asynchronous address register for storing the address from 09 in response to the asynchronous V blanking start signal from the input terminal 524, 522 is the address from the selector 509 and the address from the asynchronous address register 521 from the control signal generation circuit 515. Selector that switches in response to an asynchronous select signal, 52
0 is an address load signal indicating the timing of loading an address to the selector 519, and 523 is an asynchronous selection signal for switching the selector 522.

In this embodiment, writing and reading of the video signal of the synchronous system 1 and writing and reading of the video signal of the asynchronous system 2 which is not synchronized with the video signal of the synchronous system 1 are performed.

As in the fifth embodiment, the memory space is divided into storage area 0 and storage area 1 as shown in FIG. 14, absolute addresses are applied to storage area 0, and absolute addresses are applied to storage area 1. The logical address that is inverted is applied.

The address update register 503 has a storage area 0
The offset values corresponding to the address pointers W1 and R1 and the offset value corresponding to the read address pointer ASR of the storage area 1 are stored. In addition, the address register 508 includes the address pointers W1 and R1 of the storage area 0.
Each address corresponding to 1 and each address corresponding to each address pointer ASW, ASR of the storage area 1 are stored.

When writing and reading the video signal of the synchronous system 1, the storage area 0 is used. The bit inverting circuit 518 outputs the address from the selector 509 without inverting it. Further, the selector 522 selects the address from the selector 509 and gives this address to the arithmetic unit 505. Therefore, the address increment and update is
This is exactly the same as in the first embodiment. The operation of the limiter 509 is exactly the same as that of the fifth embodiment.

Next, the read and write operations of the video signal of the asynchronous system 2 will be described.

First, the generation of the write address of the video signal of the asynchronous system 2 will be described. Since the speed at which the asynchronous address pointer ASW advances differs from that at the synchronous address, a dedicated area is allocated in the memory space. In this embodiment, the storage area 1 is assigned. In addition, the address register 508
The write and read addresses of the asynchronous system 2 corresponding to the address pointers ASW and ASR are stored.

The control signal generation circuit 515 has the input terminals 501, 5
When it is determined that access to the address corresponding to the write address pointer ASW is requested based on the address generation timing signal and the pointer identification signal from 02, the selector 509, the bit inversion circuit 518, and the selector 52.
2 and the limiter 506 are controlled to generate an address corresponding to the write address pointer ASW. That is, the selector 509 selects the address corresponding to the address pointer ASW. Further, since writing and reading of the asynchronous system 2 are performed on the storage area 1, the limiter 509 performs the operation shown in FIG. 16, and the bit inverting circuit 518 inverts the address from the selector 509 and outputs it. Furthermore, selector 522
Selects the address from selector 509, selector 504
Selects the value "1". The arithmetic unit 505 increments the address corresponding to the write address pointer ASW by "1".

The generation timing of the address pointer ASW is instructed by the address generation timing signal and is determined in synchronization with the video signal of the asynchronous system 2.

Thus, in the state where the address corresponding to the write address pointer ASW is being generated, the control signal generation circuit 515 receives the V blanking start signal from the input terminal 500, but the address pointer ASW in the address register 508. Is not updated, that is, the address is not updated with the offset value. That is, the writing of the asynchronous system 2 is only increment, and the address pointer circulates in the storage area 1 of the memory space.

Then, the asynchronous system 2 written in the storage area 1
The operation for reading the video signal of 1 in synchronization with the video signal of the synchronous system 1 will be described.

Since the video signal of the asynchronous system 2 and the video signal of the synchronous system 1 are not synchronized with each other, when reading each video signal, each video signal written in the storage area 1 is made to be substantially synchronized with each other. Selectively skip frames, 2
By reading again, the frequency difference between the video signals is absorbed.

FIG. 18 shows each frame when the write and read field frequencies are different. The frame is shown so that the EVEN / ODD relationship of the field is not disturbed even in the case of an interlaced signal.

FIG. 18A shows the case where the write field frequency is higher than the read field frequency, that is, the frequency of the asynchronous system 2 is higher than the frequency of the synchronous system 1, and FIG. 18B shows the opposite case. Is shown. In either case, frame reading is performed from the start address of the frame in which writing is being performed, and frame writing and reading are performed in parallel.

For example, in the case of FIG. 18 (a), the written frame is read as it is up to 5 frames.
Since writing of 7 frames has already started before reading the frames, 6 frames are skipped,
Reading is performed.

In such an operation, the start address of the write frame is held at the time of disclosure of the frame, and 1
When the reading of the frame is completed, the held start address is used as it is as the start address of the next frame to be read. As a result, it is possible to skip frames and convert an asynchronous signal into a synchronous signal.

On the other hand, in the case of FIG.
In other words, if the write field frequency is lower than the read field frequency and applied as it is, the reading of one frame may be completed before the writing of one frame is completed. In this case, the video signal cannot be read correctly. In FIG. 18 (b), the part that could not be read correctly is indicated by NG.

In order to avoid this overtaking operation, the V blanking start signal of the asynchronous system 2 used for writing is given a width corresponding to the period of the timing at which the read frame overtakes the written frame. The width corresponding to the period portion of this timing is the time portion corresponding to the difference between the two field frequencies.

In this case, at the time of updating the read address, if the V blanking start signal of the asynchronous system 2 is "Low", the head address of the frame held at the start of writing the frame is unchanged. When the V blanking start signal of the asynchronous system 2 is "High" as the start address of the next frame to be read, the start address of the frame one frame before the start address of the frame held at the start of writing the frame Is the start address of the next frame to be read.

As a result, even if the write field frequency is lower than the read field frequency,
As shown at the bottom of 8 (b), an asynchronous signal can be converted into a synchronous signal without the read frame overtaking the written frame.

The operation shown in FIG. 18 so far is performed as follows. First, the asynchronous address register 521
Each time an asynchronous V blanking start signal is input from the input terminal 524, the address corresponding to the address pointer ASW output from the selector 509, that is, the head address of the frame at the start of writing the frame is stored.
In response to the V blanking start signal from the input terminal 500,
When updating each address in the address register 508, if the asynchronous V blanking start signal from the input terminal 524 is "Low", the selector 522 determines the address from the asynchronous address register 521, that is, the frame write start time. Select the start address of the frame. Further, the selector 504 selects the fixed value “0”. Therefore, the calculator
The 505 outputs the address from the asynchronous address register 522 as it is.

Further, when updating each address in the address register 508 in response to the V blanking start signal from the input terminal 500, if the asynchronous V blanking start signal is "High", the selector 522 is The address from the asynchronous address register 521, that is, the start address of the frame at the time of starting writing of the frame is selected. Also,
The selector 504 sets the offset value for one frame corresponding to the read address pointer ASR to the address update register 5
Select from 03. At this time, the arithmetic unit 505 is instructed to subtract by the addition / subtraction identification signal 514, and the address pointer A from the address from the asynchronous address register 521.
The offset value corresponding to SR is subtracted, and the start address at which writing one frame before has started is calculated and output.

When an address corresponding to the read address pointer ASR is requested in response to the address generation timing signal and the pointer identification signal input from the input terminals 501 and 502, the selector 509 causes the address register 508 to send the address pointer. The address corresponding to the ASR is selected, and the bit inverting circuit 518 inverts the address from the selector 509 and outputs it as a memory address for reading from the storage area 1. At this time, the selector
522 selects the address from the selector 509, and the selector 504 selects the fixed value "1". Therefore, the calculator 50
5 increments the address by "1".

By the above operation, the asynchronous video signal can be written in the memory, and the asynchronous video signal can be read in synchronization with the synchronous video signal.

When the address output from the asynchronous address register 521 is used as it is as an update value,
Although the fixed value "0" is selected by the selector 504, instead of performing the arithmetic operation by the arithmetic unit 505 on the address from the asynchronous address register 521, the address is directly output from the arithmetic unit 505. May be.

The logic of the asynchronous V blanking start signal and the storage area for writing and reading the asynchronous video signal are not limited to those in this embodiment.
Furthermore, this embodiment is based on the fifth embodiment, but is applied to a circuit having another configuration as an address generating method using a memory for synchronizing the video signals of two different field frequencies. May be.

[0151]

As described above, according to the present invention, it is not necessary to prepare the arithmetic means for the number of address pointers, and a plurality of address pointers can be updated by only one arithmetic means. Can be realized on a small circuit scale, and its practical effect is great. Further, by updating a plurality of addresses based on a predetermined relative relationship, it is possible to allocate each address in the memory space while always maintaining the relative relationship of each address.

Further, by calculating the update of a plurality of addresses with the relative value with respect to the reference address, even if the calculation is erroneous at the time of updating the address, at the time of the next address updating, it becomes possible to re-direct each address to the correct relative relationship. , Its practical effect is great.

Further, by reversing the updating direction of the reference address and the updating direction of other addresses, it is not necessary to provide a register for storing the code information of the arithmetic unit, and the number of bits of the register can be reduced. Furthermore, the number of bits of the arithmetic unit can be reduced, and its practical effect is great.

As for necessary addresses among the addresses, a horizontal offset can be given to the addresses by updating for each H blanking start signal, and a small screen is formed on the memory, for example. It becomes possible and the practical effect is great.

In addition, when writing and reading each video signal having a different number of bits and a required number of fields,
Forming multiple storage areas in one memory space,
Since the pointer is advanced at different speeds for each storage area, the memory space can be effectively used,
Its practical effect is great.

When the memory space is divided into two storage areas at a single boundary, both storage areas can be treated in the same way by introducing a logical address, so that the circuit scale can be reduced. , Its practical effect is great.

Even when a plurality of asynchronous video signals are written and read, an address is generated by one memory address generator, and an asynchronous signal can be read by one memory consistently with a synchronous system. Is possible, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory address generator of the present invention.

FIG. 2 is a diagram showing address update in the first embodiment.

FIG. 3 is a diagram showing an operation of a limiter in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the memory address generator of the present invention.

FIG. 5 is a diagram showing address updating in the second embodiment.

FIG. 6 is a diagram showing an operation of a limiter in the second embodiment.

FIG. 7 is a block diagram showing a third embodiment of the memory address generator of the present invention.

FIG. 8 is a diagram showing address updating in the third embodiment.

FIG. 9 is a block diagram showing a fourth embodiment of the memory address generator of the present invention.

FIG. 10 is a diagram showing an address space in the fourth embodiment.

FIG. 11 is a diagram showing an operation of a limiter in the fourth embodiment.

FIG. 12 is a diagram showing an operation of a limiter in the fourth embodiment.

FIG. 13 is a block diagram showing a fifth embodiment of the memory address generation device of the present invention.

FIG. 14 is a diagram showing an address space in the fifth embodiment.

FIG. 15 is a diagram showing an operation of a limiter in the fifth embodiment.

FIG. 16 is a diagram showing another operation of the limiter in the fifth embodiment.

FIG. 17 is a block diagram showing a sixth embodiment of the memory address generation device of the present invention.

FIG. 18 is a diagram showing a frame synchronization operation in the sixth embodiment.

[Explanation of symbols]

500,501,502,516,524 Input terminals 503 Address update register 504,509,522 Selector 505 arithmetic unit 506 limiter 507 Address update circuit 508 address register 510 output terminal 511 Update register selection signal 512 address register load signal 513 Address register selection signal 514 Addition / subtraction identification signal 515 Control signal generation circuit 517 Memory area identification signal 518-bit inversion circuit 519 latch 521 Asynchronous Address Register 523 Asynchronous selection signal

─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masahiro Tani 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor ▲ Toku ▼ Naoya Nagata 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Sangyo Co., Ltd. (72) Inventor Kenta Samukawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroshi Miyaguchi 3-6-12 Kita-Aoyama Minato-ku, Tokyo Aoyama Fuji Building Japan Within Instruments Co., Ltd. (56) Reference JP-A-9-55869 (JP, A) JP-A-7-302073 (JP, A) JP-A-5-191782 (JP, A) JP-A-8-154227 ( JP, A) JP 5-328247 (JP, A) JP 9-128959 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12 / 00-12 / 02 H04N 5/073 H04N 5 / 76,5 / 80-5 / 907 G09G 5/00-5/42

Claims (6)

(57) [Claims] 1. Multiple ads for accessing memory.
A memory address generation device for generating a response, and at a predetermined timing, N (N is a natural number) addresses
Address to be updated based on the predetermined relative relationship of addresses
An update means is provided, and the predetermined relative relationship of each address is K (K is a natural number).
It is represented by a predetermined value, and the address updating means uses the K addresses (K
Was updated by the predetermined value is a natural number), the predetermined value of K (K is a natural number) is a offset value, said address updating means, in advance from the address
Calculate the specified address based on the offset value
After the reference address selectively Update by, by calculation based on the calculation result and the offset value of the reference address, it updates the address other than the reference address, updated the memory address generator to increment the respective address apparatus. 2. The address updating means includes an updating direction of one of the respective addresses serving as the reference address,
Reverse the update direction of the other one of the above addresses
Address is updated by using the update direction
2. The memory address generating device according to claim 1 , wherein the information of the means is input . 3. A first synchronization signal and a second synchronization signal having different frequencies are provided, and the address updating means selectively updates each of the addresses by selectively using the first and second synchronization signals. The memory address generator according to claim 1 . 4. The address updating means logically divides the address space of one memory into a plurality of areas, and increments the respective address pointers in respective different ways for each area, 4. The memory address generating device according to claim 1, which generates an address. 5. The address updating means divides the address space of one memory into a first area including an address 0 and a second area including an end address with a single boundary value, and 0 is applied to both areas. 5. The memory address generation device according to claim 4 , wherein an address operation is performed with a logical address based on an address, and a real address is output by inverting the operation result for the second area. 6. An M-type (M is a natural number) synchronization signal and a K-type (K is a natural number) asynchronous signal asynchronous with the synchronization signal are provided, and the address updating means is an address of one memory. A dedicated area for writing and reading asynchronous signals is provided in the space, and the read addresses of the asynchronous signals are held at predetermined timings and the write and read frequencies. Equivalent to the difference
The memory address generation device according to claim 5 , wherein the memory address generation device is calculated based on an identification signal .